mirror of
https://github.com/romychs/SprinterESP.git
synced 2025-11-01 23:36:00 +03:00
296 lines
5.0 KiB
C
296 lines
5.0 KiB
C
#pragma nonrec
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#include <stdio.h>
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#include <conio.h>
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#include <dos.h>
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unsigned port;
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char b;
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char save_mmu3;
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#define port_isa 0x9FBD
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#define port_system 0x1FFD
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#define isa_addr_base 0xC000
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#define com3_addr_base 0x3E8
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#define emm_win_p3 0xE2
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#define port_serial 0xC3E8
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#define RBR port_serial
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#define THR port_serial
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#define IER port_serial+1
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#define IIR port_serial+2
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#define FCR port_serial+2
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#define LCR port_serial+3
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#define MCR port_serial+4
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#define LSR port_serial+5
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#define MSR port_serial+6
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#define SCR port_serial+7
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#define DLL port_serial
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#define DLM port_serial+1
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#define AFR port_serial+2
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/*
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#define BAUD_RATE 115200
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#define XIN_FREQ 14745600
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#define DIVISOR XIN_FREQ / (BAUD_RATE * 16)
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*/
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/**
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* Small delay
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*/
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delay() {
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unsigned ctr;
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for (ctr=0; ctr<2000; ctr++) {
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}
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}
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/**
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* Reset ISA device
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*/
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reset_isa() {
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outp(port_isa, 0xc0); // RESET=1 AEN=1
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delay();
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outp(port_isa,0); // RESET=0 AEN=0
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delay();
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delay();
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}
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/*
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* Open access to ISA ports as memory
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*/
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open_isa() {
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save_mmu3 = inp(emm_win_p3);
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outp(port_system, 0x11);
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outp(emm_win_p3, 0xd4);
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outp(port_isa, 0);
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}
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/*
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* Close access to ISA ports
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*/
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close_isa() {
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outp(port_system, 0x01);
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outp(emm_win_p3, save_mmu3);
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}
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/*
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* Init ISA device
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*/
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init_isa() {
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reset_isa(); // just only reset
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}
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unsigned addr;
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char lcr;
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char *ptr;
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/*
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* Init UART device TL16C550
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*/
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init_serial() {
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open_isa();
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mset(FCR, 0x01); // 8 byte FIFO buffer
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mset(FCR, 0x81);
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mset(IER, 0x00); // Disable interrupts
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mset(LCR, 0x83); // enable Baud rate latch
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mset(DLL, 0x08); // 8 - 115200;
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mset(DLM, 0x00);
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mset(LCR, 0x03); // dis Baud rate latch & 8N1
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// reset ESP
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mset(MCR, 0x06); // ESP -PGM=1, -RTS=0
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delay();
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mset(MCR, 0x02); // ESP -RST=1, -RTS=0
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delay();
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close_isa();
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}
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char read_reg(reg)
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unsigned reg;
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{
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char rb;
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open_isa();
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rb = mget(reg);
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close_isa();
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return rb;
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}
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void write_reg(reg, b)
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unsigned reg;
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char b;
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{
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open_isa();
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mset(reg, b);
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close_isa();
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}
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char *scr_ptr = SCR;
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void write_sr(b)
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char b;
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{
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open_isa();
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*scr_ptr = b;
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close_isa();
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}
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char read_sr() {
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char rb;
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open_isa();
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rb = *scr_ptr;
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close_isa();
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return rb;
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}
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void wait_tr() {
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unsigned w;
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char ls;
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w = 0;
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ls = read_reg(LSR);
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while ((ls & 0x20) == 0 && w<100) {
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delay(20);
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ls = read_reg(LSR);
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w++;
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}
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}
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/*
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* Empty receiver FIFO buffer
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*/
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void empty_rs() {
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open_isa();
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mset(FCR, 0x83);
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close_isa();
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}
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/*
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* Wait byte in receiver fifo
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*/
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void wait_rs() {
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unsigned w;
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char ls;
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w = 0;
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ls = read_reg(LSR);
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while ((ls & 0x01) == 0 && w<1000) {
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delay();
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ls = read_reg(LSR);
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w++;
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}
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}
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char tb;
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char rr;
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unsigned ctr;
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unsigned r;
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char* buff = "AT+GMR\r\n\0";
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char* tbuf;
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char rbuf[1024];
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main() {
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char ok;
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printf("\nInit ISA\n");
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init_isa();
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printf("\nInit serial\n");
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init_serial();
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r = port_serial;
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rr = 0;
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for (ctr=0; ctr<=7; ctr++) {
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tb = read_reg(r);
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printf("REG["); hex8(rr);
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printf("]="); hex8(tb);
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printf("\n");
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r++;
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rr++;
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}
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r = port_serial;
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rr = 0;
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write_reg(LCR,0x83);
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for (ctr=0; ctr<3; ctr++) {
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tb = read_reg(r);
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printf("REG[1");
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hex8(rr);
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printf("]=");
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hex8(tb);
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printf("\n");
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r++;
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rr++;
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}
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write_reg(LCR,0x03);
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// Wait ESP reload
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for (ctr=0; ctr<400; ctr++) {
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delay();
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}
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printf("\nClear receiver buffer");
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empty_rs();
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printf("\nGet version\n");
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tbuf = buff;
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while (*tbuf != '\0') {
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wait_tr();
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tb = read_reg(LSR);
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if ((tb & 0x20) == 0) {
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printf(".TXNR.");
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} else {
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write_reg(THR, *tbuf++);
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}
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}
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ctr = 0;
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r = 0;
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ok = 0;
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disable();
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open_isa();
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do {
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rr = mget(LSR);
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if ((rr & 0x80) != 0) {
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close_isa();
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printf("\nReceiver error:");
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rr = (rr>>1) & 0x07;
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hex8(rr);
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break;
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} else {
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if ((rr & 0x01) == 1) {
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tb = mget(RBR);
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rbuf[ctr++] = tb;
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if (ok == 0 && tb == 'O') {
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ok = 1;
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}
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if (ok == 1 && tb == 'K') {
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ok = 2;
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} else {
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ok = 0;
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}
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r = 0;
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} else {
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r++;
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}
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}
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} while (ok<2 && r<10000 && ctr<1024);
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enable();
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close_isa();
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printf("\nctr="); dec16(ctr);
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printf("\nr="); dec16(r);
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printf("\nReceived:\n");
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printf(rbuf);
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}
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