mirror of
https://github.com/romychs/SprinterESP.git
synced 2025-04-18 17:52:45 +03:00
433 lines
9.4 KiB
NASM
433 lines
9.4 KiB
NASM
; ======================================================
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; Library for Sprinter-WiFi ESP ISA Card
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;
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; By Romych's, 2024 (c)
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; ======================================================
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;ISA_BASE_A EQU 0xC000 ; Базовый адрес портов ISA в памяти
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PORT_UART EQU 0x03E8 ; Базовый номер порта COM3
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PORT_UART_A EQU ISA_BASE_A + PORT_UART ; Порты чипа UART в памяти
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; UART TC16C550 Registers in memory
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REG_RBR EQU PORT_UART_A + 0
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REG_THR EQU PORT_UART_A + 0
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REG_IER EQU PORT_UART_A + 1
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REG_IIR EQU PORT_UART_A + 2
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REG_FCR EQU PORT_UART_A + 2
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REG_LCR EQU PORT_UART_A + 3
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REG_MCR EQU PORT_UART_A + 4
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REG_LSR EQU PORT_UART_A + 5
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REG_MSR EQU PORT_UART_A + 6
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REG_SCR EQU PORT_UART_A + 7
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REG_DLL EQU PORT_UART_A + 0
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REG_DLM EQU PORT_UART_A + 1
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REG_AFR EQU PORT_UART_A + 2
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; UART TC16C550 Register bits
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MCR_DTR EQU 0x01
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MCR_RTS EQU 0x02
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MCR_RST EQU 0x04
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MCR_PGM EQU 0x08
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MCR_LOOP EQU 0x10
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MCR_AFE EQU 0x20
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LCR_WL8 EQU 0x03 ; 8 bits word len
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LCR_SB2 EQU 0x04 ; 1.5 or 2 stp bits
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LCR_DLAB EQU 0x80 ; Enable Divisor latch
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FCR_FIFO EQU 0x01 ; Enable FIFO for rx and tx
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FCR_RESET_RX EQU 0x02 ; Reset Rx FIFO
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FCR_RESET_TX EQU 0x04 ; Reset Tx FIFO
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FCR_DMA EQU 0x08 ; Set -RXRDY, -TXRDY to "1"
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FCR_TR1 EQU 0x00 ; Trigger on 1 byte in fifo
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FCR_TR4 EQU 0x40 ; Trigger on 4 bytes in fifo
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FCR_TR8 EQU 0x80 ; Trigger on 8 bytes in fifo
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FCR_TR14 EQU 0xC0 ; Trigger on 14 bytes in fifo
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LSR_DR EQU 0x01 ; Data Ready
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LSR_OE EQU 0x02 ; Overrun Error
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LSR_PE EQU 0x04 ; Parity Error
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LSR_FE EQU 0x08 ; Framing Error
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LSR_BI EQU 0x10 ; Break Interrupt
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LSR_THRE EQU 0x20 ; Transmitter Holding Register
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LSR_TEMT EQU 0x40 ; Transmitter empty
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LSR_RCVE EQU 0x80 ; Error in receiver FIFO
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; Speed divider for UART
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BAUD_RATE EQU 115200 ; Скорость соединения с ESP8266
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XIN_FREQ EQU 14745600 ; Частота генератора для TL16C550
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DIVISOR EQU XIN_FREQ / (BAUD_RATE * 16) ; Делитель частоты для передачи/приема данных
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RS_BUFF_SIZE EQU 2048 ; Receive buffer size
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MAX_BUFF_SIZE EQU 16384
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LSTR_SIZE EQU 20 ; Size of buffer for last response line
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LF EQU 0x0A
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CR EQU 0x0D
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; --
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RES_OK EQU 0
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RES_ERROR EQU 1
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RES_FAIL EQU 2
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RES_TX_TIMEOUT EQU 3
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RES_RS_TIMEOUT EQU 4
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RES_CONNECTED EQU 5
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RES_NOT_CONN EQU 6
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RES_ENABLED EQU 7
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RES_DISABLED EQU 8
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MODULE WIFI
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; ------------------------------------------------------
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; Find TL550C in ISA slot
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; Out: CF=1 - Not found, CF=0 - ISA.ISA_SLOT found in slot
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; ------------------------------------------------------
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UART_FIND
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PUSH HL
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XOR A
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CALL UT_T_SLOT
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JR Z, UF_T_FND
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LD A,1
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CALL UT_T_SLOT
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JR Z, UF_T_FND
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SCF
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UF_T_FND
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POP HL
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RET
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; Test slot, A - ISA Slot no. 0 or 1
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UT_T_SLOT
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LD (ISA.ISA_SLOT), A
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LD HL, REG_IER
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CALL UART_READ
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AND 0xF0
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RET
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; ------------------------------------------------------
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; Init UART device TL16C550
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; ------------------------------------------------------
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UART_INIT
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PUSH AF
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PUSH HL
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CALL ISA.ISA_OPEN
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LD A, FCR_TR14 | FCR_FIFO ; Enable FIFO buffer, trigger to 14 byte
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LD (REG_FCR),A
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XOR A
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LD (REG_IER), A ; Disable interrupts
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; Set 8bit word and Divisor for speed
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LD A, LCR_DLAB | LCR_WL8
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LD (REG_LCR), A ; Enable Baud rate latch
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LD A, DIVISOR
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LD (REG_DLL), A ; 8 - 115200
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XOR A
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LD (REG_DLM), A
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LD A, LCR_WL8 ; 8bit word, disable latch
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LD (REG_LCR), A
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CALL ISA.ISA_CLOSE
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POP HL
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POP AF
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RET
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; ------------------------------------------------------
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; Read TL16C550 register
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; Inp: HL - register
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; Out: A - value from register
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; ------------------------------------------------------
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UART_READ
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IF DEBUG==0
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CALL ISA.ISA_OPEN
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LD A, (HL)
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CALL ISA.ISA_CLOSE
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RET
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ELSE
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; --- DEBUG
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LD HL,(RX_PTR)
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LD A,(HL)
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OR A
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JR NZ, RX_RET
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LD BC, RX_MSG
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LD (HL),BC
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JR UART_READ
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RX_RET
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INC HL
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LD (RX_PTR),HL
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RET
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RX_PTR DW RX_MSG
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RX_MSG DB "WiFi module\r\nOK\r\n",0
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ENDIF
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; ------------------------------------------------------
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; Write TL16C550 register
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; Inp: HL - register, E - value
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; ------------------------------------------------------
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UART_WRITE
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CALL ISA.ISA_OPEN
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LD (HL), E
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CALL ISA.ISA_CLOSE
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RET
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; ------------------------------------------------------
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; Wait for transmitter ready
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; Out: CF=1 - tr not ready, CF=0 ready
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; ------------------------------------------------------
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UART_WAIT_TR
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PUSH BC, HL
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CALL ISA.ISA_OPEN
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LD BC, 200
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LD HL, REG_LSR
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WAIT_TR_R
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LD A,(HL)
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AND A, LSR_THRE
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JP NZ,WAIT_TR_E
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CALL UTIL.DELAY_1MS
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DEC BC
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LD A, C
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OR B
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JP NZ,WAIT_TR_R
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SCF
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WAIT_TR_E
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CALL ISA.ISA_CLOSE
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POP HL, BC
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RET
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; ------------------------------------------------------
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; Transmit byte
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; Inp: E - byte
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; Out: CF=1 - Not ready
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; ------------------------------------------------------
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UART_TX_BYTE
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CALL UART_WAIT_TR
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JP C, UTB_NOT_R
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LD HL, REG_THR
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CALL UART_WRITE
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XOR A
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UTB_NOT_R
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RET
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; ------------------------------------------------------
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; char uart_tx_buffer(char* tbuff, int size)
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; Inp: HL -> buffer, BC - size
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; Out: CF=0 - Ok, CF=1 - Timeout
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; ------------------------------------------------------
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IF DEBUG==0
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UART_TX_BUFFER
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PUSH BC,DE,HL
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LD DE, REG_THR
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CALL ISA.ISA_OPEN
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UTX_NEXT
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; buff not empty?
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LD A, B
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OR C
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JR Z,UTX_EMP
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; check transmitter ready
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CALL UART_WAIT_TR
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JR C, UTX_EMP
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; transmitt byte
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LD A,(HL)
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INC HL
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LD (DE),A
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DEC BC
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JR UTX_NEXT
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; CF=0
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XOR A
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UTX_EMP
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CALL ISA.ISA_CLOSE
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POP HL,DE,BC
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RET
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ELSE
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; --- DEBUG
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UART_TX_BUFFER
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XOR A
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RET
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ENDIF
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; ------------------------------------------------------
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; Empty receiver FIFO buffer
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; ------------------------------------------------------
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UART_EMPTY_RS
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PUSH AF
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CALL ISA.ISA_OPEN
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LD A, FCR_TR14 | FCR_RESET_RX | FCR_FIFO
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LD (REG_FCR), A
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CALL ISA.ISA_CLOSE
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POP AF
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RET
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; ------------------------------------------------------
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; Wait byte in receiver fifo
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; Inp: BC - Wait ms
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; Out: CF=1 - Timeout, FIFO is EMPTY
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; ------------------------------------------------------
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IF DEBUG==0
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UART_WAIT_RS1
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PUSH BC,HL
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WAIT_MS+* LD BC,0x0000
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JR UVR_NEXT
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ENDIF
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UART_WAIT_RS
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PUSH BC,HL
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UVR_NEXT
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LD HL, REG_LSR
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CALL UART_READ
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AND LSR_DR
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JR Z,UVR_OK
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CALL UTIL.DELAY_1MS
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DEC BC
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LD A,B
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OR A,C
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JR NZ,UVR_NEXT
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UVR_TO
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SCF
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UVR_OK
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POP HL,BC
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IF DEBUG==1
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WAIT_MS
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DW 0
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UART_WAIT_RS1
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AND A ; CF=0
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ENDIF
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RET
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; ------------------------------------------------------
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; Reset ESP module
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; Inp: A != 0 - Full Reset
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; ------------------------------------------------------
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ESP_RESET
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PUSH HL, AF
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CALL ISA.ISA_OPEN
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AND A
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JR Z, ESPR_SHRT
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LD HL, REG_MCR
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LD A, MCR_RST | MCR_RTS ; 0110b ESP -PGM=1, -RST=0, -RTS=0
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LD (HL), A
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CALL UTIL.DELAY
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ESPR_SHRT
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LD A, MCR_AFE | MCR_RTS ; 0x22 -RST = 1 -RTS=0 AutoFlow enabled
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LD (HL), A
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CALL ISA.ISA_CLOSE
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POP AF
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AND A
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JR Z,ESPR_NW
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LD HL,0xFFFF
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CALL UTIL.DELAY
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ESPR_NW
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POP HL
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RET
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; Receive block size
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BSIZE DW 0
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; Received message for OK result
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MSG_OK DB "OK", 0
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; Received message for Error
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MSG_ERROR DB "ERROR", 0
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; Received message for Failure
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MSG_FAIL DB "FAIL", 0
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; ------------------------------------------------------
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; UART TX Command
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; Inp: HL - ptr to command,
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; DE - ptr to receive buffer,
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; BC - wait ms
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; Out: CF=1 if Error
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; ------------------------------------------------------
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UART_TX_CMD
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PUSH BC, DE, HL
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LD A, low RS_BUFF_SIZE
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LD (BSIZE), A
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LD A, high RS_BUFF_SIZE
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LD (BSIZE+1), A
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;LD (RESBUF),DE
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XOR A
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LD (DE), A
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LD (WAIT_MS), BC
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CALL UART_EMPTY_RS
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; HL - Buffer, BC - Size
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CALL UTIL.STRLEN
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CALL UART_TX_BUFFER
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JR NC, UTC_STRT_RX
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; error, transmit timeout
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LD A, RES_TX_TIMEOUT
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JR UTC_RET
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UTC_STRT_RX
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; no transmit timeout, receive response
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; IX - pointer to begin of current line
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LD IXH, D
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LD IXL, E
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LD BC,(BSIZE)
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UTC_RCV_NXT
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; wait receiver ready
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;LD BC,(WAIT_MS)
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CALL UART_WAIT_RS1
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JR NC, UTC_NO_RT
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; error, read timeout
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LD A, RES_RS_TIMEOUT
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JR UTC_RET
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; no receive timeout
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UTC_NO_RT
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; read symbol from tty
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LD HL, REG_RBR
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CALL UART_READ
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CP CR
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JP Z, UTC_RCV_NXT ; Skip CR
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CP LF
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JR Z, UTC_END ; LF - last symbol in responce
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LD (DE),A
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INC DE
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DEC BC
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LD A, B
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OR C
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JR NZ, UTC_RCV_NXT
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UTC_END
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XOR A
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LD (DE),A ; temporary mark end of string
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PUSH DE ; store DE
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POP IY
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PUSH IX
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POP DE ; DE - ptr to begin pf current line
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; It is 'OK<LF>'?
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LD HL, MSG_OK
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CALL UTIL.STRCMP
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JR NC, UTC_RET
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; It is 'ERROR<LF>'?
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LD HL,MSG_ERROR
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CALL UTIL.STRCMP
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JR C, UTC_CP_FAIL
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LD A, RES_ERROR
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; It is 'FAIL<LF>'?
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JR UTC_RET
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UTC_CP_FAIL
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LD HL,MSG_FAIL
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CALL UTIL.STRCMP
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JR C, UTC_NOMSG
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LD A, RES_FAIL
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JR UTC_RET
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UTC_NOMSG
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; no resp message, continue receive
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PUSH IY
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POP DE
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LD A, LF
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LD (DE),A ; change 0 - EOL to LF
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INC DE
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LD IXH,D ; store new start line ptr
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LD IXL,E
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JR UTC_RCV_NXT
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UTC_RET
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POP HL, DE, BC
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RET
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; Buffer to receive response from ESP
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RS_BUFF DS RS_BUFF_SIZE, 0
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ENDMODULE |