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fix disassm IXl IXh loading

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This commit is contained in:
Роман Бойков 2026-04-17 13:48:24 +03:00
parent 3c891c0a04
commit 9bf52f0504
2 changed files with 59 additions and 0 deletions
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42
dis/z80disasm.go
View File

@ -401,16 +401,52 @@ func (d *Disassembler) opocodeDD(op byte) string {
result = "LD (ii" + d.getRel() + ")" + sep + "n" result = "LD (ii" + d.getRel() + ")" + sep + "n"
case 0x39: case 0x39:
result = "ADD ii" + sep + "SP" result = "ADD ii" + sep + "SP"
case 0x44:
result = "LD B" + sep + "iiH"
case 0x45:
result = "LD B" + sep + "iiL"
case 0x46: case 0x46:
result = "LD B" + sep + "(ii" + d.getRel() + ")" result = "LD B" + sep + "(ii" + d.getRel() + ")"
case 0x4C:
result = "LD C" + sep + "iiH"
case 0x4D:
result = "LD C" + sep + "iiL"
case 0x4E: case 0x4E:
result = "LD C" + sep + "(ii" + d.getRel() + ")" result = "LD C" + sep + "(ii" + d.getRel() + ")"
case 0x54:
result = "LD D" + sep + "iiH"
case 0x55:
result = "LD D" + sep + "iiL"
case 0x56: case 0x56:
result = "LD D" + sep + "(ii" + d.getRel() + ")" result = "LD D" + sep + "(ii" + d.getRel() + ")"
case 0x5C:
result = "LD E" + sep + "iiH"
case 0x5D:
result = "LD E" + sep + "iiL"
case 0x5E: case 0x5E:
result = "LD E" + sep + "(ii" + d.getRel() + ")" result = "LD E" + sep + "(ii" + d.getRel() + ")"
case 0x62:
result = "LD iiH" + sep + "D"
case 0x65:
result = "LD IXH" + sep + "IXL"
case 0x66: case 0x66:
result = "LD H" + sep + "(ii" + d.getRel() + ")" result = "LD H" + sep + "(ii" + d.getRel() + ")"
case 0x6A:
result = "LD iiL" + sep + "D"
case 0x6B:
result = "LD iiL" + sep + "E"
case 0x6C:
result = "LD IXL" + sep + "IXH"
case 0x6E: case 0x6E:
result = "LD L" + sep + "(ii" + d.getRel() + ")" result = "LD L" + sep + "(ii" + d.getRel() + ")"
case 0x70: case 0x70:
@ -427,8 +463,14 @@ func (d *Disassembler) opocodeDD(op byte) string {
result = "LD (ii" + d.getRel() + ")" + sep + "L" result = "LD (ii" + d.getRel() + ")" + sep + "L"
case 0x77: case 0x77:
result = "LD (ii" + d.getRel() + ")" + sep + "A" result = "LD (ii" + d.getRel() + ")" + sep + "A"
case 0x7C:
result = "LD A" + sep + "iiH"
case 0x7D:
result = "LD A" + sep + "iiL"
case 0x7E: case 0x7E:
result = "LD A" + sep + "(ii" + d.getRel() + ")" result = "LD A" + sep + "(ii" + d.getRel() + ")"
case 0x86: case 0x86:
result = "ADD A" + sep + "(ii" + d.getRel() + ")" result = "ADD A" + sep + "(ii" + d.getRel() + ")"
case 0x8E: case 0x8E:

17
dis/z80disasm_test.go
View File

@ -112,3 +112,20 @@ func Test_JR_mnn(t *testing.T) {
t.Errorf("Error disassm JR -nn, result '%s', expected '%s'", res, expected) t.Errorf("Error disassm JR -nn, result '%s', expected '%s'", res, expected)
} }
} }
var testLDrIXn = []byte{0xdd, 0x55, 0xdd, 0x7c}
func Test_LD_r_IXn(t *testing.T) {
expected := " 0100 LD D, IXL"
setMemory(0x0100, testLDrIXn)
res := disasm.Disassm(0x0100)
if res != expected {
t.Errorf("Error disassm LD_r_IXn, result '%s', expected '%s'", res, expected)
}
expected = " 0102 LD A, IXH"
res = disasm.Disassm(0x0102)
if res != expected {
t.Errorf("Error disassm LD_r_IXn, result '%s', expected '%s'", res, expected)
}
}