mirror of
https://github.com/romychs/z80go.git
synced 2026-04-16 08:44:20 +03:00
675 lines
15 KiB
Go
675 lines
15 KiB
Go
package dis
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import (
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"fmt"
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"strings"
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"github.com/romychs/z80go"
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)
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type Disassembler struct {
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pc uint16
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core z80go.MemIoRW
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}
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type Disassembly interface {
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Disassm(pc uint16) string
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}
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func NewDisassembler(core z80go.MemIoRW) *Disassembler {
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d := Disassembler{
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pc: 0,
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core: core,
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}
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return &d
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}
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// opcode & 0x07
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var operands = []string{"B", "C", "D", "E", "H", "L", "(HL)", "A"}
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var aluOp = []string{"ADD A" + sep, "ADC A" + sep, "SUB ", "SBC A" + sep, "AND ", "XOR ", "OR ", "CP "}
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const sep = ", "
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func (d *Disassembler) jp(op, cond string) string {
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addr := d.getW()
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if cond != "" {
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cond += sep
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}
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return fmt.Sprintf("%s %s%s", op, cond, addr)
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}
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func (d *Disassembler) jr(op, cond string) string {
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addr := d.pc + 1
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offset := d.getByte()
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if offset&0x80 != 0 {
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addr += 0xFF00 | uint16(offset)
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} else {
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addr += uint16(offset)
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}
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if cond != "" {
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cond += sep
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}
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return fmt.Sprintf("%s %s0x%04X", op, cond, addr)
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}
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func (d *Disassembler) getByte() byte {
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b := d.core.MemRead(d.pc)
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d.pc++
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return b
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}
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func (d *Disassembler) Disassm(pc uint16) string {
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d.pc = pc
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result := fmt.Sprintf(" %04X ", d.pc)
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op := d.getByte()
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switch {
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// == 00:0F
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case op == 0x00:
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result += "NOP"
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case op == 0x01:
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result += "LD BC" + sep + d.getW()
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case op == 0x02:
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result += "LD (BC)" + sep + "A"
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case op == 0x03:
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result += "INC BC"
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case op == 0x04:
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result += "INC B"
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case op == 0x05:
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result += "DEC B"
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case op == 0x06:
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result += "LD B" + sep + d.getB()
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case op == 0x07:
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result += "RLCA"
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case op == 0x08:
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result += "EX AF, AF'"
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case op == 0x09:
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result += "ADD HL" + sep + "BC"
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case op == 0x0A:
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result += "LD A" + sep + "(BC)"
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case op == 0x0B:
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result += "DEC BC"
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case op == 0x0C:
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result += "INC C"
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case op == 0x0D:
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result += "DEC C"
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case op == 0x0E:
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result += "LD C" + sep + d.getB()
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case op == 0x0F:
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result += "RRCA"
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// 10:1F
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case op == 0x10:
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// DJNZ rel
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result += d.jr("DJNZ", "")
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case op == 0x11:
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result += "LD DE" + sep + d.getW()
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case op == 0x12:
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result += "LD (DE)" + sep + "A"
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case op == 0x13:
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result += "INC DE"
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case op == 0x14:
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result += "INC D"
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case op == 0x15:
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result += "DEC D"
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case op == 0x16:
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result += "LD D" + sep + d.getB()
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case op == 0x17:
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result += "RLA"
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case op == 0x18:
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result += d.jr("JR", "")
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case op == 0x19:
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result += "ADD HL" + sep + "DE"
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case op == 0x1A:
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result += "LD A" + sep + "(DE)"
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case op == 0x1B:
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result += "DEC DE"
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case op == 0x1C:
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result += "INC E"
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case op == 0x1D:
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result += "DEC E"
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case op == 0x1E:
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result += "LD E" + sep + d.getB()
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case op == 0x1F:
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result += "RRA"
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// == 20:2F
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case op == 0x20:
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result += d.jr("JR", "NZ")
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case op == 0x21:
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result += "LD HL" + sep + d.getW()
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case op == 0x22:
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// LD (nn),HL
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result += "LD (" + d.getW() + ")" + sep + "HL"
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case op == 0x23:
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result += "INC HL"
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case op == 0x24:
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result += "INC H"
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case op == 0x25:
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result += "DEC H"
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case op == 0x26:
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result += "LD H" + sep + d.getB()
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case op == 0x27:
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result += "DAA"
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case op == 0x28:
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result += d.jr("JR", "Z")
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case op == 0x29:
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result += "ADD HL" + sep + "HL"
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case op == 0x2A:
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result += "LD HL" + sep + "(" + d.getW() + ")"
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case op == 0x2B:
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result += "DEC HL"
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case op == 0x2C:
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result += "INC L"
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case op == 0x2D:
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result += "DEC L"
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case op == 0x2E:
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result += "LD L" + sep + d.getB()
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case op == 0x2F:
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result += "CPL"
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// == 30:3F
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case op == 0x30:
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result += d.jr("JR", "NC")
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case op == 0x31:
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result += "LD SP" + sep + d.getW()
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case op == 0x32:
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result += "LD (" + d.getW() + ")" + sep + "A"
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case op == 0x33:
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result += "INC SP"
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case op == 0x34:
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result += "INC (HL)"
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case op == 0x35:
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result += "DEC (HL)"
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case op == 0x36:
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result += "LD (HL)" + sep + d.getB()
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case op == 0x37:
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result += "SCF"
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case op == 0x38:
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result += d.jr("JR", "C")
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case op == 0x39:
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result += "ADD HL" + sep + "SP"
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case op == 0x3A:
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result += "LD A" + sep + "(" + d.getW() + ")"
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case op == 0x3B:
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result += "DEC SP"
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case op == 0x3C:
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result += "INC A"
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case op == 0x3D:
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result += "DEC A"
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case op == 0x3E:
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result += "LD A" + sep + d.getB()
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case op == 0x3F:
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result += "CCF"
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case op == 0x76:
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result += "HALT"
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case op >= 0x40 && op <= 0x7F:
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// LD op8, op8
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result += "LD " + operands[(op>>3)&0x07] + sep + operands[op&0x07]
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case op >= 0x80 && op <= 0xBF:
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// ALU op8
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result += aluOp[(op>>3)&0x07] + operands[op&0x07]
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case op == 0xc0:
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result += "RET NZ"
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case op == 0xc1:
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result += "POP BC"
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case op == 0xc2:
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result += d.jp("JP", "NZ")
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case op == 0xc3:
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result += d.jp("JP", "")
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case op == 0xc4:
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result += d.jp("CALL", "NZ")
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case op == 0xc5:
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result += "PUSH BC"
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case op == 0xc6:
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result += "ADD A" + sep + d.getB()
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case op == 0xc7 || op == 0xd7 || op == 0xe7 || op == 0xf7 || op == 0xcf || op == 0xdf || op == 0xef || op == 0xff:
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// RST nnH
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result += fmt.Sprintf("RST %d%dH", (op>>4)&3, (op&1)*8)
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case op == 0xc8:
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result += "RET Z"
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case op == 0xc9:
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result += "RET"
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case op == 0xca:
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result += d.jp("JP", "Z")
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case op == 0xcb:
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result += d.opocodeCB()
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case op == 0xcc:
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result += d.jp("CALL", "Z")
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case op == 0xcd:
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result += d.jp("CALL", "")
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case op == 0xce:
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result += "ADC A" + sep + d.getB()
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case op == 0xd0:
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result += "RET NC"
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case op == 0xd1:
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result += "POP DE"
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case op == 0xd2:
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result += d.jp("JP", "NC")
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case op == 0xd3:
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result += "OUT (" + d.getB() + ")" + sep + "A"
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case op == 0xd4:
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result += d.jp("CALL", "NC")
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case op == 0xd5:
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result += "PUSH DE"
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case op == 0xd6:
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result += "SUB " + d.getB()
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case op == 0xd8:
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result += "RET C"
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case op == 0xd9:
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result += "EXX"
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case op == 0xda:
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result += d.jp("JP", "C")
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case op == 0xdb:
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result += "IN A" + sep + " (" + d.getB() + ")"
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case op == 0xdc:
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result += d.jp("CALL", "C")
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case op == 0xdd:
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result += d.opocodeDD(op)
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case op == 0xde:
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result += "SBC A" + sep + d.getB()
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case op == 0xe0:
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result += "RET PO"
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case op == 0xe1:
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result += "POP HL"
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case op == 0xe2:
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result += d.jp("JP", "PO")
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case op == 0xe3:
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result += "EX (SP)" + sep + "HL"
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case op == 0xe4:
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result += d.jp("CALL", "PO")
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case op == 0xe5:
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result += "PUSH HL"
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case op == 0xe6:
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result += "AND " + d.getB()
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case op == 0xe8:
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result += "RET PE"
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case op == 0xe9:
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result += "JP (HL)"
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case op == 0xea:
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result += d.jp("JP", "PE")
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case op == 0xeb:
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result += "EX DE" + sep + "HL"
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case op == 0xec:
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result += d.jp("CALL", "PE")
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case op == 0xed:
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result += d.opocodeED()
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case op == 0xee:
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result += "XOR " + d.getB()
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case op == 0xf0:
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result += "RET P"
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case op == 0xf1:
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result += "POP AF"
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case op == 0xf2:
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result += d.jp("JP", "P")
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case op == 0xf3:
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result += "DI"
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case op == 0xf4:
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result += d.jp("CALL", "P")
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case op == 0xf5:
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result += "PUSH AF"
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case op == 0xf6:
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result += "OR " + d.getB()
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case op == 0xf8:
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result += "RET M"
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case op == 0xf9:
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result += "LD SP" + sep + "HL"
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case op == 0xfa:
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result += d.jp("JP", "M")
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case op == 0xfb:
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result += "EI"
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case op == 0xfc:
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result += d.jp("CALL", "M")
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case op == 0xfd:
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result += d.opocodeDD(op)
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case op == 0xfe:
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result += "CP " + d.getB()
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default:
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// All unknown as DB
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result += fmt.Sprintf("DB 0x%02X", op)
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}
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return result
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}
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func (d *Disassembler) getW() string {
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lo := d.core.MemRead(d.pc)
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d.pc++
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hi := d.core.MemRead(d.pc)
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d.pc++
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return fmt.Sprintf("0x%02X%02X", hi, lo)
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}
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func (d *Disassembler) getB() string {
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lo := d.core.MemRead(d.pc)
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d.pc++
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return fmt.Sprintf("0x%02X", lo)
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}
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func (d *Disassembler) getRel() string {
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offset := d.core.MemRead(d.pc)
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var sign string
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if int8(offset) < 0 {
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sign = "-"
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} else {
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sign = "+"
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}
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return sign + fmt.Sprintf("0x%02X", offset&0x7F)
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}
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var shiftOps = []string{"RLC", "RRC", "RL", "RR", "SLA", "SRA", "SLL", "SRL"}
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// opocodeCB disassemble Z80 Opcodes, with CB first byte
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func (d *Disassembler) opocodeCB() string {
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op := ""
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opcode := d.getByte()
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if opcode <= 0x3F {
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op = shiftOps[opcode>>3&0x07] + operands[opcode&0x7]
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} else {
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op = shiftOps[(opcode>>6&0x03)-1] + operands[opcode&0x7]
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}
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return op
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}
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func (d *Disassembler) opocodeDD(op byte) string {
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opcode := d.getByte()
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result := ""
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switch opcode {
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case 0x09:
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result = "ADD ii" + sep + "BC"
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case 0x19:
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result = "ADD ii" + sep + "DE"
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case 0x21:
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result = "LD ii" + sep + d.getW()
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case 0x22:
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result = "LD (" + d.getW() + ")" + sep + "ii"
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case 0x23:
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result = "INC ii"
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case 0x24:
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result = "INC IXH"
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case 0x25:
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result = "DEC IXH"
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case 0x26:
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result = "LD IXH" + sep + "n"
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case 0x29:
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result = "ADD ii" + sep + "ii"
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case 0x2A:
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result = "LD ii" + sep + "(" + d.getW() + ")"
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case 0x2B:
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result = "DEC ii"
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case 0x34:
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result = "INC (ii" + d.getRel() + ")"
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case 0x35:
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result = "DEC (ii" + d.getRel() + ")"
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case 0x36:
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result = "LD (ii" + d.getRel() + ")" + sep + "n"
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case 0x39:
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result = "ADD ii" + sep + "SP"
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case 0x46:
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result = "LD B" + sep + "(ii" + d.getRel() + ")"
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case 0x4E:
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result = "LD C" + sep + "(ii" + d.getRel() + ")"
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case 0x56:
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result = "LD D" + sep + "(ii" + d.getRel() + ")"
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case 0x5E:
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result = "LD E" + sep + "(ii" + d.getRel() + ")"
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case 0x66:
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result = "LD H" + sep + "(ii" + d.getRel() + ")"
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case 0x6E:
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result = "LD L" + sep + "(ii" + d.getRel() + ")"
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case 0x70:
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result = "LD (ii" + d.getRel() + ")" + sep + "B"
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case 0x71:
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result = "LD (ii" + d.getRel() + ")" + sep + "C"
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case 0x72:
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result = "LD (ii" + d.getRel() + ")" + sep + "D"
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case 0x73:
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result = "LD (ii" + d.getRel() + ")" + sep + "E"
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case 0x74:
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result = "LD (ii" + d.getRel() + ")" + sep + "H"
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case 0x75:
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result = "LD (ii" + d.getRel() + ")" + sep + "L"
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case 0x77:
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result = "LD (ii" + d.getRel() + ")" + sep + "A"
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case 0x7E:
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result = "LD A" + sep + "(ii" + d.getRel() + ")"
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case 0x86:
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result = "ADD A" + sep + "(ii" + d.getRel() + ")"
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case 0x8E:
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result = "ADC A" + sep + "(ii" + d.getRel() + ")"
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case 0x96:
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result = "SUB (ii" + d.getRel() + ")"
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case 0x9E:
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result = "SBC A" + sep + "(ii" + d.getRel() + ")"
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case 0xA6:
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result = "AND (ii" + d.getRel() + ")"
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case 0xAE:
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result = "XOR (ii" + d.getRel() + ")"
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case 0xB6:
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result = "OR (ii" + d.getRel() + ")"
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case 0xBE:
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result = "CP (ii" + d.getRel() + ")"
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case 0xCB:
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result = d.opocodeDDCB(op, opcode)
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case 0xE1:
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result = "POP ii"
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case 0xE3:
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result = "EX (SP)" + sep + "ii"
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case 0xE5:
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result = "PUSH ii"
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case 0xE9:
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result = "JP (ii)"
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case 0xF9:
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result = "LD SP" + sep + "ii"
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default:
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return fmt.Sprintf("DB 0x%02X, 0x%02X", op, opcode)
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}
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reg := "IX"
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if op == 0xFD {
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reg = "IY"
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}
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return strings.ReplaceAll(result, "ii", reg)
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}
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//var bitOps = []string{"BIT", "RES", "SET"}
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func (d *Disassembler) opocodeDDCB(op1 byte, op2 byte) string {
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opcode := d.getByte()
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result := ""
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switch opcode {
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case 0x06:
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result = "RLC (ii" + d.getRel() + ")"
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case 0x0E:
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result = "RRC (ii" + d.getRel() + ")"
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case 0x16:
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result = "RL (ii" + d.getRel() + ")"
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case 0x1E:
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result = "RR (ii" + d.getRel() + ")"
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case 0x26:
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result = "SLA (ii" + d.getRel() + ")"
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case 0x2E:
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result = "SRA (ii" + d.getRel() + ")"
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case 0x3E:
|
||
result = "SRL (ii" + d.getRel() + ")"
|
||
case 0x46:
|
||
result = "BIT 0" + sep + "(ii" + d.getRel() + ")"
|
||
case 0x4E:
|
||
result = "BIT 1" + sep + "(ii" + d.getRel() + ")"
|
||
case 0x56:
|
||
result = "BIT 2" + sep + "(ii" + d.getRel() + ")"
|
||
case 0x5E:
|
||
result = "BIT 3" + sep + "(ii" + d.getRel() + ")"
|
||
case 0x66:
|
||
result = "BIT 4" + sep + "(ii" + d.getRel() + ")"
|
||
case 0x6E:
|
||
result = "BIT 5" + sep + "(ii" + d.getRel() + ")"
|
||
case 0x76:
|
||
result = "BIT 6" + sep + "(ii" + d.getRel() + ")"
|
||
case 0x7E:
|
||
result = "BIT 7" + sep + "(ii" + d.getRel() + ")"
|
||
case 0x86:
|
||
result = "RES 0" + sep + "(ii" + d.getRel() + ")"
|
||
case 0x8E:
|
||
result = "RES 1" + sep + "(ii" + d.getRel() + ")"
|
||
case 0x96:
|
||
result = "RES 2" + sep + "(ii" + d.getRel() + ")"
|
||
case 0x9E:
|
||
result = "RES 3" + sep + "(ii" + d.getRel() + ")"
|
||
case 0xA6:
|
||
result = "RES 4" + sep + "(ii" + d.getRel() + ")"
|
||
case 0xAE:
|
||
result = "RES 5" + sep + "(ii" + d.getRel() + ")"
|
||
case 0xB6:
|
||
result = "RES 6" + sep + "(ii" + d.getRel() + ")"
|
||
case 0xBE:
|
||
result = "RES 7" + sep + "(ii" + d.getRel() + ")"
|
||
case 0xC6:
|
||
result = "SET 0" + sep + "(ii" + d.getRel() + ")"
|
||
case 0xCE:
|
||
result = "SET 1" + sep + "(ii" + d.getRel() + ")"
|
||
case 0xD6:
|
||
result = "SET 2" + sep + "(ii" + d.getRel() + ")"
|
||
case 0xDE:
|
||
result = "SET 3" + sep + "(ii" + d.getRel() + ")"
|
||
case 0xE6:
|
||
result = "SET 4" + sep + "(ii" + d.getRel() + ")"
|
||
case 0xEE:
|
||
result = "SET 5" + sep + "(ii" + d.getRel() + ")"
|
||
case 0xF6:
|
||
result = "SET 6" + sep + "(ii" + d.getRel() + ")"
|
||
case 0xFE:
|
||
result = "SET 7" + sep + "(ii" + d.getRel() + ")"
|
||
default:
|
||
result = fmt.Sprintf("DB 0x%02X, 0x%02X, 0x%02X", op1, op2, opcode)
|
||
}
|
||
return result
|
||
}
|
||
|
||
func (d *Disassembler) opocodeED() string {
|
||
opcode := d.getByte()
|
||
result := ""
|
||
switch opcode {
|
||
case 0x40:
|
||
result = "IN B" + sep + "(C)"
|
||
case 0x41:
|
||
result = "OUT (C)" + sep + "B"
|
||
case 0x42:
|
||
result = "SBC HL" + sep + "BC"
|
||
case 0x43:
|
||
result = "LD (" + d.getW() + ")" + sep + "BC"
|
||
case 0x44, 0x4C, 0x54, 0x5C, 0x64, 0x6C, 0x74, 0x7C:
|
||
result = "NEG"
|
||
case 0x45, 0x55, 0x5D, 0x65, 0x6D, 0x75, 0x7D:
|
||
result = "RETN"
|
||
case 0x46, 0x4E, 0x66, 0x6E:
|
||
result = "IM 0"
|
||
case 0x47:
|
||
result = "LD I" + sep + "A"
|
||
case 0x48:
|
||
result = "IN C" + sep + "(C)"
|
||
case 0x49:
|
||
result = "OUT (C)" + sep + "C"
|
||
case 0x4A:
|
||
result = "ADC HL" + sep + "BC"
|
||
case 0x4B:
|
||
result = "LD BC" + sep + "(" + d.getW() + ")"
|
||
case 0x4D:
|
||
result = "REТI"
|
||
case 0x4F:
|
||
result = "LD R" + sep + "A"
|
||
case 0x50:
|
||
result = "IN D" + sep + "(C)"
|
||
case 0x51:
|
||
result = "OUT (C)" + sep + "D"
|
||
case 0x52:
|
||
result = "SBC HL" + sep + "DE"
|
||
case 0x53:
|
||
result = "LD (nn)" + sep + "DE"
|
||
case 0x56, 0x76:
|
||
result = "IM 1"
|
||
case 0x57:
|
||
result = "LD A" + sep + "I"
|
||
case 0x58:
|
||
result = "IN E" + sep + "(C)"
|
||
case 0x59:
|
||
result = "OUT (C)" + sep + "E"
|
||
case 0x5A:
|
||
result = "ADC HL" + sep + "DE"
|
||
case 0x5B:
|
||
result = "LD DE" + sep + "(" + d.getW() + ")"
|
||
case 0x5E, 0x7E:
|
||
result = "IM 2"
|
||
case 0x5F:
|
||
result = "LD A" + sep + "R"
|
||
case 0x60:
|
||
result = "IN H" + sep + "(C)"
|
||
case 0x61:
|
||
result = "OUT (C)" + sep + "H"
|
||
case 0x62:
|
||
result = "SBC HL" + sep + "HL"
|
||
case 0x63:
|
||
result = "LD (nn)" + sep + "HL"
|
||
case 0x67:
|
||
result = "RRD"
|
||
case 0x68:
|
||
result = "IN L" + sep + " (C)"
|
||
case 0x69:
|
||
result = "OUT (C)" + sep + "L"
|
||
case 0x6A:
|
||
result = "ADC HL" + sep + " HL"
|
||
case 0x6B:
|
||
result = "LD HL" + sep + " (nn)"
|
||
case 0x6F:
|
||
result = "RLD"
|
||
case 0x70:
|
||
result = "INF"
|
||
case 0x71:
|
||
result = "OUT (C)" + sep + " 0"
|
||
case 0x72:
|
||
result = "SBC HL" + sep + "SP"
|
||
case 0x73:
|
||
result = "LD (nn)" + sep + "SP"
|
||
case 0x78:
|
||
result = "IN A" + sep + "(C)"
|
||
case 0x79:
|
||
result = "OUT (C)" + sep + "A"
|
||
case 0x7A:
|
||
result = "ADC HL" + sep + "SP"
|
||
case 0x7B:
|
||
result = "LD SP" + sep + "(" + d.getW() + ")"
|
||
case 0xA0:
|
||
result = "LDI"
|
||
case 0xA1:
|
||
result = "CPI"
|
||
case 0xA2:
|
||
result = "INI"
|
||
case 0xA3:
|
||
result = "OUTI"
|
||
case 0xA8:
|
||
result = "LDD"
|
||
case 0xA9:
|
||
result = "CPD"
|
||
case 0xAA:
|
||
result = "IND"
|
||
case 0xAB:
|
||
result = "OUTD"
|
||
case 0xB0:
|
||
result = "LDIR"
|
||
case 0xB1:
|
||
result = "CPIR"
|
||
case 0xB2:
|
||
result = "INIR"
|
||
case 0xB3:
|
||
result = "OTIR"
|
||
case 0xB8:
|
||
result = "LDDR"
|
||
case 0xB9:
|
||
result = "CPDR"
|
||
case 0xBA:
|
||
result = "INDR"
|
||
case 0xBB:
|
||
result = "OTDR"
|
||
default:
|
||
result = fmt.Sprintf("DB 0xED, 0x%02X", opcode)
|
||
}
|
||
return result
|
||
}
|