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The Blue Wizard
Lars Brinkhoff
parent
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commit
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8
ARCompact/README.md
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8
ARCompact/README.md
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This subfolder contains the documents and other stuff for ARC CPU family.
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[Main Wikipedia article on this family](https://en.wikipedia.org/wiki/ARC_%28processor%29)
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| Files | Description | Source |
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| ----- | ----------- | ------ |
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| ARCompactISA_ProgrammersReference.pdf | ARCompact ISA Programmers Reference | |
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BIN
ARM/QRC0001_UAL.pdf
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BIN
ARM/QRC0001_UAL.pdf
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Binary file not shown.
579
MCS6500/6502_opcode_table.htm
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MCS6500/6502_opcode_table.htm
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<html>
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<head>
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<title>Atari "Sally" (6502) Instruction Set</title>
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</head>
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<h1><center><b>Atari "Sally" (6502) Instruction Set</b></center></h1>
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<hr width="75%">
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<h2><b>Op-Code Table</b> (arranged in op-code order):</h2>
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<table border cellpadding=5 width="100%">
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<tr align="center">
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<td width="7%">\ LSD<br>
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MSD \</td>
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<td width="7%">0</td>
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<td width="7%">1</td>
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<td width="7%">2</td>
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<td width="7%">3</td>
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<td width="7%">4</td>
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<td width="7%">5</td>
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<td width="7%">6</td>
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<td width="7%">7</td>
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<td width="7%">8</td>
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<td width="7%">9</td>
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<td width="7%">A</td>
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<td width="7%">B</td>
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<td width="7%">C</td>
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<td width="7%">D</td>
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<td width="7%">E</td>
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<td width="7%">F</td>
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<td width="7%">LSD /<br>
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/ MSD</td></tr>
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<tr>
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<td align="center">0</td>
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<td>BRK</td>
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<td>ORA<br>
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(IND,X)</td>
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<td>JAM *</td>
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<td>SRA *<br>
|
||||
(IND,X)</td>
|
||||
<td>NOP *<br>
|
||||
Z-Page</td>
|
||||
<td>ORA<br>
|
||||
Z-Page</td>
|
||||
<td>ASL<br>
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||||
Z-Page</td>
|
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<td>SRA *<br>
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||||
Z-Page</td>
|
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<td>PHP</td>
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||||
<td>ORA<br>
|
||||
IMM</td>
|
||||
<td>ASL<br>
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||||
A</td>
|
||||
<td>ANC *<br>
|
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IMM</td>
|
||||
<td>NOP *<br>
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ABS</td>
|
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<td>ORA<br>
|
||||
ABS</td>
|
||||
<td>ASL<br>
|
||||
ABS</td>
|
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<td>SRA *<br>
|
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ABS</td>
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<td align="center">0</td></tr>
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<tr>
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<td align="center">1</td>
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<td>BPL</td>
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<td>ORA<br>
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(IND),Y</td>
|
||||
<td>JAM *</td>
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||||
<td>SRA *<br>
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||||
(IND),Y</td>
|
||||
<td>NOP *<br>
|
||||
Z-Page,X</td>
|
||||
<td>ORA<br>
|
||||
Z-Page,X</td>
|
||||
<td>ASL<br>
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||||
Z-Page,X</td>
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<td>SRA *<br>
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Z-Page,X</td>
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<td>CLC</td>
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<td>ORA<br>
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ABS,Y</td>
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<td>NOP *</td>
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<td>SRA *<br>
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||||
ABS,Y</td>
|
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<td>NOP *<br>
|
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ABS,X</td>
|
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<td>ORA<br>
|
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ABS,X</td>
|
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<td>ASL<br>
|
||||
ABS,X</td>
|
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<td>SRA *<br>
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ABS,X</td>
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<td align="center">1</td></tr>
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<tr>
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<td align="center">2</td>
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<td>JSR<br>
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ABS</td>
|
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<td>AND<br>
|
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(IND,X)</td>
|
||||
<td>JAM *</td>
|
||||
<td>RLA *<br>
|
||||
(IND,X)</td>
|
||||
<td>BIT<br>
|
||||
Z-Page</td>
|
||||
<td>AND<br>
|
||||
Z-Page</td>
|
||||
<td>ROL<br>
|
||||
Z-Page</td>
|
||||
<td>RLA *<br>
|
||||
Z-Page</td>
|
||||
<td>PLP</td>
|
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<td>AND<br>
|
||||
IMM</td>
|
||||
<td>ROL<br>
|
||||
A</td>
|
||||
<td>ANC *<br>
|
||||
IMM</td>
|
||||
<td>BIT<br>
|
||||
ABS</td>
|
||||
<td>AND<br>
|
||||
ABS</td>
|
||||
<td>ROL<br>
|
||||
ABS</td>
|
||||
<td>RLA *<br>
|
||||
ABS</td>
|
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<td align="center">2</td></tr>
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<tr>
|
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<td align="center">3</td>
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<td>BMI</td>
|
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<td>AND<br>
|
||||
(IND),Y</td>
|
||||
<td>JAM *</td>
|
||||
<td>RLA *<br>
|
||||
(IND),Y</td>
|
||||
<td>NOP *<br>
|
||||
Z-Page,X</td>
|
||||
<td>AND<br>
|
||||
Z-Page,X</td>
|
||||
<td>ROL<br>
|
||||
Z-Page,X</td>
|
||||
<td>RLA *<br>
|
||||
Z-Page,X</td>
|
||||
<td>SEC</td>
|
||||
<td>AND<br>
|
||||
ABS,Y</td>
|
||||
<td>NOP *</td>
|
||||
<td>RLA *<br>
|
||||
ABS,Y</td>
|
||||
<td>NOP *<br>
|
||||
ABS,X</td>
|
||||
<td>AND<br>
|
||||
ABS,X</td>
|
||||
<td>ROL<br>
|
||||
ABS,X</td>
|
||||
<td>RLA *<br>
|
||||
ABS,X</td>
|
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<td align="center">3</td></tr>
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<tr>
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<td align="center">4</td>
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<td>RTI</td>
|
||||
<td>EOR<br>
|
||||
(IND,X)</td>
|
||||
<td>JAM *</td>
|
||||
<td>SLO *<br>
|
||||
(IND,X)</td>
|
||||
<td>NOP *<br>
|
||||
Z-Page</td>
|
||||
<td>EOR<br>
|
||||
Z-Page</td>
|
||||
<td>LSR<br>
|
||||
Z-Page</td>
|
||||
<td>SLO *<br>
|
||||
Z-Page</td>
|
||||
<td>PHA</td>
|
||||
<td>EOR<br>
|
||||
IMM</td>
|
||||
<td>LSR<br>
|
||||
A</td>
|
||||
<td>ASR *<br>
|
||||
IMM</td>
|
||||
<td>JMP<br>
|
||||
ABS</td>
|
||||
<td>EOR<br>
|
||||
ABS</td>
|
||||
<td>LSR<br>
|
||||
ABS</td>
|
||||
<td>SLO *<br>
|
||||
ABS</td>
|
||||
<td align="center">4</td></tr>
|
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<tr>
|
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<td align="center">5</td>
|
||||
<td>BVC</td>
|
||||
<td>EOR<br>
|
||||
(IND),Y</td>
|
||||
<td>JAM *</td>
|
||||
<td>SLO *<br>
|
||||
(IND),Y</td>
|
||||
<td>NOP *<br>
|
||||
Z-Page,X</td>
|
||||
<td>EOR<br>
|
||||
Z-Page,X</td>
|
||||
<td>LSR<br>
|
||||
Z-Page,X</td>
|
||||
<td>SLO *<br>
|
||||
Z-Page,X</td>
|
||||
<td>CLI</td>
|
||||
<td>EOR<br>
|
||||
ABS,Y</td>
|
||||
<td>NOP *</td>
|
||||
<td>SLO *<br>
|
||||
ABS,Y</td>
|
||||
<td>NOP *<br>
|
||||
ABS,X</td>
|
||||
<td>EOR<br>
|
||||
ABS,X</td>
|
||||
<td>LSR<br>
|
||||
ABS,X</td>
|
||||
<td>SLO *<br>
|
||||
ABS,X</td>
|
||||
<td align="center">5</td></tr>
|
||||
<tr>
|
||||
<td align="center">6</td>
|
||||
<td>RTS</td>
|
||||
<td>ADC<br>
|
||||
(IND,X)</td>
|
||||
<td>JAM *</td>
|
||||
<td>RRA *<br>
|
||||
(IND,X)</td>
|
||||
<td>NOP *<br>
|
||||
Z-Page</td>
|
||||
<td>ADC<br>
|
||||
Z-Page</td>
|
||||
<td>ROR<br>
|
||||
Z-Page</td>
|
||||
<td>RRA *<br>
|
||||
Z-Page</td>
|
||||
<td>PLA</td>
|
||||
<td>ADC<br>
|
||||
IMM</td>
|
||||
<td>ROR<br>
|
||||
A</td>
|
||||
<td>ARR *<br>
|
||||
IMM</td>
|
||||
<td>JMP<br>
|
||||
Indirect</td>
|
||||
<td>ADC<br>
|
||||
ABS</td>
|
||||
<td>ROR<br>
|
||||
ABS</td>
|
||||
<td>RRA *<br>
|
||||
ABS</td>
|
||||
<td align="center">6</td></tr>
|
||||
<tr>
|
||||
<td align="center">7</td>
|
||||
<td>BVS</td>
|
||||
<td>ADC<br>
|
||||
(IND),Y</td>
|
||||
<td>JAM *</td>
|
||||
<td>RRA *<br>
|
||||
(IND),Y</td>
|
||||
<td>NOP *<br>
|
||||
Z-Page,X</td>
|
||||
<td>ADC<br>
|
||||
Z-Page,X</td>
|
||||
<td>ROR<br>
|
||||
Z-Page,X</td>
|
||||
<td>RRA *<br>
|
||||
Z-Page,X</td>
|
||||
<td>SEI</td>
|
||||
<td>ADC<br>
|
||||
ABS,Y</td>
|
||||
<td>NOP *</td>
|
||||
<td>RRA *<br>
|
||||
ABS,Y</td>
|
||||
<td>NOP *<br>
|
||||
ABS,X</td>
|
||||
<td>ADC<br>
|
||||
ABS,X</td>
|
||||
<td>ROR<br>
|
||||
ABS,X</td>
|
||||
<td>RRA *<br>
|
||||
ABS,X</td>
|
||||
<td align="center">7</td></tr>
|
||||
<tr>
|
||||
<td align="center">8</td>
|
||||
<td>NOP *<br>
|
||||
IMM</td>
|
||||
<td>STA<br>
|
||||
(IND,X)</td>
|
||||
<td>NOP *<br>
|
||||
IMM</td>
|
||||
<td>SAX *<br>
|
||||
(IND,X)</td>
|
||||
<td>STY<br>
|
||||
Z-Page</td>
|
||||
<td>STA<br>
|
||||
Z-Page</td>
|
||||
<td>STX<br>
|
||||
Z-Page</td>
|
||||
<td>SAX *<br>
|
||||
Z-Page</td>
|
||||
<td>DEY</td>
|
||||
<td>NOP *<br>
|
||||
IMM</td>
|
||||
<td>TXA</td>
|
||||
<td>AXE *<br>
|
||||
IMM</td>
|
||||
<td>STY<br>
|
||||
ABS</td>
|
||||
<td>STA<br>
|
||||
ABS</td>
|
||||
<td>STX<br>
|
||||
ABS</td>
|
||||
<td>SAX *<br>
|
||||
ABS</td>
|
||||
<td align="center">8</td></tr>
|
||||
<tr>
|
||||
<td align="center">9</td>
|
||||
<td>BCC</td>
|
||||
<td>STA<br>
|
||||
(IND),Y</td>
|
||||
<td>JAM *</td>
|
||||
<td>AX7 *<br>
|
||||
(IND),Y</td>
|
||||
<td>STY<br>
|
||||
Z-Page,X</td>
|
||||
<td>STA<br>
|
||||
Z-Page,X</td>
|
||||
<td>STX<br>
|
||||
Z-Page,Y</td>
|
||||
<td>SAX *<br>
|
||||
Z-Page,Y</td>
|
||||
<td>TYA</td>
|
||||
<td>STA<br>
|
||||
ABS,Y</td>
|
||||
<td>TXS</td>
|
||||
<td>XS7 *<br>
|
||||
ABS,Y</td>
|
||||
<td>SY7 *<br>
|
||||
ABS,X</td>
|
||||
<td>STA<br>
|
||||
ABS,X</td>
|
||||
<td>SX7 *<br>
|
||||
ABS,Y</td>
|
||||
<td>AX7 *<br>
|
||||
ABS,Y</td>
|
||||
<td align="center">9</td></tr>
|
||||
<tr>
|
||||
<td align="center">A</td>
|
||||
<td>LDY<br>
|
||||
IMM</td>
|
||||
<td>LDA<br>
|
||||
(IND,X)</td>
|
||||
<td>LDX<br>
|
||||
IMM</td>
|
||||
<td>LAX *<br>
|
||||
(IND,X)</td>
|
||||
<td>LDY<br>
|
||||
Z-Page</td>
|
||||
<td>LDA<br>
|
||||
Z-Page</td>
|
||||
<td>LDX<br>
|
||||
Z-Page</td>
|
||||
<td>LAX *<br>
|
||||
Z-Page</td>
|
||||
<td>TAY</td>
|
||||
<td>LDA<br>
|
||||
IMM</td>
|
||||
<td>TAX</td>
|
||||
<td>XEA *<br>
|
||||
IMM</td>
|
||||
<td>LDY<br>
|
||||
ABS</td>
|
||||
<td>LDA<br>
|
||||
ABS</td>
|
||||
<td>LDX<br>
|
||||
ABS</td>
|
||||
<td>LAX *<br>
|
||||
ABS</td>
|
||||
<td align="center">A</td></tr>
|
||||
<tr>
|
||||
<td align="center">B</td>
|
||||
<td>BCS</td>
|
||||
<td>LDA<br>
|
||||
(IND),Y</td>
|
||||
<td>JAM *</td>
|
||||
<td>LAX *<br>
|
||||
(IND),Y</td>
|
||||
<td>LDY<br>
|
||||
Z-Page,X</td>
|
||||
<td>LDA<br>
|
||||
Z-Page,X</td>
|
||||
<td>LDX<br>
|
||||
Z-Page,Y</td>
|
||||
<td>LAX *<br>
|
||||
Z-Page,Y</td>
|
||||
<td>CLV</td>
|
||||
<td>LDA<br>
|
||||
ABS,Y</td>
|
||||
<td>TSX</td>
|
||||
<td>LAS *<br>
|
||||
ABS,Y</td>
|
||||
<td>LDY<br>
|
||||
ABS,X</td>
|
||||
<td>LDA<br>
|
||||
ABS,X</td>
|
||||
<td>LDX<br>
|
||||
ABS,Y</td>
|
||||
<td>LAX *<br>
|
||||
ABS,Y</td>
|
||||
<td align="center">B</td></tr>
|
||||
<tr>
|
||||
<td align="center">C</td>
|
||||
<td>CPY<br>
|
||||
IMM</td>
|
||||
<td>CMP<br>
|
||||
(IND,X)</td>
|
||||
<td>NOP *<br>
|
||||
IMM</td>
|
||||
<td>DCP *<br>
|
||||
(IND,X)</td>
|
||||
<td>CPY<br>
|
||||
Z-Page</td>
|
||||
<td>CMP<br>
|
||||
Z-Page</td>
|
||||
<td>DEC<br>
|
||||
Z-Page</td>
|
||||
<td>DCP *<br>
|
||||
Z-Page</td>
|
||||
<td>INY</td>
|
||||
<td>CMP<br>
|
||||
IMM</td>
|
||||
<td>DEX</td>
|
||||
<td>ASX *<br>
|
||||
IMM</td>
|
||||
<td>CPY<br>
|
||||
ABS</td>
|
||||
<td>CMP<br>
|
||||
ABS</td>
|
||||
<td>DEC<br>
|
||||
ABS</td>
|
||||
<td>DCP *<br>
|
||||
ABS</td>
|
||||
<td align="center">C</td></tr>
|
||||
<tr>
|
||||
<td align="center">D</td>
|
||||
<td>BNE</td>
|
||||
<td>CMP<br>
|
||||
(IND),Y</td>
|
||||
<td>JAM *</td>
|
||||
<td>DCP *<br>
|
||||
(IND),Y</td>
|
||||
<td>NOP *<br>
|
||||
Z-Page,X</td>
|
||||
<td>CMP<br>
|
||||
Z-Page,X</td>
|
||||
<td>DEC<br>
|
||||
Z-Page,X</td>
|
||||
<td>DCP *<br>
|
||||
Z-Page,X</td>
|
||||
<td>CLD</td>
|
||||
<td>CMP<br>
|
||||
ABS,Y</td>
|
||||
<td>NOP *</td>
|
||||
<td>DCP *<br>
|
||||
ABS,Y</td>
|
||||
<td>NOP *<br>
|
||||
ABS,X</td>
|
||||
<td>CMP<br>
|
||||
ABS,X</td>
|
||||
<td>DEC<br>
|
||||
ABS,X</td>
|
||||
<td>DCP *<br>
|
||||
ABS,X</td>
|
||||
<td align="center">D</td></tr>
|
||||
<tr>
|
||||
<td align="center">E</td>
|
||||
<td>CPX<br>
|
||||
IMM</td>
|
||||
<td>SBC<br>
|
||||
(IND,X)</td>
|
||||
<td>NOP *<br>
|
||||
IMM</td>
|
||||
<td>ISB *<br>
|
||||
(IND,X)</td>
|
||||
<td>CPX<br>
|
||||
Z-Page</td>
|
||||
<td>SBC<br>
|
||||
Z-Page</td>
|
||||
<td>INC<br>
|
||||
Z-Page</td>
|
||||
<td>ISB *<br>
|
||||
Z-Page</td>
|
||||
<td>INX</td>
|
||||
<td>SBC<br>
|
||||
IMM</td>
|
||||
<td>NOP</td>
|
||||
<td>SBC *<br>
|
||||
IMM</td>
|
||||
<td>CPX<br>
|
||||
ABS</td>
|
||||
<td>SBC<br>
|
||||
ABS</td>
|
||||
<td>INC<br>
|
||||
ABS</td>
|
||||
<td>ISB *<br>
|
||||
ABS</td>
|
||||
<td align="center">E</td></tr>
|
||||
<tr>
|
||||
<td align="center">F</td>
|
||||
<td>BEQ</td>
|
||||
<td>SBC<br>
|
||||
(IND),Y</td>
|
||||
<td>JAM *</td>
|
||||
<td>ISB *<br>
|
||||
(IND),Y</td>
|
||||
<td>NOP *<br>
|
||||
Z-Page,X</td>
|
||||
<td>SBC<br>
|
||||
Z-Page,X</td>
|
||||
<td>INC<br>
|
||||
Z-Page,X</td>
|
||||
<td>ISB *<br>
|
||||
Z-Page,X</td>
|
||||
<td>SED</td>
|
||||
<td>SBC<br>
|
||||
ABS,Y</td>
|
||||
<td>NOP *</td>
|
||||
<td>ISB *<br>
|
||||
ABS,Y</td>
|
||||
<td>NOP *<br>
|
||||
ABS,X</td>
|
||||
<td>SBC<br>
|
||||
ABS,X</td>
|
||||
<td>INC<br>
|
||||
ABS,X</td>
|
||||
<td>ISB *<br>
|
||||
ABS,X</td>
|
||||
<td align="center">F</td></tr>
|
||||
<tr align="center">
|
||||
<td>MSD /<br>
|
||||
/ LSD</td>
|
||||
<td>0</td>
|
||||
<td>1</td>
|
||||
<td>2</td>
|
||||
<td>3</td>
|
||||
<td>4</td>
|
||||
<td>5</td>
|
||||
<td>6</td>
|
||||
<td>7</td>
|
||||
<td>8</td>
|
||||
<td>9</td>
|
||||
<td>A</td>
|
||||
<td>B</td>
|
||||
<td>C</td>
|
||||
<td>D</td>
|
||||
<td>E</td>
|
||||
<td>F</td>
|
||||
<td>\ MSD<br>
|
||||
LSD \</td></tr></table>
|
||||
|
||||
<h3>Notes:</h3>
|
||||
|
||||
<p>* Undocumented instruction. The behavior of these opcodes was observed on
|
||||
an Atari 800. It may vary with other 6502-based CPU's.
|
||||
|
||||
<hr width="50%" align=left>
|
||||
|
||||
<h2><a href="atari.html"><img src="back-atari.gif" alt="Back to Atari page"
|
||||
height=64 width=64 border=0 align=abscenter></a>
|
||||
<a href="atari.html">Back to Atari Technical Information page</a></h2>
|
||||
|
||||
<hr>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
364
MCS6500/65816_opcode_table.htm
Normal file
364
MCS6500/65816_opcode_table.htm
Normal file
@ -0,0 +1,364 @@
|
||||
<html>
|
||||
<head>
|
||||
<title>65816 Instruction Set</title>
|
||||
</head>
|
||||
|
||||
<h1><center><b>65816 Instruction Set</b></center></h1>
|
||||
|
||||
<hr width="75%">
|
||||
|
||||
<h2><b>Op-Code Table</b> (arranged in op-code order):</h2>
|
||||
|
||||
<table border cellpadding=5 width="100%">
|
||||
<tr align="center">
|
||||
<td width="7%">\ LSD<br>
|
||||
MSD \</td>
|
||||
<td width="7%">0</td>
|
||||
<td width="7%">1</td>
|
||||
<td width="7%">2</td>
|
||||
<td width="7%">3</td>
|
||||
<td width="7%">4</td>
|
||||
<td width="7%">5</td>
|
||||
<td width="7%">6</td>
|
||||
<td width="7%">7</td>
|
||||
<td width="7%">8</td>
|
||||
<td width="7%">9</td>
|
||||
<td width="7%">A</td>
|
||||
<td width="7%">B</td>
|
||||
<td width="7%">C</td>
|
||||
<td width="7%">D</td>
|
||||
<td width="7%">E</td>
|
||||
<td width="7%">F</td>
|
||||
<td width="7%">LSD /<br>
|
||||
/ MSD</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td align="center">0</td>
|
||||
<td>BRK s</td>
|
||||
<td>ORA (d,x)</td>
|
||||
<td>COP s</td>
|
||||
<td>ORA d,s</td>
|
||||
<td>TSB d</td>
|
||||
<td>ORA d</td>
|
||||
<td>ASL d</td>
|
||||
<td>ORA [d]</td>
|
||||
<td>PHP s</td>
|
||||
<td>ORA #</td>
|
||||
<td>ASL A</td>
|
||||
<td>PHD s</td>
|
||||
<td>TSB a</td>
|
||||
<td>ORA a</td>
|
||||
<td>ASL a</td>
|
||||
<td>ORA al</td>
|
||||
<td align="center">0</td></tr>
|
||||
<tr>
|
||||
<td align="center">1</td>
|
||||
<td>BPL r</td>
|
||||
<td>ORA (d),y</td>
|
||||
<td>ORA (d)</td>
|
||||
<td>ORA (d,s),y</td>
|
||||
<td>TRB d</td>
|
||||
<td>ORA d,x</td>
|
||||
<td>ASL d,x</td>
|
||||
<td>ORA [d],y</td>
|
||||
<td>CLI i</td>
|
||||
<td>ORA a,y</td>
|
||||
<td>INC A</td>
|
||||
<td>TCS i</td>
|
||||
<td>TRB a</td>
|
||||
<td>ORA a,x</td>
|
||||
<td>ASL a,x</td>
|
||||
<td>ORA al,x</td>
|
||||
<td align="center">1</td></tr>
|
||||
<tr>
|
||||
<td align="center">2</td>
|
||||
<td>JSR a</td>
|
||||
<td>AND (d,x)</td>
|
||||
<td>JSL al</td>
|
||||
<td>AND d,s</td>
|
||||
<td>BIT d</td>
|
||||
<td>AND d</td>
|
||||
<td>ROL d</td>
|
||||
<td>AND [d]</td>
|
||||
<td>PLP s</td>
|
||||
<td>AND #</td>
|
||||
<td>ROL A</td>
|
||||
<td>PLD s</td>
|
||||
<td>BIT a</td>
|
||||
<td>AND a</td>
|
||||
<td>ROL a</td>
|
||||
<td>AND al</td>
|
||||
<td align="center">2</td></tr>
|
||||
<tr>
|
||||
<td align="center">3</td>
|
||||
<td>BMI r</td>
|
||||
<td>AND (d),y</td>
|
||||
<td>AND (d)</td>
|
||||
<td>AND (d,s),y</td>
|
||||
<td>BIT d,x</td>
|
||||
<td>AND d,x</td>
|
||||
<td>ROL d,x</td>
|
||||
<td>AND [d],y</td>
|
||||
<td>SEC i</td>
|
||||
<td>AND a,y</td>
|
||||
<td>DEC A</td>
|
||||
<td>TSC i</td>
|
||||
<td>BIT a,x</td>
|
||||
<td>AND a,x</td>
|
||||
<td>ROL a,x</td>
|
||||
<td>AND al,x</td>
|
||||
<td align="center">3</td></tr>
|
||||
<tr>
|
||||
<td align="center">4</td>
|
||||
<td>RTI</td>
|
||||
<td>EOR (d,x)</td>
|
||||
<td>WDM ???</td>
|
||||
<td>EOR d,s</td>
|
||||
<td>MVP xyc</td>
|
||||
<td>EOR d</td>
|
||||
<td>LSR d</td>
|
||||
<td>EOR [d]</td>
|
||||
<td>PHA</td>
|
||||
<td>EOR #</td>
|
||||
<td>LSR A</td>
|
||||
<td>PHK</td>
|
||||
<td>JMP a</td>
|
||||
<td>EOR a</td>
|
||||
<td>LSR a</td>
|
||||
<td>EOR al</td>
|
||||
<td align="center">4</td></tr>
|
||||
<tr>
|
||||
<td align="center">5</td>
|
||||
<td>BVC r</td>
|
||||
<td>EOR (d),y</td>
|
||||
<td>EOR (d)</td>
|
||||
<td>EOR (d,s),y</td>
|
||||
<td>MVN xyc</td>
|
||||
<td>EOR d,x</td>
|
||||
<td>LSR d,x</td>
|
||||
<td>EOR [d],y</td>
|
||||
<td>CLI i</td>
|
||||
<td>EOR a,y</td>
|
||||
<td>PHY s</td>
|
||||
<td>TCD i</td>
|
||||
<td>JMP al</td>
|
||||
<td>EOR a,x</td>
|
||||
<td>LSR a,x</td>
|
||||
<td>EOR al,x</td>
|
||||
<td align="center">5</td></tr>
|
||||
<tr>
|
||||
<td align="center">6</td>
|
||||
<td>RTS s</td>
|
||||
<td>ADC (d,x)</td>
|
||||
<td>PER s</td>
|
||||
<td>ADC d,s</td>
|
||||
<td>STZ d</td>
|
||||
<td>ADC d</td>
|
||||
<td>ROR d</td>
|
||||
<td>ADC [d]</td>
|
||||
<td>PLA s</td>
|
||||
<td>ADC #</td>
|
||||
<td>ROR A</td>
|
||||
<td>RTL s</td>
|
||||
<td>JMP (a)</td>
|
||||
<td>ADC a</td>
|
||||
<td>ROR a</td>
|
||||
<td>ADC al</td>
|
||||
<td align="center">6</td></tr>
|
||||
<tr>
|
||||
<td align="center">7</td>
|
||||
<td>BVS r</td>
|
||||
<td>ADC (d),y</td>
|
||||
<td>ADC (d)</td>
|
||||
<td>ADC (d,s),y</td>
|
||||
<td>STZ d,x</td>
|
||||
<td>ADC d,x</td>
|
||||
<td>ROR d,x</td>
|
||||
<td>ADC [d],y</td>
|
||||
<td>SEI i</td>
|
||||
<td>ADC a,y</td>
|
||||
<td>PLY</td>
|
||||
<td>TDC i</td>
|
||||
<td>JMP (a,x)</td>
|
||||
<td>ADC a,x</td>
|
||||
<td>ROR a,x</td>
|
||||
<td>ADC al,x</td>
|
||||
<td align="center">7</td></tr>
|
||||
<tr>
|
||||
<td align="center">8</td>
|
||||
<td>BRA r</td>
|
||||
<td>STA (d,x)</td>
|
||||
<td>BRL rl</td>
|
||||
<td>STA d,s</td>
|
||||
<td>STY d</td>
|
||||
<td>STA d</td>
|
||||
<td>STX d</td>
|
||||
<td>STA [d]</td>
|
||||
<td>DEY i</td>
|
||||
<td>BIT #</td>
|
||||
<td>TXA i</td>
|
||||
<td>PHB</td>
|
||||
<td>STY a</td>
|
||||
<td>STA a</td>
|
||||
<td>STX a</td>
|
||||
<td>STA al</td>
|
||||
<td align="center">8</td></tr>
|
||||
<tr>
|
||||
<td align="center">9</td>
|
||||
<td>BCC r</td>
|
||||
<td>STA (d),y</td>
|
||||
<td>STA (d)</td>
|
||||
<td>STA (d,s),y</td>
|
||||
<td>STY d,x</td>
|
||||
<td>STA d,x</td>
|
||||
<td>STX d,y</td>
|
||||
<td>STA [d],y</td>
|
||||
<td>TYA i</td>
|
||||
<td>STA a,y</td>
|
||||
<td>TXS i</td>
|
||||
<td>TXY i</td>
|
||||
<td>STZ a</td>
|
||||
<td>STA a,x</td>
|
||||
<td>STZ a,x</td>
|
||||
<td>STA al,x</td>
|
||||
<td align="center">9</td></tr>
|
||||
<tr>
|
||||
<td align="center">A</td>
|
||||
<td>LDY #</td>
|
||||
<td>LDA (d,x)</td>
|
||||
<td>LDX #</td>
|
||||
<td>LDA d,s</td>
|
||||
<td>LDY d</td>
|
||||
<td>LDA d</td>
|
||||
<td>LDX d</td>
|
||||
<td>LDA [d]</td>
|
||||
<td>TAY i</td>
|
||||
<td>LDA #</td>
|
||||
<td>TAX i</td>
|
||||
<td>PLB s</td>
|
||||
<td>LDY a</td>
|
||||
<td>LDA a</td>
|
||||
<td>LDX a</td>
|
||||
<td>LDA al</td>
|
||||
<td align="center">A</td></tr>
|
||||
<tr>
|
||||
<td align="center">B</td>
|
||||
<td>BCS r</td>
|
||||
<td>LDA (d),y</td>
|
||||
<td>LDA (d)</td>
|
||||
<td>LDA (d,s),y</td>
|
||||
<td>LDY d,x</td>
|
||||
<td>LDA d,x</td>
|
||||
<td>LDX d,y</td>
|
||||
<td>LDA [d],y</td>
|
||||
<td>CLV i</td>
|
||||
<td>LDA a,y</td>
|
||||
<td>TSX i</td>
|
||||
<td>TYX i</td>
|
||||
<td>LDY a,x</td>
|
||||
<td>LDA a,x</td>
|
||||
<td>LDX a,y</td>
|
||||
<td>LDA al,x</td>
|
||||
<td align="center">B</td></tr>
|
||||
<tr>
|
||||
<td align="center">C</td>
|
||||
<td>CPY #</td>
|
||||
<td>CMP (d,x)</td>
|
||||
<td>REP #</td>
|
||||
<td>CMP d,s</td>
|
||||
<td>CPY d</td>
|
||||
<td>CMP d</td>
|
||||
<td>DEC d</td>
|
||||
<td>CMP [d]</td>
|
||||
<td>INY</td>
|
||||
<td>CMP #</td>
|
||||
<td>DEX i</td>
|
||||
<td>WAI</td>
|
||||
<td>CPY a</td>
|
||||
<td>CMP a</td>
|
||||
<td>DEC a</td>
|
||||
<td>CMP al</td>
|
||||
<td align="center">C</td></tr>
|
||||
<tr>
|
||||
<td align="center">D</td>
|
||||
<td>BNE r</td>
|
||||
<td>CMP (d),y</td>
|
||||
<td>CMP (d)</td>
|
||||
<td>CMP (d,s),y</td>
|
||||
<td>PEI d</td>
|
||||
<td>CMP d,x</td>
|
||||
<td>DEC d,x</td>
|
||||
<td>CMP [d],y</td>
|
||||
<td>CLD i</td>
|
||||
<td>CMP a,y</td>
|
||||
<td>PHX</td>
|
||||
<td>STP</td>
|
||||
<td>JML (a)</td>
|
||||
<td>CMP a,x</td>
|
||||
<td>DEC a,x</td>
|
||||
<td>CMP al,x</td>
|
||||
<td align="center">D</td></tr>
|
||||
<tr>
|
||||
<td align="center">E</td>
|
||||
<td>CPX #</td>
|
||||
<td>SBC (d,x)</td>
|
||||
<td>SEP #</td>
|
||||
<td>SBC d,s</td>
|
||||
<td>CPX d</td>
|
||||
<td>SBC d</td>
|
||||
<td>INC d</td>
|
||||
<td>SBC [d]</td>
|
||||
<td>INX</td>
|
||||
<td>SBC #</td>
|
||||
<td>NOP</td>
|
||||
<td>XBA i</td>
|
||||
<td>CPX a</td>
|
||||
<td>SBC a</td>
|
||||
<td>INC a</td>
|
||||
<td>SBC al</td>
|
||||
<td align="center">E</td></tr>
|
||||
<tr>
|
||||
<td align="center">F</td>
|
||||
<td>BEQ r</td>
|
||||
<td>SBC (d),y</td>
|
||||
<td>SBC (d)</td>
|
||||
<td>SBC (d,s),y</td>
|
||||
<td>PEA s</td>
|
||||
<td>SBC d,x</td>
|
||||
<td>INC d,x</td>
|
||||
<td>SBC [d],y</td>
|
||||
<td>SED i</td>
|
||||
<td>SBC a,y</td>
|
||||
<td>PLX s</td>
|
||||
<td>XCE i</td>
|
||||
<td>JSR (a,x)</td>
|
||||
<td>SBC a,x</td>
|
||||
<td>INC a,x</td>
|
||||
<td>SBC al,x</td>
|
||||
<td align="center">F</td></tr>
|
||||
<tr align="center">
|
||||
<td>MSD /<br>
|
||||
/ LSD</td>
|
||||
<td>0</td>
|
||||
<td>1</td>
|
||||
<td>2</td>
|
||||
<td>3</td>
|
||||
<td>4</td>
|
||||
<td>5</td>
|
||||
<td>6</td>
|
||||
<td>7</td>
|
||||
<td>8</td>
|
||||
<td>9</td>
|
||||
<td>A</td>
|
||||
<td>B</td>
|
||||
<td>C</td>
|
||||
<td>D</td>
|
||||
<td>E</td>
|
||||
<td>F</td>
|
||||
<td>\ MSD<br>
|
||||
LSD \</td>
|
||||
</tr>
|
||||
</table>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
240
MCS6500/65c02.txt
Normal file
240
MCS6500/65c02.txt
Normal file
@ -0,0 +1,240 @@
|
||||
----------------------------------------------------------------
|
||||
| |
|
||||
| |
|
||||
| Rockwell |
|
||||
| |
|
||||
| 666 5555555 CCCC 000 22222 |
|
||||
| 6 5 C C 0 0 2 2 |
|
||||
| 6 5 C 0 0 0 2 |
|
||||
| 666666 555555 C 0 0 0 222 |
|
||||
| 6 6 5 C 0 0 0 2 |
|
||||
| 6 6 5 C C 0 0 2 |
|
||||
| 66666 555555 CCCC 000 2222222 |
|
||||
| |
|
||||
| 65C02 CMOS MICROPROCESSOR Instruction Set Summary |
|
||||
| |
|
||||
| |
|
||||
| |
|
||||
| |
|
||||
| |
|
||||
| _________ _________ |
|
||||
| _| \__/ |_ ___ |
|
||||
| Vss |_|1 40|_| RES <-- |
|
||||
| _| |_ |
|
||||
| --> RDY |_|2 39|_| CLK2 --> |
|
||||
| _| |_ |
|
||||
| <-- CLK1 |_|3 38|_| NC |
|
||||
| ___ _| |_ |
|
||||
| --> IRQ |_|4 37|_| CLK0 <-- |
|
||||
| _| |_ |
|
||||
| NC |_|5 36|_| NC |
|
||||
| ___ _| |_ |
|
||||
| --> NMI |_|6 35|_| NC |
|
||||
| _| |_ _ |
|
||||
| --> SYNC |_|7 34|_| R/W --> |
|
||||
| _| |_ |
|
||||
| Vcc |_|8 33|_| DB7 <--> |
|
||||
| _| |_ |
|
||||
| <-- A0 |_|9 32|_| DB6 <--> |
|
||||
| _| |_ |
|
||||
| <-- A1 |_|10 65C02 31|_| DB5 <--> |
|
||||
| _| |_ |
|
||||
| <-- A2 |_|11 30|_| DB4 <--> |
|
||||
| _| |_ |
|
||||
| <-- A3 |_|12 29|_| DB3 <--> |
|
||||
| _| |_ |
|
||||
| <-- A4 |_|13 28|_| DB2 <--> |
|
||||
| _| |_ |
|
||||
| <-- A5 |_|14 27|_| DB1 <--> |
|
||||
| _| |_ |
|
||||
| <-- A6 |_|15 26|_| DB0 <--> |
|
||||
| _| |_ |
|
||||
| <-- A7 |_|16 25|_| A15 --> |
|
||||
| _| |_ |
|
||||
| <-- A8 |_|17 24|_| A14 --> |
|
||||
| _| |_ |
|
||||
| <-- A9 |_|18 23|_| A13 --> |
|
||||
| _| |_ |
|
||||
| <-- A10 |_|19 22|_| A12 --> |
|
||||
| _| |_ |
|
||||
| <-- A11 |_|20 21|_| Vss |
|
||||
| |______________________| |
|
||||
| |
|
||||
| |
|
||||
| |
|
||||
| |
|
||||
| |
|
||||
| |
|
||||
|Written by Jonathan Bowen |
|
||||
| Programming Research Group |
|
||||
| Oxford University Computing Laboratory |
|
||||
| 8-11 Keble Road |
|
||||
| Oxford OX1 3QD |
|
||||
| England |
|
||||
| |
|
||||
| Tel +44-865-273840 |
|
||||
| |
|
||||
|Created November 1984 |
|
||||
|Updated April 1985 |
|
||||
|Issue 1.1 Copyright (C) J.P.Bowen 1985|
|
||||
----------------------------------------------------------------
|
||||
----------------------------------------------------------------
|
||||
|Mnem. |Op|NVBDIZC|A#ZBIRX@|~|Description |Notes |
|
||||
|------+--+-------+--------+-+---------------------+-----------|
|
||||
|ADC s|6D|**---**| XxX XX|4|Add with Carry |A=A+s+C %|
|
||||
|AND s|2D|*----*-| XxX XX|4|Logical AND |A=A&s %|
|
||||
|ASL d|0E|*----**| xx |6|Arith. Shift Left |d={C,d,0}<-|
|
||||
|ASLA |0A|*----**|X |2|Arith. Shift Left |A={C,d,0}<-|
|
||||
|BBRb z|0F|-------| * X |2|Branch if Bit Reset |If s<b>=0 |
|
||||
|BBSb z|8F|-------| * X |2|Branch if Bit Set |If s<b>=1 |
|
||||
|BCC a|90|-------| X |2|Branch if Carry Clear|If C=0(4~)%|
|
||||
|BCS a|B0|-------| X |2|Branch if Carry Set |If C=1(4~)%|
|
||||
|BEQ a|F0|-------| X |2|Branch if Equal |If Z=1(4~)%|
|
||||
|BIT s|2C|**---*-| Xxx |4|Bit Test |A&s $|
|
||||
|BMI a|30|-------| X |2|Branch if Minus |If N=1(4~)%|
|
||||
|BNE a|D0|-------| X |2|Branch if Not Equal |If Z=0(4~)%|
|
||||
|BPL a|10|-------| X |2|Branch if Plus |If N=0(4~)%|
|
||||
|BRA a|80|-------| X |2|Branch Always |PC=a (4~)%|
|
||||
|BRK |00|--+-1--| X |7|Break(-[S]={PC+2,P}) |PC=[FFFEH] |
|
||||
|BVC a|50|-------| X |2|Branch if Overflw Clr|If V=0(4~)%|
|
||||
|BVS a|70|-------| X |2|Branch if Overflw Set|If V=1(4~)%|
|
||||
|CLC |18|------0| X |2|Clear Carry flag |C=0 |
|
||||
|CLD |D8|---0---| X |2|Clear Decimal mode |D=0 |
|
||||
|CLI |58|----0--| X |2|Clear Int. disable |I=0 |
|
||||
|CLV |B8|-0-----| X |2|Clear Overflow flag |V=0 |
|
||||
|CMP s|CD|*----**| XxX XX|4|Compare |A-s |
|
||||
|CPX s|EC|*----**| X** |4|Compare index reg. |X-s |
|
||||
|CPY s|CC|*----**| X** |4|Compare index reg. |Y-s |
|
||||
|DEC d|CE|*----*-| xx |6|Decrement |d=d-1 |
|
||||
|DECA |3A|*----*-|X |6|Decrement Acc. |A=A-1 |
|
||||
|DEX |CA|*----*-| X |2|Decrement index reg. |X=X-1 |
|
||||
|DEY |88|*----*-| X |2|Decrement index reg. |Y=Y-1 |
|
||||
|EOR s|4D|*----*-| XxX XX|4|Logical Exclusive OR |A=Axs %|
|
||||
|INC d|EE|*----*-| xx |6|Increment |d=d+1 |
|
||||
|INCA |1A|*----*-|X |6|Increment Acc. |A=A+1 |
|
||||
|INX |E8|*----*-| X |2|Increment index reg. |X=X+1 |
|
||||
|INY |C8|*----*-| X |2|Increment index reg. |Y=Y+1 |
|
||||
|JMP s|4C|-------| * X|3|Jump |PC=s $|
|
||||
|JSR s|20|-------| * |6|Jump to Subroutine |-[S]=PC+2=s|
|
||||
|LDA s|AD|*----*-| XxX XX|4|Load Accumulator |A=s %|
|
||||
|LDX s|AE|*----*-| Xyy |4|Load index register |X=s $%|
|
||||
|LDY s|AC|*----*-| Xxx |4|Load index register |Y=s %|
|
||||
|LSR d|4E|0----**| xx |6|Logical Shift Right |d=->{0,d,C}|
|
||||
|LSRA |4A|0----**|X |2|Logical Shift Right |A=->{0,A,C}|
|
||||
|NOP |EA|-------| X |2|No Operation | |
|
||||
|ORA s|0D|*----*-| XxX XX|4|Logical Inclusive OR |A=Avs |
|
||||
|PHA |48|-------| X |3|Push Accumulator |-[S]=A |
|
||||
|PHP |08|-------| X |3|Push status register |-[S]=P |
|
||||
|PHX |DA|-------| X |2|Push index register |-[S]=X |
|
||||
|PHY |5A|-------| X |2|Push index register |-[S]=Y |
|
||||
|PLA |68|-------| X |4|Pull Accumulator |A=[S]+ |
|
||||
|PLP |28|*******| X |4|Pull status register |P=[S]+ |
|
||||
|PLX |FA|-------| X |2|Pull index register |X=[S]+ |
|
||||
|PLY |7A|-------| X |2|Pull index register |Y=[S]+ |
|
||||
|RMBb d|07|-------| * |5|Reset Memory Bit |d<b>=0 |
|
||||
|ROL d|2E|*----**| xx |6|Rotate Left |d={C,d}<- |
|
||||
|ROLA |2A|*----**|X |2|Rotate Left Acc. |A={C,A}<- |
|
||||
|ROR d|6E|*----**| xx |6|Rotate Right |d=->{C,d} |
|
||||
|RORA |6A|*----**|X |2|Rotate Right Acc. |A=->{C,A} |
|
||||
|RTI |40|*******| X |6|Return from Interrupt|{PC,P}=[S]+|
|
||||
|RTS |60|-------| X |6|Return from Subr. |PC={[S]+}+1|
|
||||
|SBC s|ED|*----**| XxX XX|4|Subtract with Carry |A=A-s-C %|
|
||||
|SEC |38|------1| X |2|Set Carry flag |C=1 |
|
||||
|SED |F8|---1---| X |2|Set Decimal mode |D=1 |
|
||||
|SEI |78|----1--| X |2|Set Interrupt disable|I=1 |
|
||||
|SMBb d|87|-------| * |5|Set Memory Bit |d<b>=1 |
|
||||
|STA d|8D|-------| xX XX|4|Store Accumulator |d=A |
|
||||
|STX d|8E|-------| y* |4|Store index register |d=X |
|
||||
|STY d|8C|-------| x* |4|Store index register |d=Y |
|
||||
|STZ d|9C|-------| xx |4|Store Zero |d=0 $|
|
||||
|TAX |AA|*----*-| X |2|Transfer Accumulator |X=A |
|
||||
|TAY |A8|*----*-| X |2|Transfer Accumulator |Y=A |
|
||||
|TRB d|1C|**---*-| ** |2|Test and Reset Bits |d=~A&d |
|
||||
|TSB d|0C|**---*-| ** |2|Test and Set Bits |d=Avd |
|
||||
|TSX |BA|*----*-| X |2|Transfer Stack ptr |X=S |
|
||||
|TXA |8A|*----*-| X |2|Transfer index reg. |A=X |
|
||||
|TXS |9A|-------| X |2|Transfer index reg. |S=X |
|
||||
|TYA |98|*----*-| X |2|Transfer index reg. |A=Y |
|
||||
|------+--+-------+--------+-+---------------------------------|
|
||||
| |XX| | |X|Hexadecimal opcode/no. of cycles |
|
||||
----------------------------------------------------------------
|
||||
----------------------------------------------------------------
|
||||
|Mnemonic |NVBDIZC|A#ZBIRX@|Description |
|
||||
|---------+-------+--------+-----------------------------------|
|
||||
| P |-*01+ | |Unaff/affected/reset/set/stack set |
|
||||
| N |N | |Negative status (Bit 7) |
|
||||
| V | V | |Overflow status (Bit 6) |
|
||||
| B | B | |Break command indicator (Bit 4) |
|
||||
| D | D | |Decimal mode control (Bit 3) |
|
||||
| I | I | |Interrupt disable control (Bit 2) |
|
||||
| Z | Z | |Zero status (Bit 1) |
|
||||
| C | C| |Carry status (Bit 0) |
|
||||
|------------------+--------+----------------------------------|
|
||||
| |* |Only non-indexed mode valid |
|
||||
| |x |X and non-indexed mode valid |
|
||||
| |y |Y and non-indexed mode valid |
|
||||
| |X |All modes valid |
|
||||
|-----------------+--------+-----------------------------------|
|
||||
| | |Add XXH to opcode |+XXH| |
|
||||
| | |Subtract XXH from opcode |-XXH| |
|
||||
| | |Add X to number of cycles | |+X|
|
||||
| | |Subtract X from cycles | |-X|
|
||||
|-----------------+--------+---------------------------+----+--|
|
||||
| b | |Bit number (b=0-7) |+b0H| |
|
||||
| A |A |Accumulator | | |
|
||||
| #n | # |Immediate |-0CH|-2|
|
||||
| #n | # | ditto (opcode = XDH) | X9H| 2|
|
||||
| BIT #n | # | ditto (special case) | 89H| 2|
|
||||
| <n | Z |Zero page |-08H|-1|
|
||||
| STZ n | Z | ditto (special case) | 64H| 3|
|
||||
| n | * |Zero page (direct mode) |-08H|-1|
|
||||
| n,X | x |Zero page indexed (X) |+08H|+0|
|
||||
| n,Y | y |Zero Page indexed (Y) |+08H|+0|
|
||||
| >nn | B |Absolute |+00H|+0|
|
||||
| nn | * |Absolute (extended mode) |+00H|+0|
|
||||
| nn,X | x |Absolute indexed (X) |+10H|+0|
|
||||
| nn,Y | y |Absolute indexed (Y) |+0CH|+0|
|
||||
| LDX nn,Y | y | ditto (special case) | BEH| 4|
|
||||
| | I |Implicit | | |
|
||||
| a | R |Relative (PC=PC+1+offset) | |+2|
|
||||
| [nn,X] | x |Indexed indirect (X) |-0CH|+2|
|
||||
| [nn],Y | y |Indirect indexed (Y) |+04H|+1|
|
||||
| [nn] | @|Absolute indirect |+05H|+1|
|
||||
| JMP [nn] | @| ditto (special case) | 6CH| 5|
|
||||
|--------------------------+-----------------------------------|
|
||||
| A |Accumulator (8-bit) |
|
||||
| P |Processor status register (8-bit) |
|
||||
| PC |Program Counter (16-bit) |
|
||||
| S |Stack pointer (9-bit, MSB=1) |
|
||||
| X |Index register X (8-bit) |
|
||||
| Y |Index register Y (8-bit) |
|
||||
|--------------------------+-----------------------------------|
|
||||
| a |Relative address (-128 to +127) |
|
||||
| b |Bit number (0 to 7) |
|
||||
| d |Destination |
|
||||
| n |8-bit expression (0 to 255) |
|
||||
| nn |16-bit expression (0 to 65535) |
|
||||
| s |Source |
|
||||
| z |Zero page, relative address (n,a) |
|
||||
|--------------------------+-----------------------------------|
|
||||
| + - |Arithmetic addition/subtraction |
|
||||
| * / |Arithmetic multiplication/division |
|
||||
| & ~ |Logical AND/NOT |
|
||||
| v x |Logical inclusive/exclusive OR |
|
||||
| <- -> |Rotate left/right |
|
||||
| [ ] |Indirect addressing |
|
||||
| [ ]+ |Post-increment indirect addressing |
|
||||
| -[ ] |Pre-decrement indirect addressing |
|
||||
| { } |Combination of operands |
|
||||
| < > |Bit number |
|
||||
| $ |Special case for addressing mode |
|
||||
| % |~s=~s+1 if crossing page boundary |
|
||||
|--------------------------+-----------------------------------|
|
||||
|0000H to 00FFH |Page 0 (see zero page addressing) |
|
||||
|0100H to 01FFH |Page 1 (stack area, 01FFH = start) |
|
||||
|XX00H to XXFFH |Page n (where n=XXH) |
|
||||
|FFFAH to FFFBH |Non maskable interrupt vector(NMI) |
|
||||
|FFFCH to FFFDH |Reset (RES) vector |
|
||||
|FFFEH to FFFFH |Interrupt Request vector (IRQ) |
|
||||
|FFFEH to FFFFH |Break command vector (see BRK) |
|
||||
----------------------------------------------------------------
|
||||
16
MCS6500/README.md
Normal file
16
MCS6500/README.md
Normal file
@ -0,0 +1,16 @@
|
||||
This subfolder contains the documents and other stuff for 6502 and 65816 CPU family.
|
||||
|
||||
[Main Wikipedia article on this family](https://en.wikipedia.org/wiki/MOS_Technology_6502)
|
||||
[Main Wikipedia article on this family](https://en.wikipedia.org/wiki/WDC_65816/65802)
|
||||
|
||||
| Files | Description | Source |
|
||||
| ----- | ----------- | ------ |
|
||||
| 6502_opcode_table.htm | 6502 opcode table in HTML format | URL not determined |
|
||||
| 65816_opcode_table.htm | 65816 opcode table in HTML format | The-Blue-Wizard created it; in public domain |
|
||||
| 65c02.txt | 65C02 Quick Card | URL not determined |
|
||||
| 65c816.txt | | URL not determined |
|
||||
| mcs6500_family_programming_manual.pdf | | |
|
||||
| mos_6510_mpu.pdf | | |
|
||||
| w65c816s.pdf | WDC 65C816 data sheet | Believed to be taken from http://www.6502.org |
|
||||
| wdc_65816_programming_manual.pdf | WDC 65C816 Programming Manual | Believed to be taken from http://www.6502.org |
|
||||
| wdc_w65c02s_oct_19_2010.pdf | WDC 65C02S data sheet | Believed to be taken from http://www.6502.org |
|
||||
BIN
MCS6500/w65c816s.pdf
Normal file
BIN
MCS6500/w65c816s.pdf
Normal file
Binary file not shown.
BIN
MCS6500/wdc_65816_programming_manual.pdf
Normal file
BIN
MCS6500/wdc_65816_programming_manual.pdf
Normal file
Binary file not shown.
BIN
MCS6500/wdc_w65c02s_oct_19_2010.pdf
Normal file
BIN
MCS6500/wdc_w65c02s_oct_19_2010.pdf
Normal file
Binary file not shown.
9
PowerPC/PowerPC/README.md
Normal file
9
PowerPC/PowerPC/README.md
Normal file
@ -0,0 +1,9 @@
|
||||
This subfolder contains the documents and other stuff for PowerPC CPU family.
|
||||
|
||||
[Main Wikipedia article on this family](https://en.wikipedia.org/wiki/PowerPC)
|
||||
|
||||
| Files | Description | Source |
|
||||
| ----- | ----------- | ------ |
|
||||
| es-archpub1.pdf | PowerPC User ISA - Book I | URL not determined |
|
||||
| es-archpub2.pdf | PowerPC Virtual Environment Architecture - Book II | URL not determined |
|
||||
| es-archpub3.pdf | PowerPC Operating Environment Architecture - Book III | URL not determined |
|
||||
BIN
PowerPC/PowerPC/es-archpub1.pdf
Normal file
BIN
PowerPC/PowerPC/es-archpub1.pdf
Normal file
Binary file not shown.
BIN
PowerPC/PowerPC/es-archpub2.pdf
Normal file
BIN
PowerPC/PowerPC/es-archpub2.pdf
Normal file
Binary file not shown.
BIN
PowerPC/PowerPC/es-archpub3.pdf
Normal file
BIN
PowerPC/PowerPC/es-archpub3.pdf
Normal file
Binary file not shown.
26
README.md
26
README.md
@ -1,10 +1,11 @@
|
||||
This repository contains the documentations for various CPUs. It may contain data sheets, programmer's references, quick cards, and the like.
|
||||
This repository contains the documentations for various CPUs. It may contain data sheets, programmer's manuals, quick reference cards, and the like.
|
||||
|
||||
| Subfolders | Description |
|
||||
| ---------- | ----------- |
|
||||
| 8085 | Intel 8085 |
|
||||
| Alpha | Compaq Alpha |
|
||||
| ARM | |
|
||||
| Alpha | Compaq Alpha family |
|
||||
| ARCompact | |
|
||||
| ARM | ARM CPU family |
|
||||
| AVR | |
|
||||
| Burroughs | |
|
||||
| CRIS | |
|
||||
@ -13,13 +14,13 @@ This repository contains the documentations for various CPUs. It may contain dat
|
||||
| F18A | |
|
||||
| H8 | |
|
||||
| HD6301 | |
|
||||
| IA-64 | Intel IA-64 |
|
||||
| IA-64 | Intel IA-64 family |
|
||||
| KDF9 | |
|
||||
| M68000 | Motorola 680x0 CPU family |
|
||||
| MARC4 | |
|
||||
| MC6809 | Motorola 6809 and Hitachi 6309 |
|
||||
| MCS-51 | |
|
||||
| MCS6500 | |
|
||||
| MCS6500 | 6502 and 65816 CPU family |
|
||||
| MIPS | |
|
||||
| MN103 | |
|
||||
| MSP430 | |
|
||||
@ -28,14 +29,19 @@ This repository contains the documentations for various CPUs. It may contain dat
|
||||
| PDP-1 | DEC PDP-1 |
|
||||
| PDP-10 | DEC PDP-10 |
|
||||
| PDP-8 | DEC PDP-8 |
|
||||
| PIC | |
|
||||
| PowerPC | IBM PowerPC |
|
||||
| PIC16 | |
|
||||
| PIC18 | |
|
||||
| PICmicro | |
|
||||
| PowerPC | PowerPC |
|
||||
| PSC1000 | |
|
||||
| RISC-V | |
|
||||
| RTX2000 | |
|
||||
| SPARC | |
|
||||
| SPARC | Sun SPARC CPU family |
|
||||
| SuperH | Hitachi SuperH |
|
||||
| TMS320C3x | |
|
||||
| VAX | DEC VAX |
|
||||
| VEB50 | |
|
||||
| x86-64 | |
|
||||
| Xtensa | |
|
||||
| Xtensa | Tensilica Xtensa |
|
||||
| Z80 | Zilog Z80 |
|
||||
| zArchitecture | |
|
||||
| zArchitecture | IBM z/Architecture family |
|
||||
|
||||
28088
RS08/MC9RS08LA8RM.pdf
Normal file
28088
RS08/MC9RS08LA8RM.pdf
Normal file
File diff suppressed because one or more lines are too long
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Reference in New Issue
Block a user