mirror of
https://github.com/larsbrinkhoff/awesome-cpus
synced 2025-11-04 02:06:02 +03:00
195 lines
5.9 KiB
Plaintext
195 lines
5.9 KiB
Plaintext
68000abc.txt
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Instruction set of the 68000 in alphabetical order
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1988/wjvg
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0 2 3 4 5
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abcd Ds,Dd 1100 ddd100 000sss
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abcd -(As),-(Ad) 1100 ddd100 001sss
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add.z a,Dd 1101 ddd0zz aaaaaa
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add.z Ds,a 1101 sss1zz aaaaaa
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adda.z a,Ad 1101 dddz11 aaaaaa
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addi.z #kz,a 0000 0110zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk
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addq.z #k3,a 0101 kkk0zz aaaaaa
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addx.z Ds,Dd 1101 ddd1zz 000sss
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addx.z -(As),-(Ad) 1101 ddd1zz 001sss
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and.z a,Dd 1100 ddd0zz aaaaaa
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and.z Ds,a 1100 sss1zz aaaaaa
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andi.z #kz,a 0000 0010zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk
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asld.z Ds,Dd 1110 sss1zz 100ddd
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asld.z #k,Dd 1110 kkk1zz 000ddd
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asld.w #1,a 1110 000111 aaaaaa
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asrd.z Ds,Dd 1110 sss0zz 100ddd
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asrd.z #k,Dd 1110 kkk0zz 000ddd
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asrd.w #1,a 1110 000011 aaaaaa
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bcc label 0110 ccccll llllll if zero, a 16bit address follows
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bra label 0110 0000ll llllll if zero, a 16bit address follows
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bsr label 0110 0001ll llllll if zero, a 16bit address follows
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bchg #n,a 0000 100001 aaaaaa 00000000 000nnnnn
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bchg Ds,a 0000 sss101 aaaaaa
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bclr #n,a 0000 100010 aaaaaa 00000000 000nnnnn
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bclr Ds,a 0000 sss110 aaaaaa
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bset #n,a 0000 100011 aaaaaa 00000000 000nnnnn
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bset Ds,a 0000 sss111 aaaaaa
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btst #n,a 0000 100000 aaaaaa 00000000 000nnnnn
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btst Ds,a 0000 sss100 aaaaaa
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chk.w a,Dd 0100 ddd110 aaaaaa
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clr.z a 0100 0010zz aaaaaa
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cmp.z a,Dd 1011 ddd0zz aaaaaa
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cmpa.z a,Ad 1011 dddz11 aaaaaa
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cmpi.z #kz,a 0000 1100zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk
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cmpm.z Ds,Dd 1011 ddd1zz 000sss
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cmpm.z (As)+,(Ad)+ 1011 ddd1zz 001sss
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db(cc) Ds,label 0101 cccc11 001sss llllllll llllllll
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divs.w a,Dd 1000 ddd111 aaaaaa
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divu.w a,Dd 1000 ddd011 aaaaaa
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eor.z a,Dd 1011 ddd1zz aaaaaa
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eori.z #kz,a 0000 1010zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk
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exg.l As,Ad 1100 ddd101 001sss
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exg.l Ds,Dd 1100 ddd101 000sss
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exg.l As,Dd 1100 ddd110 001sss
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ext.z Dd 0100 10001z 000ddd
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jmp a 0100 111011 aaaaaa
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jsr a 0100 111010 aaaaaa
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lea a,Ad 0100 ddd111 aaaaaa
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link As,d16 0100 111001 010sss dddddddd dddddddd
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lsld.z Ds,Dd 1110 sss1zz 101ddd
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lsld.z #k,Dd 1110 kkk1zz 001ddd
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lsld.w #1,a 1110 001111 aaaaaa
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lsrd.z Ds,Dd 1110 sss0zz 101ddd
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lsrd.z #k,Dd 1110 kkk0zz 001ddd
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lsrd.w #1,a 1110 001011 aaaaaa
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move SR,a 0100 000011 aaaaaa
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move a,CCR 0100 010011 aaaaaa
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move a,SR 0100 011011 aaaaaa
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move As,USP 0100 111001 100sss
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move USP,Ad 0100 111001 101ddd
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move.b as,ad 0001 dddddd ssssss (dddddd reversed)
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move.l as,ad 0010 dddddd ssssss (dddddd reversed)
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move.w as,ad 0011 dddddd ssssss (dddddd reversed)
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movem.z a,reg-list 0100 11001z aaaaaa a6543210 d6543210
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movem.z reg-list,a 0100 10001z aaaaaa a6543210 d6543210
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movep.z Ds,d16(Ad) 0000 sss11z 001ddd dddddddd dddddddd
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movep.z d16(As),Dd 0000 ddd10z 001sss dddddddd dddddddd
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moveq.l #k8,Dd 0111 ddd0kk kkkkkk
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muls.w a,Dd 1100 ddd111 aaaaaa
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mulu.w a,Dd 1100 ddd011 aaaaaa
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nbcd a 0100 100000 aaaaaa
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neg.z a 0100 0100zz aaaaaa
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negx.z a 0100 0000zz aaaaaa
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nop 0100 111001 110001
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not.z a 0100 0110zz aaaaaa
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or.z a,Dd 1000 ddd0zz aaaaaa
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or.z Ds,a 1000 sss1zz aaaaaa
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ori.z #kz,a 0000 0000zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk
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pea a 0100 100001 aaaaaa
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reset 0100 111001 110000
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rold.z Ds,Dd 1110 sss1zz 111ddd
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rold.z #k,Dd 1110 kkk1zz 011ddd
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rold.w #1,a 1110 011111 aaaaaa
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rord.z Ds,Dd 1110 sss0zz 111ddd
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rord.z #k,Dd 1110 kkk0zz 011ddd
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rord.w #1,a 1110 011011 aaaaaa
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roxld.z Ds,Dd 1110 sss1zz 110ddd
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roxld.z #k,Dd 1110 kkk1zz 010ddd
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roxld.w #1,a 1110 010111 aaaaaa
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roxrd.z Ds,Dd 1110 sss0zz 110ddd
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roxrd.z #k,Dd 1110 kkk0zz 010ddd
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roxrd.w #1,a 1110 010011 aaaaaa
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rte 0100 111001 110011
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rtr 0100 111001 110111
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rts 0100 111001 110101
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sbcd Ds,Dd 1000 ddd100 000sss
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sbcd -(As),-(Ad) 1000 ddd100 001sss
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stcc.b a 0101 cccc11 aaaaaa
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stop #k16 0100 111001 110010 kkkkkkkk kkkkkkkk
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sub.z Ds,a 1001 sss1zz aaaaaa
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sub.z a,Dd 1001 ddd0zz aaaaaa
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subi.z #kz,a 0000 0100zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk
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suba.z a,Ad 1001 dddz11 aaaaaa
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subq.z #k3,a 0101 kkk1zz aaaaaa
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subx.z Ds,Dd 1001 ddd1zz 000sss
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subx.z -(As),-(Ad) 1001 ddd1zz 001sss
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swap.w Dd 0100 100001 000ddd
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tas.b a 0100 101011 aaaaaa
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trap vector 0100 111001 00vvvv
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trapv 0100 111001 110110
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tst.z a 0100 1010zz aaaaaa
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unlk Ad 0100 111001 011ddd
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general subfields
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zz 00=b, 01=w, 10=l
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z 0=w, 1=l
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kkk immediate data in addq etc.: 0==8
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immediate data in movq is sign extended to 32bits
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shift count also represents 1..8 (how?)
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addresssing modes (aaaaaa):
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000 rrr Dr
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001 rrr Ar
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010 rrr (Ar)
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011 rrr (Ar)+
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100 rrr -(Ar)
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101 rrr d16(Ar) dddddddd dddddddd
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110 rrr d8(Ar,ix) aiiiz000 dddddddd
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111 000 addr16 dddddddd dddddddd
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111 001 addr32 dddddddd dddddddd ddddddddd dddddddd
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111 010 d16(PC) dddddddd dddddddd
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111 011 d8(PC,ix) aiiiz000 dddddddd
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111 100 imm/implied
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flags:
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0000 t allways or bra ipv btr
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0001 f never or bsr ipv bnv
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0010 hi
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0011 ls
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0100 cc
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0101 cs
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0110 ne
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0111 eq
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1000 vc
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1001 vs
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1010 pl
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1011 mi
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1100 ge
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1101 lt
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1110 gt
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1111 le
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