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370 lines
18 KiB
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<!-- saved from url=(0051)http://www.village.org/pdp11/faq.pages/PDPinst.html -->
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<HTML><HEAD><TITLE>The PDP-11 FAQ</TITLE>
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<META http-equiv=Content-Type content="text/html; charset=windows-1252">
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<META content="MSHTML 6.00.2900.3059" name=GENERATOR></HEAD>
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<BODY>
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<H1><A name=PDPinst>What is the PDP-11 instruction set?</A></H1>
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<P>The instruction set of the PDP-11 was designed towards a clean, general,
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symmetric instruction set. It can be used as a register-based, stack-based, or
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memory-based machine, depending on the programmer's preferences. Interrupt
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responsiveness is also important, supported with multiple interrupt levels for
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real-time computing as well as allowing for a separate interrupt handler for
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each device that generates interrupts. </P>
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<P>Word length is 16 bits with the leftmost, most significant bit (MSB) being
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bit 15. There are eight general registers of 16 bits each. Register 7 is the
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program counter (PC) and, by convention, Register 6 is the stack pointer (SP).
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There is also a Processor Status Register/Word (PSW) which indicates the 4
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condition code bits (N, Z, V, C), the Trace Trap bit, processor interrupt
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priority, and 4 bits for current and previous operating modes. Addressing on the
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-11 is linear from memory address 0 through 177777. Memory management allows
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access to physical memory with addresses of up to 22 bits (17777777). All I/O
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devices, registers etc are addressed as if they were part of memory. These live
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in the 4KW of reserved memory space at the top of the addressing range.
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Additionally, on most implementations of the PDP-11 architecture, the
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processor's registers are memory-mapped to the range 17777700-17777717 (there
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are many control registers beyond just the general registers, the specifics vary
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between implementations). Thus Register 2 (R2) has an address of 17777702. All
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word memory addresses are even, except for registers. In byte operations, an
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even address specifies the least-significant byte and an odd address specifies
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the most-significant byte. Specifying an odd byte in a word operation will
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return an odd address trap. Memory addresses from 0 to 400 octal are reserved
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for various exception traps such as timeouts, reserved instructions, parity,
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etc., and device interrupts. </P>
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<P>Addressing for the Single Operand, Double Operand and Jump instructions is
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achieved via six bits: </P><PRE> _ _ _ _ _ _
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|x|x|x|_|_|_|
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|Mode |Reg |
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</PRE>
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<P>where the modes are as follows: (Reg = Register, Def = Deferred) </P><PRE> Mode 0 Reg Direct addressing of the register
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Mode 1 Reg Def Contents of Reg is the address
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Mode 2 AutoIncr Contents of Reg is the address, then Reg incremented
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Mode 3 AutoIncrDef Content of Reg is addr of addr, then Reg Incremented
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Mode 4 AutoDecr Reg is decremented then contents is address
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Mode 5 AutoDecrDef Reg is decremented then contents is addr of addr
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Mode 6 Index Contents of Reg + Following word is address
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Mode 7 IndexDef Contents of Reg + Following word is addr of addr
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</PRE>
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<P>Note that the right-most bit of the mode is an indirection bit.
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<P>Although not special cases, when dealing with R7 (aka the PC), some of these
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operations are called different things: </P><PRE> _ _ _ _ _ _
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|x|x|x|1|1|1|
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|Mode | R7 |
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Mode 2 Immediate Operand follows the instruction
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Mode 3 Absolute Address of Operand follows the instruction
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Mode 6 Relative Instr address+4+Next word is Address
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Mode 7 RelativeDef Instr address+4+Next word is Address of address
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</PRE>
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<P>Mainstream instructions are broken into Single operand and Double operand
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instructions, which in turn can be word or byte instructions. </P>
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<H2>Double Operand Instructions</H2><PRE> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
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|b|i|i|i|s|s|s|s|s|s|d|d|d|d|d|d|
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| | | : | : |
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| | Op | Source | Dest |
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</PRE>
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<P>Bit 15, b, generally selects between word-sized (b=0) and byte-sized (b=1)
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operands. In the table below, the mnemonics and names are given in the order
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b=0/b=1. </P>
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<P>The double operand instructions are: </P>
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<DL>
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<DT>b 000 ssssss dddddd
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<DD>Non-double-operand instructions.
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<P></P>
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<DT>b 001 ssssss dddddd -- MOV/MOVB <I>Move Word/Byte</I>
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<DD>Moves a value from source to destination.
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<P></P>
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<DT>b 010 ssssss dddddd -- CMP/CMPB <I>Compare Word/Byte</I>
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<DD>Compares values by subtracting the destination from the source, setting
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the condition codes, and then discarding the result of the subtraction.
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<P></P>
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<DT>b 011 ssssss dddddd -- BIT/BITB <I>Bit Test Word/Byte</I>
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<DD>Performs a bit-wise AND of the source and the destination, sets the
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condition codes, and then discards the result of the AND.
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<P></P>
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<DT>b 100 ssssss dddddd -- BIC/BICB <I>Bit Clear Word/Byte</I>
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<DD>For each bit set in the source, that bit is cleared in the destination.
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This is accomplished by taking the ones-complement of the source and ANDing it
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with the destination. The result of the AND is stored in the destination.
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<P></P>
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<DT>b 101 ssssss dddddd -- BIS/BISB <I>Bit Set Word/Byte</I>
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<DD>For each bit set in the source, that bit is set in the destination. This
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is accomplished by ORing the source and destination, and storing the result in
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the destination.
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<P></P>
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<DT>b 110 ssssss dddddd -- ADD/SUB <I>Add/Subtract Word</I>
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<DD>Adds the source and destination, storing the results in the destination.
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<P>Subtracts the source from the destination, storing the results in the
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destination.
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<P>Note that this is a special case for b=1, in that it does not indicate that
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byte-wide operands are used.
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<P></P>
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<DT>b 111 xxxxxx xxxxxx
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<DD>Arithmetic functions not supported by all implementations of the PDP-11
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architecture. </DD></DL>
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<H2>Single Operand Instructions</H2><PRE> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
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|b|0|0|0|i|i|i|i|i|i|d|d|d|d|d|d|
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| | | : | : |
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| | |Instruction| Dest |
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</PRE>
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<P>Bit 15, b, generally selects between word-sized (b=0) and byte-sized (b=1)
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operands. In the table below, the mnemonics and names are given in the order
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b=0/b=1. Unless otherwise stated, the operand is read for the data to operate
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on, and the result is then written over that data. </P>
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<P>The single operand instructions are: </P>
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<DL>
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<DT>b 000 000 011 dddddd -- SWAB/BPL <I>Swap Bytes/Branch Plus</I>
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<DD>Swap bytes exchanges the two bytes found in the destination, writing the
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result back to it.
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<P>The branch (b=1) is described in the section on branches, below.
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<P>Note that SWAB is actually a bit pattern from the range reserved for
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branches. This particular pattern is otherwise unused, as it would be a
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modification of BR, Branch Always, which has no obvious semantics.
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<P></P>
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<DT>b 000 101 000 dddddd -- CLR/CLRB <I>Clear Word/Byte</I>
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<DD>Sets all the bits in destination to zero.
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<P></P>
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<DT>b 000 101 001 dddddd -- COM/COMB <I>Complement Word/Byte</I>
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<DD>Calculates the ones-complement of the operand, and stores it. The
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ones-complement is formed by inverting each bit (0->1, 1->0)
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independently.
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<P></P>
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<DT>b 000 010 010 dddddd -- INC/INCB <I>Increment Word/Byte</I>
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<DD>Adds one to the destination.
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<P></P>
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<DT>b 000 101 011 dddddd -- DEC/DECB <I>Decrement Word/Byte</I>
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<DD>Subtracts one from the destination.
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<P></P>
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<DT>b 000 101 100 dddddd -- NEG/NEGB <I>Negate Word/Byte</I>
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<DD>Calculates the twos-complement of the operand, and stores it. The
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twos-complement is formed by adding one to the ones-complement. The effect is
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the same as subtracting the operand from zero.
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<P></P>
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<DT>b 000 101 101 dddddd -- ADC/ADCB <I>Add Carry Word/Byte</I>
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<DD>Adds the current value of the carry flag to the destination. This is
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useful for implementing arithmetic subroutines with more than word-sized
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operands.
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<P></P>
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<DT>b 000 101 110 dddddd -- SBC/SBCB <I>Subtract Carry Word/Byte</I>
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<DD>Subtracts the current value of the carry flag from the destination. This
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is useful for implementing arithmetic subroutines with more than word-sized
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operands.
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<P></P>
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<DT>b 000 101 111 dddddd -- TST/TSTB <I>Test Word/Byte</I>
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<DD>Sets the N (negative) and Z (zero) condition codes based on the value of
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the operand.
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<P></P>
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<DT>b 000 110 000 dddddd -- ROR/RORB <I>Rotate Right Word/Byte</I>
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<DD>Rotates the bits of the operand one position to the right. The right-most
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bit is placed in the carry flag, and the carry flag is copied to the left-most
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bit (bit 15) of the operand.
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<P></P>
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<DT>b 000 110 001 dddddd -- ROL/ROLB <I>Rotate Left Word/Byte</I>
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<DD>Rotates the bits of the operand one position to the left. The left-most
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bit is placed in the carry flag, and the carry flag is copied to the
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right-most bit (bit 0) of the operand.
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<P></P>
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<DT>b 000 110 010 dddddd -- ASR/ASRB <I>Arithmetic Shift Right Word/Byte</I>
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<DD>Shifts the bits of the operand one position to the right. The left-most
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bit is duplicated. The effect is to perform a signed division by 2.
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<P></P>
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<DT>b 000 110 011 dddddd -- ASL/ASLB <I>Arithmetic Shift Left Word/Byte</I>
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<DD>Shifts the bits of the operand one position to the left. The right-most
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bit is set to zero. The effect is to perform a signed multiplication by 2.
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<P></P>
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<DT>b 000 110 100 dddddd -- MARK/MTPS <I>Mark/Move To Processor Status</I>
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<DD>Mark is used as part of one of the subroutine call/ return sequences. The
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operand is the number of parameters.
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<P>MTPS is only on LSI-11s, and is used to move a byte to the processor status
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word. This is needed because the LSI-11 does not support accessing registers
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via memory addresses.
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<P></P>
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<DT>b 000 110 101 dddddd -- MFPI/MFPD <I>Move From Prev. Instruction/Data</I>
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<DD>Pushes a word onto the current R6 stack from the operand address in the
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previous address space, as indicated in the PSW. On PDP-11s that do not
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support separate instruction and data spaces, MFPD is treated the same as
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MFPI.
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<P></P>
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<DT>b 000 110 110 dddddd -- MTPI/MTPD <I>Move To Previous Instruction/Data</I>
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<DD>Pops a word from the current stack as indicated in the PSW to the operand
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address in the previous address space, as indicated in the PSW. On PDP-11s
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that do not support separate instruction and data spaces, MTPD is treated the
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same as MTPI.
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<P></P>
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<DT>b 000 110 111 dddddd -- SXT/MFPS <I>Sign Extend/Move From Processor
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Status</I>
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<DD>SXT sets the destination to zero if the N (negative) flag is clear, or to
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all ones if N is set. This is useful for implementing arithmetic subroutines
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with more than word-sized operands.
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<P>MFPS copies the processor status byte to the indicated register. This only
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exists on LSI-11s, and is needed there because those systems don't support
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accessing registers via memory addresses. </P></DD></DL>
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<H2>Branches</H2><PRE> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
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|b|0|0|0|b|b|b|b|d|d|d|d|d|d|d|d|
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| Branch Code | Destination |
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</PRE>
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<P>The destination of a branch is +127 to -128 words from the word following the
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branch instruction itself. This seems slightly odd, until you realize the
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sequence of events: the branch instruction is read from memory and the PC
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incremented. If the branch is to be taken, the offset is then added to the
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current value of the PC. Since the PC has already been incremented, the offset
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is thus relative to the following word. Note that all branch instructions are
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one word long. </P>
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<P>The various branches test the values of specific condition codes, and if the
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tests succeed, the branch is taken. The condition codes are N (negative), Z
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(zero), C (carry), and V (overflow). In the table below, the branch tests are
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shown as boolean expressions. `x' stands for exclusive-OR. `v' stands for
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inclusive-OR. </P>
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<DL compact>
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<DT>0 000 000 1dd dddddd
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<DD>BR: Branch Always
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<DT>0 000 001 0dd dddddd
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<DD>BNE: Branch if Not Equal (Z==0)
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<DT>0 000 001 1dd dddddd
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<DD>BEQ: Branch if EQual (Z==1)
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<DT>0 000 010 0dd dddddd
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<DD>BGE: Branch if Greater or Equal (NxV == 0)
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<DT>0 000 010 1dd dddddd
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<DD>BLT: Branch if Less Than (NxV == 1)
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<DT>0 000 011 0dd dddddd
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<DD>BGT: Branch if Greater Than (Zv(NxV) == 0)
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<DT>0 000 011 1dd dddddd
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<DD>BLE: Branch if Less or Equal (Zv(NxV) == 1)
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<DT>1 000 000 0dd dddddd
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<DD>BPL: Branch if PLus (N == 0)
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<DT>1 000 000 1dd dddddd
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<DD>BMI: Branch if MInus (N == 1)
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<DT>1 000 001 0dd dddddd
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<DD>BHI: Branch if HIgher (C==0 and Z==0)
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<DT>1 000 001 1dd dddddd
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<DD>BLOS: Branch if Lower Or Same (CvZ == 1)
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<DT>1 000 010 0dd dddddd
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<DD>BVC: Branch if oVerflow Clear (V == 0)
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<DT>1 000 010 1dd dddddd
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<DD>BVS: Branch if oVerflow set (V == 1)
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<DT>1 000 011 0dd dddddd
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<DD>BCC: Branch if Carry Clear (C == 0) <BR><I>also known as</I><BR>BHIS:
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Branch if Higher Or Same
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<DT>1 000 011 1dd dddddd
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<DD>BCS: Branch if Carry Set (C == 1) <BR><I>also known as</I><BR>BLO: Branch
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if Lower </DD></DL>
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<H2>Condition Code Operations</H2><PRE> _ _ _ _ _ _ _ _ _ _:_ _ _:_ _ _
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|0|0|0|0|0|0|0|0|1|0|1|s|N|Z|V|C|
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| O p c o d e | | Mask |
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</PRE>
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<P>General opcode 000240x. Set/Clear corresponding bits depending on sense of
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bit 04 (set=1, clear=0). Codes 240 and 260 set/clear no bits and are, thus, used
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as NOP. Although specific mnemonic are provided for each flag and all flags, any
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combination may actually be set or cleared at a time. </P>
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<P>General mnemonics are: </P>
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<DL compact>
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<DT>CLx
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<DD>Clear x, where x is N, Z, V, or C
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<DT>SEx
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<DD>Set x, where x is N, Z, V, or C
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<DT>CCC
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<DD>Clear all condition codes
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<DT>SCC
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<DD>Set all condition codes </DD></DL><BR>
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<DL compact>
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<DT>0 000 000 010 1s0 000
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<DD>NOP/NOP: No Operation
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<DT>0 000 000 010 1s0 001
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<DD>SEC/CLC: Set/Clear Carry
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<DT>0 000 000 010 1s0 010
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<DD>SEV/CLV: Set/Clear Overflow
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<DT>0 000 000 010 1s0 100
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<DD>SEZ/CLZ: Set/Clear Zero
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<DT>0 000 000 010 1s1 000
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<DD>SEN/CLN: Set/Clear Negative
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<DT>0 000 000 010 1s1 111
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<DD>SCC/CCC: Set/Clear All Condition Codes </DD></DL>
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<H2>Other, Miscellaneous</H2><PRE> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
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|0|0|0|0|1|0|0|s|s|s|d|d|d|d|d|d|
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| Opcode |Stack|Destination|
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</PRE>
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<P>
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<DL compact>
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<DT>0 000 100 sss dddddd -- JSR <I>Jump to Subroutine</I>
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<DD>The actual sequence of steps taken is: <PRE> MOV <source>,-(R6)
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MOV PC,<source>
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JMP <destination>
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</PRE><BR>
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<P>Thus, it loads the calling address into the specified source register
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(after saving the original contents). It then jumps to the destination. The
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fun part is (as usual with the PDP-11) that the PC is a general register, and
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the description above is the result when the PC is used as the source.
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</P></DD></DL><PRE> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
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|0|0|0|0|0|0|0|0|1|0|0|0|0|s|s|s|
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| Opcode |Stack|
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</PRE>
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<P>
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<DL compact>
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<DT>0 000 000 010 000 sss -- RTS <I>ReTurn from Subroutine</I>
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<DD>Undoes the effects of a JSR. For predictable results, it is suggested that
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the same register should be used as was named in the corresponding JSR
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instruction.
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<P>The actual operations involved are: <PRE> MOV <source>,PC
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MOV (R6)+,<source>
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</PRE><BR>
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<P>This is the reverse of JSR. Obviously, the finesse here too is that you can
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use the PC, to get what people normally consider a CALL/RETURN function.
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<P>Why is it done like this then? Well, consider this example: <PRE> ...
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JSR R0,FOO
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.WORD A
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.WORD B
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MOV R1,C
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...
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FOO: MOV @(R0)+,R1
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ADD @(R0)+,R1
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RTS R0
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</PRE><BR>
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<P>This type of parameter passing is used extensively in the PDP-8 and
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PDP-10), for example. Also, the FORTRAN runtime system on the PDP-11 do it
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this way. (It is fairly easy to write a compiler who generates such a calling
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sequence, and then have a library of functions which expect this calling
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convention.) </P></DD></DL><PRE> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
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|0|0|0|0|0|0|0|0|0|1|d|d|d|d|d|d|
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| Opcode |Destination|
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</PRE>
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<P>
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<DL compact>
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<DT>0 000 000 001 ddd ddd -- JMP <I>JuMP</I>
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<DD>Loads the destination address into the PC, thus effecting an unconditional
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jump. Note that a trap will occur on some systems if an odd address is
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specified. On others, the destination is silently rounded down to the
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next-lower even address (i.e., the right-most bit is ignored). </DD></DL><PRE> _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
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|0|0|0|0|0|0|0|0|0|0|0|0|0|i|i|i|
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| | | | | | Op |
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</PRE>
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<P>
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<DL compact>
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<DD>0 000 000 000 000 000 -- HALT <I>Halts the machine</I>
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<DD>Ceases I/O, and gives control to the console. Operator intervention is
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required to continue or restart the system.
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<P></P>
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<DD>0 000 000 000 000 001 -- WAIT <I>WAIT for interrupt</I>
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<DD>0 000 000 000 000 010 -- RTI <I>ReTurn from Interrupt</I>
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<DD>0 000 000 000 000 100 -- BPT <I>BreakPoint Trap</I>
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<DD>0 000 000 000 000 101 -- RESET <I>Initializes the system</I> </DD></DL>
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<P>The following opcode ranges are all unused (using three bits per digit):
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<P>
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<DL compact>
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<DD>00 00 07 .. 00 00 77
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<DD>00 02 10 .. 00 02 27
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<DD>00 70 00 .. 00 77 77
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<DD>07 50 40 .. 07 67 77
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<DD>10 64 00 .. 10 64 77
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<DD>10 67 00 .. 10 77 77 </DD></DL>
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<P>Other arithmetic and floating point instructions were added to the basic set
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over the years, but those listed above form the core PDP-11 instruction set.
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<P>There is a comparison of PDP-11 and 80x86 floating point formats available
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at: <A
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href="ftp://ftp.dbit.com/pub/pdp11/info/fpp.txt">ftp://ftp.dbit.com/pub/pdp11/info/fpp.txt</A>
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<HR>
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<A href="http://www.village.org/pdp11/faq.html">Table of Contents</A>
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