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https://github.com/larsbrinkhoff/awesome-cpus
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287 lines
20 KiB
Plaintext
287 lines
20 KiB
Plaintext
Full eZ80 Opcode List
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=====================
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File: http://mdfs.net/Docs.Comp.eZ80.OpList - Update: 0.11
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Author: J.G.Harston - Date: 15-04-1998
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nn nn DD nn CB nn FD CB dd nn ED nn
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-----------------------------------------------------------------------------------
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00 NOP - RLC B - IN0 B,(&00)
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01 LD BC,&0000 - RLC C - OUT0 (&00),B
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02 LD (BC),A - RLC D - LEA BC,IX+d
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03 INC BC - RLC E - LEA BC,IY+d
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04 INC B - RLC H - TST A,B
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05 DEC B - RLC L - -
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06 LD B,&00 - RLC (HL) RLC (IY+d) -
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07 RLCA LD BC,(IX+d) RLC A - LD BC,(HL)
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08 EX AF,AF' - RRC B - IN0 C,(&00)
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09 ADD HL,BC ADD IX,BC RRC C - OUT0 (&00),C
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0A LD A,(BC) - RRC D - -
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0B DEC BC - RRC E - -
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0C INC C - RRC H - TST A,C
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0D DEC C - RRC L - -
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0E LD C,&00 - RRC (HL) RRC (IY+d) -
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0F RRCA LD (IX+d),BC RRC A - LD (HL),BC
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10 DJNZ dist - RL B - IN0 D,(&00)
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11 LD DE,&0000 - RL C - OUT0 (&00),D
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12 LD (DE),A - RL D - LEA DE,IX+d
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13 INC DE - RL E - LEA DE,IY+d
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14 INC D - RL H - TST A,D
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15 DEC D - RL L - -
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16 LD D,&00 - RL (HL) RL (IY+d) -
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17 RLA LD DE,(IX+d) RL A - LD DE,(HL)
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18 JR dist - RR B - IN0 E,(&00)
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19 ADD HL,DE ADD IX,DE RR C - OUT0 (&00),E
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1A LD A,(DE) - RR D - -
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1B DEC DE - RR E - -
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1C INC E - RR H - TST A,E
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1D DEC E - RR L - -
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1E LD E,&00 - RR (HL) RR (IY+d) -
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1F RRA LD (IX+d),DE RR A - LD (HL),DE
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20 JR NZ,dist - SLA B - IN0 H,(&00)
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21 LD HL,&0000 LD IX,&0000 SLA C - OUT0 (&00),H
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22 LD (&0000),HL LD (&0000),IX SLA D - LEA HL,IX+d
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23 INC HL INC IX SLA E - LEA HL,IY+d
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24 INC H INC IXH SLA H - TST A,H
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25 DEC H DEC IXH SLA L - -
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26 LD H,&00 LD IXH,&00 SLA (HL) SLA (IY+d) -
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27 DAA LD HL,(IX+d) SLA A - LD HL,(HL)
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28 JR Z,dist - SRA B - IN0 L,(&00)
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29 ADD HL,HL ADD IX,IX SRA C - OUT0 (&00),L
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2A LD HL,(&0000) LD IX,(&0000) SRA D - -
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2B DEC HL DEC IX SRA E - -
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2C INC L INC IXL SRA H - TST A,L
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2D DEC L DEC IXL SRA L - -
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2E LD L,&00 LD IXL,&00 SRA (HL) SRA (IY+d) -
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2F CPL LD (IX+d),HL SRA A - LD (HL),HL
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30 JR NC,dist - - - -
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31 LD SP,&0000 LD IY,(IX+d) - - -
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32 LD (&0000),A - - - LEA IX,IX+d
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33 INC SP - - - LEA IY,IY+d
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34 INC (HL) INC (IX+d) - - TST A,(HL)
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35 DEC (HL) DEC (IX+d) - - -
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36 LD (HL),&00 LD (IX+d),&00 - - LD IY,(HL)
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37 SCF LD IX,(IX+d) - - LD IX,(HL)
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38 JR C,dist - SRL B - IN0 A,(&00)
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39 ADD HL,SP ADD IX,SP SRL C - OUT0 (&00),A
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3A LD A,(&0000) - SRL D - -
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3B DEC SP - SRL E - -
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3C INC A - SRL H - TST A,A
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3D DEC A - SRL L - -
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3E LD A,&00 LD (IX+d),IY SRL (HL) SRL (IY+d) LD (HL),IY
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3F CCF LD (IX+d),IX SRL A - LD (HL),IX
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40 LD B,B - BIT 0,B - IN B,(BC)
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41 LD B,C - BIT 0,C - OUT (BC),B
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42 LD B,D - BIT 0,D - SBC HL,BC
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43 LD B,E - BIT 0,E - LD (&0000),BC
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44 LD B,H LD B,IXH BIT 0,H - NEG
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45 LD B,L LD B,IXL BIT 0,L - RETN
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46 LD B,(HL) LD B,(IX+d) BIT 0,(HL) BIT 0,(IY+d) IM 0
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47 LD B,A - BIT 0,A - LD I,A
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48 LD C,B - BIT 1,B - IN C,(BC)
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49 LD C,C - BIT 1,C - OUT (BC),C
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4A LD C,D - BIT 1,D - ADC HL,BC
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4B LD C,E - BIT 1,E - LD BC,(&0000)
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4C LD C,H LD C,IXH BIT 1,H - MULT BC
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4D LD C,L LD C,IXL BIT 1,L - RETI
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4E LD C,(HL) LD C,(IX+d) BIT 1,(HL) BIT 1,(IY+d) -
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4F LD C,A - BIT 1,A - LD R,A
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50 LD D,B - BIT 2,B - IN D,(BC)
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51 LD D,C - BIT 2,C - OUT (BC),D
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52 LD D,D - BIT 2,D - SBC HL,DE
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53 LD D,E - BIT 2,E - LD (&0000),DE
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54 LD D,H LD D,IXH BIT 2,H - LEA IX,IY+d
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55 LD D,L LD D,IXL BIT 2,L - LEA IY,IX+d
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56 LD D,(HL) LD D,(IX+d) BIT 2,(HL) BIT 2,(IY+d) IM 1
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57 LD D,A - BIT 2,A - LD A,I
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58 LD E,B - BIT 3,B - IN E,(BC)
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59 LD E,C - BIT 3,C - OUT (BC),E
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5A LD E,D - BIT 3,D - ADC HL,DE
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5B LD E,E - BIT 3,E - LD DE,(&0000)
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5C LD E,H LD E,IXH BIT 3,H - MULT DE
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5D LD E,L LD E,IXL BIT 3,L - -
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5E LD E,(HL) LD E,(IX+d) BIT 3,(HL) BIT 3,(IY+d) IM 2
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5F LD E,A - BIT 3,A - LD A,R
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60 LD H,B LD IXH,B BIT 4,B - IN H,(BC)
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61 LD H,C LD IXH,C BIT 4,C - OUT (BC),H
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62 LD H,D LD IXH,D BIT 4,D - SBC HL,HL
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63 LD H,E LD IXH,E BIT 4,E - LD (&0000),HL
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64 LD H,H LD IXH,IXH BIT 4,H - TST A,&00
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65 LD H,L LD IXH,IXL BIT 4,L - PEA IX+d
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66 LD H,(HL) LD H,(IX+d) BIT 4,(HL) BIT 4,(IY+d) PEA IY+d
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67 LD H,A LD IXH,A BIT 4,A - RRD
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68 LD L,B LD IXL,B BIT 5,B - IN L,(BC)
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69 LD L,C LD IXL,C BIT 5,C - OUT (BC),L
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6A LD L,D LD IXL,D BIT 5,D - ADC HL,HL
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6B LD L,E LD IXL,E BIT 5,E - LD HL,(&0000)
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6C LD L,H LD IXL,IXH BIT 5,H - MULT HL
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6D LD L,L LD IXL,IXL BIT 5,L - LD MB,A
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6E LD L,(HL) LD L,(IX+d) BIT 5,(HL) BIT 5,(IY+d) LD A,MB
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6F LD L,A LD IXL,A BIT 5,A - RLD
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70 LD (HL),B LD (IX+d),B BIT 6,B - -
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71 LD (HL),C LD (IX+d),C BIT 6,C - -
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72 LD (HL),D LD (IX+d),D BIT 6,D - SBC HL,SP
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73 LD (HL),E LD (IX+d),E BIT 6,E - LD (&0000),SP
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74 LD (HL),H LD (IX+d),H BIT 6,H - TSR (&00)
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75 LD (HL),L LD (IX+d),L BIT 6,L - -
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76 HALT - BIT 6,(HL) BIT 6,(IY+d) SLP
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77 LD (HL),A LD (IX+d),A BIT 6,A - -
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78 LD A,B - BIT 7,B - IN A,(BC)
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79 LD A,C - BIT 7,C - OUT (BC),A
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7A LD A,D - BIT 7,D - ADC HL,SP
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7B LD A,E - BIT 7,E - LD SP,(&0000)
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7C LD A,H LD A,IXH BIT 7,H - MULT SP
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7D LD A,L LD A,IXL BIT 7,L - STMIX
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7E LD A,(HL) LD A,(IX+d) BIT 7,(HL) BIT 7,(IY+d) RSMIX
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7F LD A,A - BIT 7,A - -
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80 ADD A,B - RES 0,B - -
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81 ADD A,C - RES 0,C - -
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82 ADD A,D - RES 0,D - INIM
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83 ADD A,E - RES 0,E - OTIM
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84 ADD A,H ADD A,IXH RES 0,H - INI2
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85 ADD A,L ADD A,IXL RES 0,L - -
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86 ADD A,(HL) ADD A,(IX+d) RES 0,(HL) RES 0,(IY+d) -
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87 ADD A,A - RES 0,A - -
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88 ADC A,B - RES 1,B - -
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89 ADC A,C - RES 1,C - -
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8A ADC A,D - RES 1,D - INDM
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8B ADC A,E - RES 1,E - OTDM
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8C ADC A,H ADC A,IXH RES 1,H - IND2
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8D ADC A,L ADC A,IXL RES 1,L - -
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8E ADC A,(HL) ADC A,(IX+d) RES 1,(HL) RES 1,(IY+d) -
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8F ADC A,A - RES 1,A - -
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90 SUB A,B - RES 2,B - -
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91 SUB A,C - RES 2,C - -
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92 SUB A,D - RES 2,D - INIMR
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93 SUB A,E - RES 2,E - OTIMR
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94 SUB A,H SUB A,IXH RES 2,H - INI2R
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95 SUB A,L SUB A,IXL RES 2,L - -
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96 SUB A,(HL) SUB A,(IX+d) RES 2,(HL) RES 2,(IY+d) -
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97 SUB A,A - RES 2,A - -
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98 SBC A,B - RES 3,B - -
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99 SBC A,C - RES 3,C - -
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9A SBC A,D - RES 3,D - INDMR
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9B SBC A,E - RES 3,E - OTDMR
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9C SBC A,H SBC A,IXH RES 3,H - IND2R
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9D SBC A,L SBC A,IXL RES 3,L - -
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9E SBC A,(HL) SBC A,(IX+d) RES 3,(HL) RES 3,(IY+d) -
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9F SBC A,A - RES 3,A - -
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A0 AND B - RES 4,B - LDI
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A1 AND C - RES 4,C - CPI
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A2 AND D - RES 4,D - INI
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A3 AND E - RES 4,E - OTI
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A4 AND H AND IXH RES 4,H - OTI2
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A5 AND L AND IXL RES 4,L - -
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A6 AND (HL) AND (IX+d) RES 4,(HL) RES 4,(IY+d) -
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A7 AND A - RES 4,A - -
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A8 XOR B - RES 5,B - LDD
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A9 XOR C - RES 5,C - CPD
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AA XOR D - RES 5,D - IND
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AB XOR E - RES 5,E - OTD
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AC XOR H XOR IXH RES 5,H - OTD2
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AD XOR L XOR IXL RES 5,L - -
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AE XOR (HL) XOR (IX+d) RES 5,(HL) RES 5,(IY+d) -
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AF XOR A - RES 5,A - -
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B0 OR B - RES 6,B - LDIR
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B1 OR C - RES 6,C - CPIR
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B2 OR D - RES 6,D - INIR
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B3 OR E - RES 6,E - OTIR
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B4 OR H OR IXH RES 6,H - ORI2R
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B5 OR L OR IXL RES 6,L - -
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B6 OR (HL) OR (IX+d) RES 6,(HL) RES 6,(IY+d) -
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B7 OR A - RES 6,A - -
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B8 CP B - RES 7,B - LDDR
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B9 CP C - RES 7,C - CPDR
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BA CP D - RES 7,D - INDR
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BB CP E - RES 7,E - OTDR
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BC CP H CP IXH RES 7,H - OTD2R
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BD CP L CP IXL RES 7,L - -
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BE CP (HL) CP (IX+d) RES 7,(HL) RES 7,(IY+d) -
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BF CP A - RES 7,A - -
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C0 RET NZ - SET 0,B - -
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C1 POP BC - SET 0,C - -
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C2 JP NZ,&0000 - SET 0,D - -
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C3 JP &0000 - SET 0,E - -
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C4 CALL NZ,&0000 - SET 0,H - -
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C5 PUSH BC - SET 0,L - -
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C6 ADD A,&00 - SET 0,(HL) SET 0,(IY+d) -
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C7 RST &00 - SET 0,A - -
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C8 RET Z - SET 1,B - -
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C9 RET - SET 1,C - -
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CA JP Z,&0000 - SET 1,D - -
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CB **** CB **** **** CB **** SET 1,E - -
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CC CALL Z,&0000 - SET 1,H - -
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CD CALL &0000 - SET 1,L - -
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CE ADC A,&00 - SET 1,(HL) SET 1,(IY+d) -
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CF RST &08 - SET 1,A - -
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D0 RET NC - SET 2,B - -
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D1 POP DE - SET 2,C - -
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D2 JP NC,&0000 - SET 2,D - -
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D3 OUT (&00),A - SET 2,E - -
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D4 CALL NC,&0000 - SET 2,H - -
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D5 PUSH DE - SET 2,L - -
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D6 SUB A,&00 - SET 2,(HL) SET 2,(IY+d) -
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D7 RST &10 - SET 2,A - -
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D8 RET C - SET 3,B - -
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D9 EXX - SET 3,C - -
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DA JP C,&0000 - SET 3,D - -
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DB IN A,(&00) - SET 3,E - -
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DC CALL C,&0000 - SET 3,H - -
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DD **** DD **** - SET 3,L - -
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DE SBC A,&00 - SET 3,(HL) SET 3,(IY+d) -
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DF RST &18 - SET 3,A - -
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E0 RET PO - SET 4,B - -
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E1 POP HL POP IX SET 4,C - -
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E2 JP PO,&0000 - SET 4,D - -
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E3 EX (SP),HL EX (SP),IX SET 4,E - -
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E4 CALL PO,&0000 - SET 4,H - -
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E5 PUSH HL PUSH IX SET 4,L - -
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E6 AND &00 - SET 4,(HL) SET 4,(IY+d) -
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E7 RST &20 - SET 4,A - -
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E8 RET PE - SET 5,B - -
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E9 JP (HL) JP (IX) SET 5,C - -
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EA JP PE,&0000 - SET 5,D - -
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EB EX DE,HL - SET 5,E - -
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EC CALL PE,&0000 - SET 5,H - -
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ED **** ED **** - SET 5,L - -
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EE XOR &00 - SET 5,(HL) SET 5,(IY+d) -
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EF RST &28 - SET 5,A - -
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F0 RET P - SET 6,B - -
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F1 POP AF - SET 6,C - -
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F2 JP P,&0000 - SET 6,D - -
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F3 DI - SET 6,E - -
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F4 CALL P,&0000 - SET 6,H - -
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F5 PUSH AF - SET 6,L - -
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F6 OR &00 - SET 6,(HL) SET 6,(IY+d) -
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F7 RST &30 - SET 6,A - -
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F8 RET M - SET 7,B - -
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F9 LD SP,HL LD SP,IX SET 7,C - -
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FA JP M,&0000 - SET 7,D - -
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FB EI - SET 7,E - -
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FC CALL M,&0000 - SET 7,H - -
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FD **** FD **** - SET 7,L - -
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FE CP &00 - SET 7,(HL) SET 7,(IY+d) -
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FF RST &38 - SET 7,A - -
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Notes on index registers
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------------------------
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Where DD and IX are mentioned, FD and IY may be substituted and vis versa.
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If a DD or FD opcode prefixes an nonexistant instruction, then the DD or
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FD opcode acts as a NOP and the base instruction is executed. For example,
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DD FF does a RST &38.
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Notes on Indexed Shift/Bit Operations
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-------------------------------------
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A shift or bit operation on an indexed byte in memory is done by prefixing a
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CB opcode refering to (HL) with DD or FD to specify (IX+n) or (IY+n). If
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the CB opcode does not refer to (HL), then the CB prefix is executed as a
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NOP and the following code executed.
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Notes on ED opcodes
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-------------------
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Opcodes 00 to 3F and C0 to FF (other than the block instructions) just
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increment the R register by 2.
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References
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