mirror of
https://github.com/larsbrinkhoff/awesome-cpus
synced 2025-10-31 08:16:02 +03:00
180 lines
8.3 KiB
Plaintext
180 lines
8.3 KiB
Plaintext
68000bin.txt
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Instruction set of the 68000 in binary order
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1988/wjvg
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0 2 3 4 5
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0000 0000zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk ori.z #kz,a
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0000 0010zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk andi.z #kz,a
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0000 0100zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk subi.z #kz,a
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0000 0110zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk addi.z #kz,a
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0000 1010zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk eori.z #kz,a
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0000 1100zz aaaaaa kkkkkkkk kkkkkkkk kifz==lk kifz==lk cmpi.z #kz,a
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0000 100000 aaaaaa 00000000 000nnnnn btst #n,a
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0000 100001 aaaaaa 00000000 000nnnnn bchg #n,a
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0000 100010 aaaaaa 00000000 000nnnnn bclr #n,a
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0000 100011 aaaaaa 00000000 000nnnnn bset #n,a
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0000 sss100 aaaaaa btst Ds,a
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0000 sss101 aaaaaa bchg Ds,a
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0000 sss110 aaaaaa bclr Ds,a
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0000 sss111 aaaaaa bset Ds,a
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0000 ddd10z 001sss dddddddd dddddddd movep.z d16(As),Dd
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0000 sss11z 001ddd dddddddd dddddddd movep.z Ds,d16(Ad)
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0001 dddddd ssssss (dddddd reversed) move.b as,ad
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0010 dddddd ssssss (dddddd reversed) move.l as,ad
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0011 dddddd ssssss (dddddd reversed) move.w as,ad
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0100 0000zz aaaaaa negx.z a
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0100 000011 aaaaaa move SR,a
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0100 0010zz aaaaaa clr.z a
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0100 0100zz aaaaaa neg.z a
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0100 010011 aaaaaa move a,CCR
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0100 0110zz aaaaaa not.z a
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0100 011011 aaaaaa move a,SR
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0100 100000 aaaaaa nbcd a
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0100 100001 000ddd swap.w Dd
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0100 100001 aaaaaa pea a
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0100 10001z 000ddd ext.z Dd
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0100 10001z aaaaaa a6543210 d6543210 movem.z reg-list,a
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0100 1010zz aaaaaa tst.z a
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0100 101011 aaaaaa tas.b a
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0100 11001z aaaaaa a6543210 d6543210 movem.z a,reg-list
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0100 111001 00vvvv trap #vector
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0100 111001 010sss dddddddd dddddddd link As,#k16
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0100 111001 011ddd unlk Ad
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0100 111001 100sss move As,USP
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0100 111001 101ddd move USP,Ad
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0100 111001 110000 reset
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0100 111001 110001 nop
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0100 111001 110010 kkkkkkkk kkkkkkkk stop #k16
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0100 111001 110011 rte
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0100 111001 110101 rts
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0100 111001 110110 trapv
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0100 111001 110111 rtr
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0100 111010 aaaaaa jsr a
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0100 111011 aaaaaa jmp a
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0100 ddd110 aaaaaa chk.w a,Dd
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0100 ddd111 aaaaaa lea a,Ad
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0101 cccc11 001sss llllllll llllllll db(cc) Ds,label
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0101 cccc11 aaaaaa stcc.b a
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0101 kkk0zz aaaaaa addq.z #k3,a
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0101 kkk1zz aaaaaa subq.z #k3,a
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0110 0000ll llllll if zero, a 16bit address follows bra label
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0110 0001ll llllll if zero, a 16bit address follows bsr label
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0110 ccccll llllll if zero, a 16bit address follows bcc label
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0111 ddd0kk kkkkkk moveq.l #k8,Dd
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1000 ddd0zz aaaaaa or.z a,Dd
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1000 ddd011 aaaaaa divu.w a,Dd
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1000 ddd100 000sss sbcd Ds,Dd
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1000 ddd100 001sss sbcd -(As),-(Ad)
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1000 sss1zz aaaaaa or.z Ds,a
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1000 ddd111 aaaaaa divs.w a,Dd
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1001 ddd0zz aaaaaa sub.z a,Dd
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1001 ddd1zz 000sss subx.z Ds,Dd
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1001 ddd1zz 001sss subx.z -(As),-(Ad)
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1001 sss1zz aaaaaa sub.z Ds,a
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1001 dddz11 aaaaaa suba.z a,Ad
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1011 ddd0zz aaaaaa cmp.z a,Dd
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1011 ddd1zz 000sss cmpm.z Ds,Dd
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1011 ddd1zz 001sss cmpm.z (As)+,(Ad)+
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1011 ddd1zz aaaaaa eor.z a,Dd
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1011 dddz11 aaaaaa cmpa.z a,Ad
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1100 ddd0zz aaaaaa and.z a,Dd
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1100 ddd011 aaaaaa mulu.w a,Dd
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1100 ddd100 000sss abcd Ds,Dd
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1100 ddd101 000sss exg.l Ds,Dd
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1100 ddd100 001sss abcd -(As),-(Ad)
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1100 ddd101 001sss exg.l As,Ad
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1100 ddd110 001sss exg.l As,Dd
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1100 sss1zz aaaaaa and.z Ds,a
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1100 ddd111 aaaaaa muls.w a,Dd
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1101 ddd0zz aaaaaa add.z a,Dd
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1101 ddd1zz 000sss addx.z Ds,Dd
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1101 ddd1zz 001sss addx.z -(As),-(Ad)
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1101 sss1zz aaaaaa add.z Ds,a
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1101 dddz11 aaaaaa adda.z a,Ad
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1110 kkk0zz 000ddd asrd.z #k,Dd
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1110 kkk0zz 001ddd lsrd.z #k,Dd
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1110 kkk0zz 010ddd roxrd.z #k,Dd
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1110 kkk0zz 011ddd rord.z #k,Dd
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1110 kkk1zz 000ddd asld.z #k,Dd
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1110 kkk1zz 001ddd lsld.z #k,Dd
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1110 kkk1zz 010ddd roxld.z #k,Dd
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1110 kkk1zz 011ddd rold.z #k,Dd
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1110 sss0zz 100ddd asrd.z Ds,Dd
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1110 sss0zz 101ddd lsrd.z Ds,Dd
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1110 sss0zz 110ddd roxrd.z Ds,Dd
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1110 sss0zz 111ddd rord.z Ds,Dd
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1110 sss1zz 100ddd asld.z Ds,Dd
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1110 sss1zz 101ddd lsld.z Ds,Dd
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1110 sss1zz 110ddd roxld.z Ds,Dd
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1110 sss1zz 111ddd rold.z Ds,Dd
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1110 000011 aaaaaa asrd.w #1,a
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1110 000111 aaaaaa asld.w #1,a
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1110 001011 aaaaaa lsrd.w #1,a
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1110 001111 aaaaaa lsld.w #1,a
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1110 010011 aaaaaa roxrd.w #1,a
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1110 010111 aaaaaa roxld.w #1,a
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1110 011011 aaaaaa rord.w #1,a
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1110 011111 aaaaaa rold.w #1,a
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general subfields
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zz 00=b, 01=w, 10=l
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z 0=w, 1=l
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kkk immediate data in addq etc.: 0==8
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immediate data in movq is sign extended to 32bits
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shift count also represents 1..8 (how?)
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addressing modes (aaaaaa):
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000 rrr Dr
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001 rrr Ar
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010 rrr (Ar)
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011 rrr (Ar)+
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100 rrr -(Ar)
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101 rrr d16(Ar) dddddddd dddddddd
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110 rrr d8(Ar,ix) aiiiz000 dddddddd
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111 000 addr16 dddddddd dddddddd
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111 001 addr32 dddddddd dddddddd ddddddddd dddddddd
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111 010 d16(PC) dddddddd dddddddd
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111 011 d8(PC,ix) aiiiz000 dddddddd
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111 100 imm/implied
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flags:
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0000 t allways or bra ipv btr
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0001 f never or bsr ipv bnv
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0010 hi
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0011 ls
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0100 cc
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0101 cs
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0110 ne
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0111 eq
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1000 vc
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1001 vs
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1010 pl
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1011 mi
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1100 ge
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1101 lt
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1110 gt
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1111 le
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*end
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