| .. | ||
| ip | ||
| Basys3_Master.xdc | ||
| gigatron_basys.tcl | ||
| gigatron_nexys.tcl | ||
| gigatron_tb.vhd | ||
| gigatron.vhd | ||
| Nexys-A7-100T-Master.xdc | ||
| README.md | ||
| ROMv5a.coe | ||
FPGA
I have a FPGA recreation of the gigatron here. I have currently tested it on Nexys A7 and Basys 3 but it should work on most anything if willing to change out the Vivado IP BRAM and Clocking Wizard for vendor specific or custom implementations. I will likely add a couple more boards if I find the time. This is my first version and not optimized yet but is already tiny (around 150 LUTs). The recreation while being cycle accurate I believe loses some of the beauty of the design, especially around the ALU. But it is a logical and functional recreation.
In order to build the project open vivado and execute these commands in the CLI window
cd /git/gigatron-rom/Contrib/fetchingcat/fpga
Then execute one of these depending on your board:
source gigatron_basys.tcl
source gigatron_nexys.tcl
I need to add the user input through the pluggy mc plugface adaptor and the audio still (the audio pins just go to LEDs at the moment).