51 lines
1.1 KiB
VHDL
51 lines
1.1 KiB
VHDL
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-- written by Robert Sanchez
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity gigatron_tb is
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end gigatron_tb;
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architecture Behavioral of gigatron_tb is
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component gigatron
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Port (
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sysclk : in std_logic;
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VGA_R : out std_logic_vector(3 downto 0);
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VGA_G : out std_logic_vector(3 downto 0);
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VGA_B : out std_logic_vector(3 downto 0);
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VGA_HS : out std_logic;
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VGA_VS : out std_logic;
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LED : out std_logic_vector(15 downto 0));
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end component;
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signal sysclk : std_logic := '0';
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signal LED : std_logic_vector(15 downto 0);
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signal VGA_R : std_logic_vector(3 downto 0);
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signal VGA_G : std_logic_vector(3 downto 0);
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signal VGA_B : std_logic_vector(3 downto 0);
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signal VGA_HS : std_logic;
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signal VGA_VS : std_logic;
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constant clk_period : time := 10 ns;
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begin
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uut: gigatron port map(sysclk, VGA_R, VGA_G, VGA_B, VGA_HS, VGA_VS, LED);
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clk_process: process
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begin
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wait for clk_period/2;
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sysclk <= '1';
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wait for clk_period/2;
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sysclk <= '0';
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end process;
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end Behavioral;
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