29 lines
1.8 KiB
Markdown
29 lines
1.8 KiB
Markdown
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### Simulator ###
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Here I have a simulated digital logic recreation of the gigatron based on the gigatron [schematics](https://cdn.hackaday.io/files/20781889094304/Schematics%202020-03-20.pdf)
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This simulation runs using [Hneemann's Digital Logic Simulator](https://github.com/hneemann/Digital).
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This project was used as a map for helping creating the FPGA version, though I found I mostly implemented it without being a chip for chip recreation.
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This project drew inspirations from monsonite's much more aesthetically pleasing version [here](https://github.com/monsonite/Gigatron-Simulator)
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I worked to try to be as accurate as possible and as such you could use this to help diagnose or just investigate the inner workerings closer.
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In order to get the VGA output to render correctly I needed to modify the Digital simulator by adding the VGA timings its using.
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I currently have a custom build deployed [here](https://github.com/fetchingcat/Digital/releases/tag/patched_release).
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Otherwise you can use the normal Digital found here but it will generate an error once it starts to try to render a VGA screen.
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The clocking works by having 4 clock steps for the VGA pixel clock and 1 step for the gigatron.
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This gives us the 4:1 ratio needed to simulate 25mhz and 6.25mhz.
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There is also a simple hardware breakpoint wired in to a comparator.
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Currently there is no user input mechanism, but it is something I am planning to add eventually.
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Please note that I don't really have a proper reset circuit at the moment so ensure the PC starts at 0x0000 before enabling cycles
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