RomanRom2/ossc
1
0
Fork 0
mirror of https://github.com/marqs85/ossc synced 2026-01-27 18:23:25 +03:00
Code Issues Actions Packages Projects Releases Wiki Activity

prevent potential alignment issues wrt. link & load

Browse Source
This commit is contained in:
marqs 2025-04-09 23:58:29 +03:00
parent e74da07802
commit 3abd3d7ec0
2 changed files with 7 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
software/sys_controller/Makefile
View File

@ -1140,8 +1140,8 @@ ossc/userdata_sjis.c: ossc/userdata.c
iconv -f UTF-8 -t SHIFT-JIS ossc/userdata.c > ossc/userdata_sjis.c iconv -f UTF-8 -t SHIFT-JIS ossc/userdata.c > ossc/userdata_sjis.c
mem_init/flash.hex: sys_controller.elf mem_init/flash.hex: sys_controller.elf
$(RV_OBJCOPY) --change-addresses -0x02A00000 -O binary --gap-fill 0 $< mem_init/flash.bin $(RV_OBJCOPY) --change-addresses -0x02080000 -O binary --gap-fill 0 $< mem_init/flash.bin
$(RV_OBJCOPY) --change-addresses -0x02A00000 -O ihex --gap-fill 0 $< mem_init/flash.hex $(RV_OBJCOPY) --change-addresses -0x02080000 -O ihex --gap-fill 0 $< mem_init/flash.hex
mkdir -p mem_init/chunks mkdir -p mem_init/chunks
rm -f mem_init/chunks/* rm -f mem_init/chunks/*
split -d -b 64 -a 4 mem_init/flash.bin mem_init/chunks/flash. split -d -b 64 -a 4 mem_init/flash.bin mem_init/chunks/flash.

8
software/sys_controller/link.common.ld
View File

@ -54,6 +54,7 @@ SECTIONS
*(.rodata.*) *(.rodata.*)
*(.srodata); *(.srodata);
*(.srodata.*) *(.srodata.*)
. = ALIGN(4);
} > flash_imem } > flash_imem
/*--------------------------------------------------------------------*/ /*--------------------------------------------------------------------*/
@ -84,18 +85,18 @@ SECTIONS
} > dataram } > dataram
.text_bram : AT ( LOADADDR (.rodata) + SIZEOF (.rodata) ) { .text_bram : AT ( LOADADDR (.rodata) + SIZEOF (.rodata) ) {
PROVIDE (__ram_text_start = ABSOLUTE(.));
. = ALIGN(4); . = ALIGN(4);
PROVIDE (__ram_text_start = ABSOLUTE(.));
*(.text_bram); *(.text_bram);
LONG(0) . = ALIGN(4);
PROVIDE (__ram_text_end = ABSOLUTE(.)); PROVIDE (__ram_text_end = ABSOLUTE(.));
} > dataram } > dataram
PROVIDE (__flash_text_bram_start = LOADADDR(.text_bram)); PROVIDE (__flash_text_bram_start = LOADADDR(.text_bram));
.data : AT ( LOADADDR (.text_bram) + SIZEOF (.text_bram) ) { .data : AT ( LOADADDR (.text_bram) + SIZEOF (.text_bram) ) {
PROVIDE (__ram_rwdata_start = ABSOLUTE(.));
. = ALIGN(4); . = ALIGN(4);
PROVIDE (__ram_rwdata_start = ABSOLUTE(.));
sdata = .; sdata = .;
_sdata = .; _sdata = .;
*(.data); *(.data);
@ -106,6 +107,7 @@ SECTIONS
*(.sdata2.*) *(.sdata2.*)
edata = .; edata = .;
_edata = .; _edata = .;
. = ALIGN(4);
PROVIDE (__ram_rwdata_end = ABSOLUTE(.)); PROVIDE (__ram_rwdata_end = ABSOLUTE(.));
} > dataram } > dataram