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first version booting from flash

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marqs 2025-03-26 23:30:42 +02:00
parent 429b0f7201
commit e74da07802
53 changed files with 5048 additions and 4961 deletions
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6
.gitmodules vendored
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@ -1,3 +1,3 @@
[submodule "ip/pulpino_qsys"]
path = ip/pulpino_qsys
url = https://github.com/marqs85/pulpino_qsys.git
[submodule "ip/ibex_qsys"]
path = ip/ibex_qsys
url = git@github.com:marqs85/ibex_qsys.git

1
ip/ibex_qsys Submodule

@ -0,0 +1 @@
Subproject commit 95fd422a056dcbb63f535c04f5eb5e54f78cd99d

1
ip/pulpino_qsys

@ -1 +0,0 @@
Subproject commit dfb0af0ed3b4e9e72e444eba2b1c149b5adad2cc

10
ossc.cof
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@ -10,9 +10,15 @@
<user_name>Page_0</user_name>
<page_flags>1</page_flags>
<bit0>
<sof_filename>output_files/ossc.sof<compress_bitstream>1</compress_bitstream></sof_filename>
<sof_filename>output_files/ossc.sof</sof_filename>
</bit0>
</sof_data>
<hex_block>
<hex_filename>software/sys_controller/mem_init/flash.hex</hex_filename>
<hex_addressing>relative</hex_addressing>
<hex_offset>524288</hex_offset>
<hex_little_endian>0</hex_little_endian>
</hex_block>
<version>10</version>
<create_cvp_file>0</create_cvp_file>
<create_hps_iocsr>0</create_hps_iocsr>
@ -22,7 +28,7 @@
<map_file>0</map_file>
</options>
<advanced_options>
<ignore_epcs_id_check>0</ignore_epcs_id_check>
<ignore_epcs_id_check>1</ignore_epcs_id_check>
<ignore_condone_check>2</ignore_condone_check>
<plc_adjustment>0</plc_adjustment>
<post_chain_bitstream_pad_bytes>-1</post_chain_bitstream_pad_bytes>

21
ossc.qsf
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@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP4CE15E22C8
set_global_assignment -name TOP_LEVEL_ENTITY ossc
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:27:03 MAY 17, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION "23.1std.1 Lite Edition"
set_global_assignment -name LAST_QUARTUS_VERSION "24.1std.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@ -172,9 +172,8 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name INI_VARS "FIOMGR_ENABLE_SPI_TIMING=ON"
set_global_assignment -name SEARCH_PATH rtl
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
@ -231,6 +230,12 @@ set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[7]
set_global_assignment -name VERILOG_FILE rtl/videogen.v
set_global_assignment -name VERILOG_FILE rtl/ir_rcv.v
set_global_assignment -name VERILOG_FILE rtl/ossc.v
@ -249,10 +254,8 @@ set_global_assignment -name SDC_FILE ossc.sdc
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp
set_global_assignment -name QIP_FILE rtl/char_array.qip
set_global_assignment -name SEARCH_PATH rtl
set_global_assignment -name SEARCH_PATH software/sys_controller/mem_init/
set_global_assignment -name SEARCH_PATH ip/ibex_qsys/rtl_extra
set_global_assignment -name VERILOG_MACRO "SYNTHESIS=<None>"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

4
rtl/char_array.qip
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@ -1,6 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "23.1"
set_global_assignment -name IP_TOOL_VERSION "24.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_array.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_array_inst.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_array_bb.v"]

22
rtl/char_array.v
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@ -14,24 +14,24 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 23.1std.1 Build 993 05/14/2024 SC Lite Edition
// 24.1std.0 Build 1077 03/04/2025 SC Lite Edition
// ************************************************************
//Copyright (C) 2024 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//Copyright (C) 2025 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
//Altera and sold by Altera or its authorized distributors. Please
//refer to the Altera Software License Subscription Agreements
//on the Quartus Prime software download page.
// synopsys translate_off
@ -218,6 +218,6 @@ endmodule
// Retrieval info: GEN_FILE: TYPE_NORMAL char_array.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL char_array.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL char_array.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL char_array_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL char_array_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL char_array_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL char_array_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

4
rtl/char_rom.qip
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@ -1,6 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "23.1"
set_global_assignment -name IP_TOOL_VERSION "24.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "char_rom.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_rom_inst.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "char_rom_bb.v"]

22
rtl/char_rom.v
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@ -14,24 +14,24 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 23.1std.1 Build 993 05/14/2024 SC Lite Edition
// 24.1std.0 Build 1077 03/04/2025 SC Lite Edition
// ************************************************************
//Copyright (C) 2024 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//Copyright (C) 2025 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
//Altera and sold by Altera or its authorized distributors. Please
//refer to the Altera Software License Subscription Agreements
//on the Quartus Prime software download page.
// synopsys translate_off
@ -160,6 +160,6 @@ endmodule
// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL char_rom_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

2
rtl/linebuf.qip
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@ -1,4 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "23.1"
set_global_assignment -name IP_TOOL_VERSION "24.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "linebuf.v"]

18
rtl/linebuf.v
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@ -14,24 +14,24 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 23.1std.1 Build 993 05/14/2024 SC Lite Edition
// 24.1std.0 Build 1077 03/04/2025 SC Lite Edition
// ************************************************************
//Copyright (C) 2024 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//Copyright (C) 2025 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
//Altera and sold by Altera or its authorized distributors. Please
//refer to the Altera Software License Subscription Agreements
//on the Quartus Prime software download page.
// synopsys translate_off

2
rtl/lpm_mult_8x5_9.qip
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@ -1,4 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
set_global_assignment -name IP_TOOL_VERSION "23.1"
set_global_assignment -name IP_TOOL_VERSION "24.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_8x5_9.v"]

18
rtl/lpm_mult_8x5_9.v
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@ -14,24 +14,24 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 23.1std.1 Build 993 05/14/2024 SC Lite Edition
// 24.1std.0 Build 1077 03/04/2025 SC Lite Edition
// ************************************************************
//Copyright (C) 2024 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//Copyright (C) 2025 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
//Altera and sold by Altera or its authorized distributors. Please
//refer to the Altera Software License Subscription Agreements
//on the Quartus Prime software download page.
// synopsys translate_off

2
rtl/lpm_mult_sl.qip
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@ -1,4 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
set_global_assignment -name IP_TOOL_VERSION "23.1"
set_global_assignment -name IP_TOOL_VERSION "24.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "lpm_mult_sl.v"]

18
rtl/lpm_mult_sl.v
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@ -14,24 +14,24 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 23.1std.1 Build 993 05/14/2024 SC Lite Edition
// 24.1std.0 Build 1077 03/04/2025 SC Lite Edition
// ************************************************************
//Copyright (C) 2024 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//Copyright (C) 2025 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
//Altera and sold by Altera or its authorized distributors. Please
//refer to the Altera Software License Subscription Agreements
//on the Quartus Prime software download page.
// synopsys translate_off

11
rtl/ossc.v
View File

@ -365,10 +365,8 @@ defparam
sys sys_inst(
.clk_clk (clk27),
.reset_reset_n (sys_reset_n),
.pulpino_0_config_testmode_i (1'b0),
.pulpino_0_config_fetch_enable_i (1'b1),
.pulpino_0_config_clock_gating_i (1'b0),
.pulpino_0_config_boot_addr_i (32'h00010000),
.ibex_0_config_boot_addr_i (32'h02080000),
.ibex_0_config_core_sleep_o (),
.master_0_master_reset_reset (jtagm_reset_req),
.i2c_opencores_0_export_scl_pad_io (scl),
.i2c_opencores_0_export_sda_pad_io (sda),
@ -408,10 +406,7 @@ sys sys_inst(
// These do not work in current Quartus version (23.1) and a patch file (scripts/qsys.patch) must be used after Qsys generation instead
defparam
sys_inst.epcq_controller2_0.asmi2_inst_epcq_ctrl.xip_controller.avst_fifo_inst.USE_MEMORY_BLOCKS = 0,
sys_inst.epcq_controller2_0.asmi2_inst_epcq_ctrl.xip_controller.avst_fifo_inst.avst_fifo.USE_MEMORY_BLOCKS = 0,
sys_inst.master_0.fifo.USE_MEMORY_BLOCKS = 0,
sys_inst.onchip_memory2_0.the_altsyncram.MAXIMUM_DEPTH = 2048;
sys_inst.master_0.fifo.USE_MEMORY_BLOCKS = 0;
scanconverter #(
.EMIF_ENABLE(0),

2
rtl/pll_2x.qip
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@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "23.1"
set_global_assignment -name IP_TOOL_VERSION "24.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_2x.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x.ppf"]

21
rtl/pll_2x.v
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@ -9,29 +9,29 @@
// altpll
//
// Simulation Library Files(s):
//
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 23.1std.1 Build 993 05/14/2024 SC Lite Edition
// 24.1std.0 Build 1077 03/04/2025 SC Lite Edition
// ************************************************************
//Copyright (C) 2024 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//Copyright (C) 2025 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
//Altera and sold by Altera or its authorized distributors. Please
//refer to the Altera Software License Subscription Agreements
//on the Quartus Prime software download page.
// synopsys translate_off
@ -377,4 +377,5 @@ endmodule
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.mif TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_2x.hex TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

17
rtl/tvp7002_frontend.v
View File

@ -167,7 +167,7 @@ wire [7:0] lumacode_data_3s_G = lumacode_data_3s[{lc_code[1], lc_code[2], lc_cod
wire [7:0] lumacode_data_3s_B = lumacode_data_3s[{lc_code[1], lc_code[2], lc_code[3]}][7:0];
// Lumacode palette Atari GTIA
wire [23:0] lumacode_data_gtia[0:255] = '{
/*wire [23:0] lumacode_data_gtia[0:255] = '{
24'h000000, 24'h111111, 24'h222222, 24'h333333, 24'h444444, 24'h555555, 24'h666666, 24'h777777, 24'h888888, 24'h999999, 24'haaaaaa, 24'hbbbbbb, 24'hcccccc, 24'hdddddd, 24'heeeeee, 24'hffffff,
24'h091900, 24'h192806, 24'h29370d, 24'h3a4714, 24'h4a561b, 24'h5a6522, 24'h6b7529, 24'h7b8430, 24'h8c9336, 24'h9ca33d, 24'hacb244, 24'hbdc14b, 24'hcdd152, 24'hdee059, 24'heeef60, 24'hffff67,
24'h300000, 24'h3d1108, 24'h4b2211, 24'h593319, 24'h674422, 24'h75552a, 24'h826633, 24'h90773b, 24'h9e8844, 24'hac994c, 24'hbaaa55, 24'hc7bb5d, 24'hd5cc66, 24'he3dd6e, 24'hf1ee77, 24'hffff80,
@ -183,10 +183,10 @@ wire [23:0] lumacode_data_gtia[0:255] = '{
24'h003400, 24'h0c410a, 24'h194f14, 24'h265c1e, 24'h336a28, 24'h407732, 24'h4c853c, 24'h599246, 24'h66a050, 24'h73ad5a, 24'h80bb64, 24'h8cc86e, 24'h99d678, 24'ha6e382, 24'hb3f18c, 24'hc0ff97,
24'h002a00, 24'h0f3807, 24'h1e460e, 24'h2d5416, 24'h3c621d, 24'h4b7124, 24'h5a7f2c, 24'h698d33, 24'h799b3b, 24'h88a942, 24'h97b849, 24'ha6c651, 24'hb5d458, 24'hc4e260, 24'hd3f067, 24'he3ff6f,
24'h0d1700, 24'h1d2606, 24'h2d350d, 24'h3d4514, 24'h4d541b, 24'h5d6422, 24'h6d7329, 24'h7d8330, 24'h8e9237, 24'h9ea23e, 24'haeb145, 24'hbec14c, 24'hced053, 24'hdee05a, 24'heeef61, 24'hffff68,
24'h330000, 24'h401008, 24'h4e2111, 24'h5b321a, 24'h694323, 24'h77542c, 24'h846535, 24'h92763e, 24'h9f8646, 24'had974f, 24'hbba858, 24'hc8b961, 24'hd6ca6a, 24'he3db73, 24'hf1ec7c, 24'hfffd85};
24'h330000, 24'h401008, 24'h4e2111, 24'h5b321a, 24'h694323, 24'h77542c, 24'h846535, 24'h92763e, 24'h9f8646, 24'had974f, 24'hbba858, 24'hc8b961, 24'hd6ca6a, 24'he3db73, 24'hf1ec7c, 24'hfffd85};*/
// Lumacode palette Atari CTIA/TIA
wire [23:0] lumacode_data_ctia[0:127] = '{
/*wire [23:0] lumacode_data_ctia[0:127] = '{
24'h000000, 24'h404040, 24'h6C6C6C, 24'h909090, 24'hB0B0B0, 24'hC8C8C8, 24'hDCDCDC, 24'hECECEC,
24'h444400, 24'h646410, 24'h848424, 24'hA0A034, 24'hB8B840, 24'hD0D050, 24'hE8E85C, 24'hFCFC68,
24'h702800, 24'h844414, 24'h985C28, 24'hAC783C, 24'hBC8C4C, 24'hCCA05C, 24'hDCB468, 24'hECC878,
@ -202,7 +202,7 @@ wire [23:0] lumacode_data_ctia[0:127] = '{
24'h003C00, 24'h205C20, 24'h407C40, 24'h5C9C5C, 24'h74B474, 24'h8CD08C, 24'hA4E4A4, 24'hB8FCB8,
24'h143800, 24'h345C1C, 24'h507C38, 24'h6C9850, 24'h84B468, 24'h9CCC7C, 24'hB4E490, 24'hC8FCA4,
24'h2C3000, 24'h4C501C, 24'h687034, 24'h848C4C, 24'h9CA864, 24'hB4C078, 24'hCCD488, 24'hE0EC9C,
24'h442800, 24'h644818, 24'h846830, 24'hA08444, 24'hB89C58, 24'hD0B46C, 24'hE8CC7C, 24'hFCE08C};
24'h442800, 24'h644818, 24'h846830, 24'hA08444, 24'hB89C58, 24'hD0B46C, 24'hE8CC7C, 24'hFCE08C};*/
// SOF position for scaler
wire [10:0] V_SOF_LINE = hv_in_config3[23:13];
@ -350,11 +350,13 @@ always @(posedge PCLK_i) begin
// Store hue and luma (high bits) for 1st pixel, and display last pixel of previous pair
lc_atari_hue <= {lc_code[1], lc_code[2]};
lc_atari_luma[3:2] <= lc_code[3];
{R_pp[2], G_pp[2], B_pp[2]} <= lumacode_data_gtia[{lc_atari_hue, lc_atari_luma}];
//{R_pp[2], G_pp[2], B_pp[2]} <= lumacode_data_gtia[{lc_atari_hue, lc_atari_luma}];
{R_pp[2], G_pp[2], B_pp[2]} <= '0;
end else begin
// Store luma for 2nd pixel, and display first pixel of current pair
lc_atari_luma <= {lc_code[2], lc_code[3]};
{R_pp[2], G_pp[2], B_pp[2]} <= lumacode_data_gtia[{lc_atari_hue, lc_atari_luma[3:2], lc_code[1]}];
//{R_pp[2], G_pp[2], B_pp[2]} <= lumacode_data_gtia[{lc_atari_hue, lc_atari_luma[3:2], lc_code[1]}];
{R_pp[2], G_pp[2], B_pp[2]} <= '0;
end
end
// Lumacode Atari VCS
@ -365,7 +367,8 @@ always @(posedge PCLK_i) begin
lc_atari_hue <= {lc_code[1], lc_code[2]};
end else begin
// Display pixel after receiving remaining 2 lumacode samples (luma)
{R_pp[2], G_pp[2], B_pp[2]} <= lumacode_data_ctia[{lc_atari_hue, lc_code[1], lc_code[2][1]}];
//{R_pp[2], G_pp[2], B_pp[2]} <= lumacode_data_ctia[{lc_atari_hue, lc_code[1], lc_code[2][1]}];
{R_pp[2], G_pp[2], B_pp[2]} <= '0;
end
end
end

58
scripts/dump_flash_regs.tcl Normal file
View File

@ -0,0 +1,58 @@
# flash details
set flash_base 0x02000000
set flash_imem_offset 0x00100000
set flash_imem_base [format 0x%.8x [expr $flash_base + $flash_imem_offset]]
set flash_secsize 65536
# flash controller register addresses
set control_register 0x00020100
set operating_protocols_setting 0x00020110
set read_instr 0x00020114
set write_instr 0x00020118
set flash_cmd_setting 0x0002011c
set flash_cmd_ctrl 0x00020120
set flash_cmd_addr_register 0x00020124
set flash_cmd_write_data_0 0x00020128
set flash_cmd_read_data_0 0x00020130
#Select the master service type and check for available service paths.
set service_paths [get_service_paths master]
#Set the master service path.
set master_service_path [lindex $service_paths 0]
#Open the master service.
set claim_path [claim_service master $master_service_path mylib]
puts "Halting CPU"
master_write_32 $claim_path 0x40 0x00000001
master_write_32 $claim_path 0x40 0x80000001
#read status reg
master_write_32 $claim_path $flash_cmd_setting 0x00001805
master_write_32 $claim_path $flash_cmd_ctrl 0x1
set st [master_read_8 $claim_path $flash_cmd_read_data_0 1]
puts "\nSTATUS: $st"
#read flag reg
master_write_32 $claim_path $flash_cmd_setting 0x00001848
master_write_32 $claim_path $flash_cmd_ctrl 0x1
set flags [master_read_8 $claim_path $flash_cmd_read_data_0 1]
puts "FLAGS: $flags"
#read vcr reg
master_write_32 $claim_path $flash_cmd_setting 0x00001861
master_write_32 $claim_path $flash_cmd_ctrl 0x1
set vcr [master_read_8 $claim_path $flash_cmd_read_data_0 1]
puts "VCR: $vcr"
#read evcr reg
master_write_32 $claim_path $flash_cmd_setting 0x00001881
master_write_32 $claim_path $flash_cmd_ctrl 0x1
set evcr [master_read_8 $claim_path $flash_cmd_read_data_0 1]
puts "EVCR: $evcr"
#clear flag register
master_write_32 $claim_path $flash_cmd_setting 0x00000050
master_write_32 $claim_path $flash_cmd_ctrl 0x1

35
scripts/qsys.patch
View File

@ -1,35 +0,0 @@
--- sys/synthesis/submodules/altera_asmi2_xip_controller.sv 2024-07-15 02:34:49.476724296 +0300
+++ sys/synthesis/submodules/altera_asmi2_xip_controller.sv 2024-07-15 02:50:24.750038794 +0300
@@ -611,7 +611,7 @@
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
- .USE_MEMORY_BLOCKS (1),
+ .USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
--- sys/synthesis/submodules/sys_master_0.v 2024-07-15 02:34:47.396703537 +0300
+++ sys/synthesis/submodules/sys_master_0.v 2024-07-15 02:50:14.617938092 +0300
@@ -163,7 +163,7 @@
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
- .USE_MEMORY_BLOCKS (1),
+ .USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
--- sys/synthesis/submodules/sys_onchip_memory2_0.v 2024-07-15 02:34:47.540704974 +0300
+++ sys/synthesis/submodules/sys_onchip_memory2_0.v 2024-07-15 02:49:59.685789671 +0300
@@ -71,7 +71,7 @@
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
- the_altsyncram.maximum_depth = 10496,
+ the_altsyncram.maximum_depth = 2048,
the_altsyncram.numwords_a = 10496,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",

1
scripts/reprogram.sh
View File

@ -1,6 +1,5 @@
#!/bin/sh
jtagconfig
make rv-reprogram
if [ $# -eq 1 ] && [ $1 = "jtag_uart" ] && [ $(pgrep -c nios2-terminal) = 0 ]; then

36
scripts/rv-bt.tcl Normal file
View File

@ -0,0 +1,36 @@
#Select the master service type and check for available service paths.
while 1 {
set service_paths [get_service_paths master]
if {[llength $service_paths] > 0} {
break
}
puts "Refreshing connections..."
refresh_connections
after 100
}
#Set the master service path.
set master_service_path [lindex $service_paths 0]
#Open the master service.
set claim_path [claim_service master $master_service_path mylib]
puts "Halting CPU"
master_write_32 $claim_path 0x40 0x00000001
master_write_32 $claim_path 0x40 0x80000001
master_write_32 $claim_path 0x5c [expr 0x2207b1]
puts "DPC: [master_read_32 $claim_path 0x10 1]"
master_write_32 $claim_path 0x5c [expr 0x220341]
puts "MEPC: [master_read_32 $claim_path 0x10 1]"
master_write_32 $claim_path 0x5c [expr 0x220342]
puts "MCAUSE: [master_read_32 $claim_path 0x10 1]"
set offset 0x1001
foreach i {ra sp gp tp t0 t1 t2 s0 s1 a0 a1 a2 a3 a4 a5} {
master_write_32 $claim_path 0x5c [expr 0x220000 + $offset]
puts "$i: [master_read_32 $claim_path 0x10 1]"
set offset [expr $offset + 1]
}
master_write_32 $claim_path 0x40 0x40000000

31
scripts/rv-reboot.tcl Normal file
View File

@ -0,0 +1,31 @@
#Select the master service type and check for available service paths.
while 1 {
set service_paths [get_service_paths master]
if {[llength $service_paths] > 0} {
break
}
puts "Refreshing connections..."
refresh_connections
after 100
}
#Set the master service path.
set master_service_path [lindex $service_paths 0]
#Open the master service.
set claim_path [claim_service master $master_service_path mylib]
puts "Halting CPU"
master_write_32 $claim_path 0x40 0x00000001
master_write_32 $claim_path 0x40 0x80000001
close_service master $claim_path
set jtag_debug_list [get_service_paths jtag_debug]
set jd [ lindex $jtag_debug_list 0 ]
open_service jtag_debug $jd
puts "Resetting system"
jtag_debug_reset_system $jd
close_service jtag_debug $jd
puts "Done"

64
scripts/rv-reprogram.tcl
View File

@ -1,3 +1,25 @@
# flash details
set flash_base 0x02000000
set flash_imem_offset 0x00080000
set flash_imem_base [format 0x%.8x [expr $flash_base + $flash_imem_offset]]
set flash_secsize 65536
# flash controller register addresses
set control_register 0x00020100
set operating_protocols_setting 0x00020110
set read_instr 0x00020114
set write_instr 0x00020118
set flash_cmd_setting 0x0002011c
set flash_cmd_ctrl 0x00020120
set flash_cmd_addr_register 0x00020124
set flash_cmd_write_data_0 0x00020128
set flash_cmd_read_data_0 0x00020130
# target file details
set bin_file mem_init/flash.bin
set bin_size [file size $bin_file]
set num_sectors [expr ($bin_size / $flash_secsize) + (($bin_size % $flash_secsize) ne 0)]
#Select the master service type and check for available service paths.
while 1 {
set service_paths [get_service_paths master]
@ -16,10 +38,46 @@ set master_service_path [lindex $service_paths 0]
set claim_path [claim_service master $master_service_path mylib]
puts "Halting CPU"
master_write_32 $claim_path 0x0 0x10000
master_write_32 $claim_path 0x40 0x00000001
master_write_32 $claim_path 0x40 0x80000001
puts "Writing block RAM"
master_write_from_file $claim_path mem_init/sys_onchip_memory2_0.bin 0x10000
#write enable
master_write_32 $claim_path $flash_cmd_setting 0x00000006
master_write_32 $claim_path $flash_cmd_ctrl 0x1
#write status register (clear BP)
master_write_32 $claim_path $flash_cmd_setting 0x00001001
#master_write_32 $claim_path $flash_cmd_write_data_0 0x0000005c
master_write_32 $claim_path $flash_cmd_write_data_0 0x00000000
master_write_32 $claim_path $flash_cmd_ctrl 0x1
puts "Erasing $num_sectors flash sectors"
set addr $flash_imem_offset
for {set i 0} {$i<$num_sectors} {incr i} {
master_write_32 $claim_path $flash_cmd_setting 0x00000006
master_write_32 $claim_path $flash_cmd_ctrl 0x1
master_write_32 $claim_path $flash_cmd_setting 0x000003D8
master_write_32 $claim_path $flash_cmd_addr_register $addr
master_write_32 $claim_path $flash_cmd_ctrl 0x1
set addr [expr $addr + $flash_secsize]
after 500
}
puts "Writing flash"
# writes garbage and occasionally hangs (bug in generic serial flash IF?)
#master_write_from_file $claim_path mem_init/flash.bin $flash_imem_base
# work around the issue by writing into small chunks so that FIFO does not fill up
set chunks [llength [glob mem_init/chunks/*]]
puts "Programming $chunks chunks"
set addr $flash_imem_base
for {set i 0} {$i<$chunks} {incr i} {
set file [format "flash.%04d" $i]
master_write_from_file $claim_path mem_init/chunks/$file $addr
set addr [expr $addr + 64]
}
#master_read_to_file $claim_path mem_init/flash_readback.bin $flash_imem_base $bin_size
#master_read_to_file $claim_path mem_init/ram_readback.bin 0x010000 65536
close_service master $claim_path

4
software/ossc_sw.project
View File

@ -142,7 +142,7 @@
<Target Name="Ack BSP update">cd ../sys_controller_bsp &amp;&amp; touch bsp_timestamp</Target>
<RebuildCommand/>
<CleanCommand>make clean</CleanCommand>
<BuildCommand>make ENABLE_AUDIO=y APP_CFLAGS_DEBUG_LEVEL="-DDEBUG" generate_hex</BuildCommand>
<BuildCommand>make ENABLE_AUDIO=y APP_CFLAGS_DEBUG_LEVEL="-DDEBUG"</BuildCommand>
<PreprocessFileCommand/>
<SingleFileCommand/>
<MakefileGenerationCommand/>
@ -188,7 +188,7 @@
<Target Name="Ack BSP update">cd ../sys_controller_bsp &amp;&amp; touch bsp_timestamp</Target>
<RebuildCommand/>
<CleanCommand>make clean</CleanCommand>
<BuildCommand>make ENABLE_AUDIO=y generate_hex</BuildCommand>
<BuildCommand>make ENABLE_AUDIO=y</BuildCommand>
<PreprocessFileCommand/>
<SingleFileCommand/>
<MakefileGenerationCommand/>

26
software/sys_controller/Makefile
View File

@ -258,7 +258,7 @@ endif
all:
@$(ECHO) [$(APP_NAME) build complete]
all : build_pre_process libs app build_post_process
all : build_pre_process libs app mem_init_generate_new build_post_process
#------------------------------------------------------------------------------
@ -1139,16 +1139,28 @@ ossc/menu_sjis.c: ossc/menu.c
ossc/userdata_sjis.c: ossc/userdata.c
iconv -f UTF-8 -t SHIFT-JIS ossc/userdata.c > ossc/userdata_sjis.c
mem_init/sys_onchip_memory2_0.hex: sys_controller.elf
$(RV_OBJCOPY) --change-addresses -0x10000 -O binary --gap-fill 0 $< mem_init/sys_onchip_memory2_0.bin
../../tools/bin2hex 4 mem_init/sys_onchip_memory2_0.bin mem_init/sys_onchip_memory2_0.hex
mem_init/flash.hex: sys_controller.elf
$(RV_OBJCOPY) --change-addresses -0x02A00000 -O binary --gap-fill 0 $< mem_init/flash.bin
$(RV_OBJCOPY) --change-addresses -0x02A00000 -O ihex --gap-fill 0 $< mem_init/flash.hex
mkdir -p mem_init/chunks
rm -f mem_init/chunks/*
split -d -b 64 -a 4 mem_init/flash.bin mem_init/chunks/flash.
.PHONY: mem_init_generate_new
mem_init_generate_new: mem_init/sys_onchip_memory2_0.hex
mem_init_generate_new: mem_init/flash.hex
.PHONY: generate_hex
generate_hex: clean mem_init_generate_new
.PHONY: regenerate_hex
regenerate_hex: clean mem_init_generate_new
.PHONY: rv-reprogram
rv-reprogram: mem_init_generate_new
jtagconfig
system-console -cli --script ../../scripts/rv-reprogram.tcl
rv-bt:
jtagconfig
system-console -cli --script ../../scripts/rv-bt.tcl
rv-reboot:
jtagconfig
system-console -cli --script ../../scripts/rv-reboot.tcl

8
software/sys_controller/crt0.boot.S
View File

@ -71,6 +71,14 @@ zero_loop:
ble x26, x27, zero_loop
zero_loop_end:
copy_sections:
jal alt_load
cache_setup:
fence.i
csrwi 0x7C0, 1
cache_setup_end:
main_entry:
/* jump to alt_main program entry point */

9
software/sys_controller/crt0.boot_E.S
View File

@ -55,6 +55,15 @@ zero_loop:
ble x14, x15, zero_loop
zero_loop_end:
copy_sections:
jal alt_load
copy_sections_end:
cache_setup:
fence.i
csrwi 0x7C0, 1
cache_setup_end:
main_entry:
/* jump to alt_main program entry point */

48
software/sys_controller/link.common.ld
View File

@ -1,13 +1,19 @@
SEARCH_DIR(.)
__DYNAMIC = 0;
/* First 16 flash sectors reserved for firmware image (1MB).
In typical configuration a firmware image consists of
* compressed bitstream (8 sectors / 0.5MB)
* flash_imem (8 sectors / 0.5MB)
Last 16 flash sectors reserved for userdata (16x 64KB). */
MEMORY
{
dataram : ORIGIN = 0x00010000, LENGTH = 0xa400
flash_imem : ORIGIN = 0x02080000, LENGTH = 524288
dataram : ORIGIN = 0x00010000, LENGTH = 16384
}
/* Stack information variables */
_min_stack = 0x4B0; /* 1200 - minimum stack space to reserve */
_min_stack = 0x1000; /* 4KB - minimum stack space to reserve */
_stack_start = ORIGIN(dataram) + LENGTH(dataram);
/* We have to align each sector to word boundaries as our current s19->slm
@ -19,7 +25,7 @@ SECTIONS
{
. = ALIGN(4);
KEEP(*(.vectors))
} > dataram
} > flash_imem
.text : {
. = ALIGN(4);
@ -40,7 +46,15 @@ SECTIONS
*(.lit)
*(.shdata)
_endtext = .;
} > dataram
} > flash_imem
.rodata : {
. = ALIGN(4);
*(.rodata);
*(.rodata.*)
*(.srodata);
*(.srodata.*)
} > flash_imem
/*--------------------------------------------------------------------*/
/* Global constructor/destructor segement */
@ -69,19 +83,18 @@ SECTIONS
PROVIDE_HIDDEN (__fini_array_end = .);
} > dataram
.rodata : {
.text_bram : AT ( LOADADDR (.rodata) + SIZEOF (.rodata) ) {
PROVIDE (__ram_text_start = ABSOLUTE(.));
. = ALIGN(4);
*(.rodata);
*(.rodata.*)
*(.text_bram);
LONG(0)
PROVIDE (__ram_text_end = ABSOLUTE(.));
} > dataram
.shbss :
{
. = ALIGN(4);
*(.shbss)
} > dataram
PROVIDE (__flash_text_bram_start = LOADADDR(.text_bram));
.data : {
.data : AT ( LOADADDR (.text_bram) + SIZEOF (.text_bram) ) {
PROVIDE (__ram_rwdata_start = ABSOLUTE(.));
. = ALIGN(4);
sdata = .;
_sdata = .;
@ -93,6 +106,15 @@ SECTIONS
*(.sdata2.*)
edata = .;
_edata = .;
PROVIDE (__ram_rwdata_end = ABSOLUTE(.));
} > dataram
PROVIDE (__flash_rwdata_start = LOADADDR(.data));
.shbss :
{
. = ALIGN(4);
*(.shbss)
} > dataram
.bss :

78
software/sys_controller/memory/flash.c
View File

@ -18,52 +18,46 @@
//
#include <unistd.h>
#include <string.h>
#include "system.h"
#include "flash.h"
#include "utils.h"
// save some code space
#define SINGLE_FLASH_INSTANCE
void __attribute__((noinline, flatten, __section__(".text_bram"))) flash_write_protect(flash_ctrl_dev *dev, int enable) {
// Write enable
dev->regs->flash_cmd_cfg = 0x00000006;
dev->regs->flash_cmd_ctrl = 1;
alt_flash_dev *epcq_dev;
// Write status register
dev->regs->flash_cmd_cfg = 0x00001001;
dev->regs->flash_cmd_wrdata[0] = enable ? 0x0000005c : 0x00000000;
dev->regs->flash_cmd_ctrl = 1;
int init_flash()
{
#ifdef SINGLE_FLASH_INSTANCE
extern alt_llist alt_flash_dev_list;
epcq_dev = (alt_flash_dev*)alt_flash_dev_list.next;
#else
epcq_dev = alt_flash_open_dev(EPCQ_CONTROLLER2_0_AVL_MEM_NAME);
#endif
if (epcq_dev == NULL)
return -1;
return 0;
}
int verify_flash(alt_u32 offset, alt_u32 length, alt_u32 golden_crc, alt_u8 *tmpbuf)
{
alt_u32 crcval=0, i, j, bytes_to_read;
int retval;
for (i=0; i<length; i=i+PAGESIZE) {
bytes_to_read = ((length-i < PAGESIZE) ? (length-i) : PAGESIZE);
//retval = read_flash(i, bytes_to_read, tmpbuf);
retval = alt_epcq_controller2_read(epcq_dev, offset+i, tmpbuf, bytes_to_read);
for (j=0; j<bytes_to_read; j++)
tmpbuf[j] = bitswap8(tmpbuf[j]);
if (retval != 0)
return retval;
crcval = crc32(tmpbuf, bytes_to_read, (i==0));
// Poll status register until write has completed
while (1) {
dev->regs->flash_cmd_cfg = 0x00001805;
dev->regs->flash_cmd_ctrl = 1;
if (!(dev->regs->flash_cmd_rddata[0] & (1<<0)))
break;
}
if (crcval != golden_crc)
return -FLASH_VERIFY_ERROR;
return 0;
// Write disable
dev->regs->flash_cmd_cfg = 0x00000004;
dev->regs->flash_cmd_ctrl = 1;
}
void __attribute__((noinline, flatten, __section__(".text_bram"))) flash_sector_erase(flash_ctrl_dev *dev, uint32_t addr) {
// Write enable
dev->regs->flash_cmd_cfg = 0x00000006;
dev->regs->flash_cmd_ctrl = 1;
// Sector erase
dev->regs->flash_cmd_cfg = (dev->flash_size > 0x1000000) ? 0x000004DC : 0x000003D8;
dev->regs->flash_cmd_addr = addr;
dev->regs->flash_cmd_ctrl = 1;
// Poll status register until write has completed
while (1) {
dev->regs->flash_cmd_cfg = 0x00001805;
dev->regs->flash_cmd_ctrl = 1;
if (!(dev->regs->flash_cmd_rddata[0] & (1<<0)))
break;
}
}

34
software/sys_controller/memory/flash.h
View File

@ -20,22 +20,32 @@
#ifndef FLASH_H_
#define FLASH_H_
#include "alt_types.h"
#include <stdint.h>
#include "sysconfig.h"
#include "altera_epcq_controller2.h"
// EPCS16 pagesize is 256 bytes
// Flash is split 50-50 to FW and userdata, 1MB each
#define PAGESIZE 256
#define PAGES_PER_SECTOR 256 //EPCS "sector" corresponds to "block" on Spansion flash
#define SECTORSIZE (PAGESIZE*PAGES_PER_SECTOR)
#define USERDATA_OFFSET 0x100000
#define MAX_USERDATA_ENTRY 15 // 16 sectors for userdata
#define FLASH_SECTOR_SIZE 65536
#define FLASH_VERIFY_ERROR 204
typedef struct {
uint32_t ctrl;
uint32_t baud_rate;
uint32_t cs_delay;
uint32_t read_capture;
uint32_t oper_mode;
uint32_t read_instr;
uint32_t write_instr;
uint32_t flash_cmd_cfg;
uint32_t flash_cmd_ctrl;
uint32_t flash_cmd_addr;
uint32_t flash_cmd_wrdata[2];
uint32_t flash_cmd_rddata[2];
} gen_flash_if_regs;
typedef struct {
volatile gen_flash_if_regs *regs;
uint32_t flash_size;
} flash_ctrl_dev;
int init_flash();
int verify_flash(alt_u32 offset, alt_u32 length, alt_u32 golden_crc, alt_u8 *tmpbuf);
void flash_write_protect(flash_ctrl_dev *dev, int enable);
void flash_sector_erase(flash_ctrl_dev *dev, uint32_t addr);
#endif /* FLASH_H_ */

10
software/sys_controller/memory/sdcard.c
View File

@ -23,7 +23,7 @@
#include "flash.h"
#include "utils.h"
extern alt_flash_dev *epcq_dev;
//extern alt_flash_dev *epcq_dev;
SD_DEV sdcard_dev;
@ -45,7 +45,7 @@ int copy_sd_to_flash(alt_u32 sd_blknum, alt_u32 flash_pagenum, alt_u32 length, a
int retval, i;
alt_u32 bytes_to_rw;
while (length > 0) {
/*while (length > 0) {
bytes_to_rw = (length < SD_BLK_SIZE) ? length : SD_BLK_SIZE;
res = SD_Read(&sdcard_dev, tmpbuf, sd_blknum, 0, bytes_to_rw);
if (res != SD_OK) {
@ -68,7 +68,7 @@ int copy_sd_to_flash(alt_u32 sd_blknum, alt_u32 flash_pagenum, alt_u32 length, a
++sd_blknum;
flash_pagenum += bytes_to_rw/PAGESIZE;
length -= bytes_to_rw;
}
}*/
return 0;
}
@ -79,7 +79,7 @@ int copy_flash_to_sd(alt_u32 flash_pagenum, alt_u32 sd_blknum, alt_u32 length, a
int retval, i;
alt_u32 bytes_to_rw;
while (length > 0) {
/*while (length > 0) {
bytes_to_rw = (length < SD_BLK_SIZE) ? length : SD_BLK_SIZE;
retval = alt_epcq_controller2_read(epcq_dev, flash_pagenum*PAGESIZE, tmpbuf, bytes_to_rw);
for (i=0; i<bytes_to_rw; i++)
@ -99,7 +99,7 @@ int copy_flash_to_sd(alt_u32 flash_pagenum, alt_u32 sd_blknum, alt_u32 length, a
++sd_blknum;
flash_pagenum += bytes_to_rw/PAGESIZE;
length -= bytes_to_rw;
}
}*/
return 0;

8
software/sys_controller/ossc/av_controller.c
View File

@ -814,10 +814,10 @@ int init_hw()
}
#endif
if (init_flash() != 0) {
/*if (init_flash() != 0) {
printf("Error: could not find flash\n");
return -1;
}
}*/
// Set defaults
set_default_avconfig();
@ -828,8 +828,8 @@ int init_hw()
init_menu();
// Load initconfig and profile
read_userdata(INIT_CONFIG_SLOT, 0);
read_userdata(profile_sel, 0);
//read_userdata(INIT_CONFIG_SLOT, 0);
//read_userdata(profile_sel, 0);
// Setup test pattern
get_vmode(VMODE_480p, &vmode_in, &vmode_out, &vm_conf);

7
software/sys_controller/ossc/firmware.c
View File

@ -156,7 +156,7 @@ update_init:
strncpy(menu_row2, "please wait...", LCD_ROW_LEN+1);
ui_disp_menu(1);
retval = copy_sd_to_flash(512/SD_BLK_SIZE, 0, fw_header.data_len, databuf);
/*retval = copy_sd_to_flash(512/SD_BLK_SIZE, 0, fw_header.data_len, databuf);
if (retval != 0)
goto failure;
@ -164,7 +164,7 @@ update_init:
ui_disp_menu(1);
retval = verify_flash(0, fw_header.data_len, fw_header.data_crc, databuf);
if (retval != 0)
goto failure;
goto failure;*/
SPI_CS_High();
@ -197,9 +197,6 @@ failure:
case FW_UPD_CANCELLED:
errmsg = "Update cancelled";
break;
case -FLASH_VERIFY_ERROR:
errmsg = "Flash verif fail";
break;
default:
errmsg = "SD/Flash error";
break;

2
software/sys_controller/ossc/firmware.h
View File

@ -24,7 +24,7 @@
#include "sysconfig.h"
#define FW_VER_MAJOR 1
#define FW_VER_MINOR 12
#define FW_VER_MINOR 20
#define PROFILE_VER_MAJOR 1
#define PROFILE_VER_MINOR 12

76
software/sys_controller/ossc/menu.c
View File

@ -48,41 +48,41 @@ alt_u16 tc_h_samplerate, tc_h_samplerate_adj, tc_h_synclen, tc_h_bporch, tc_h_ac
alt_u8 menu_active;
alt_u8 vm_sel, vm_edit;
static const char *off_on_desc[] = { LNG("Off","ｵﾌ"), LNG("On","ｵﾝ") };
static const char *video_lpf_desc[] = { LNG("Auto","ｵｰﾄ"), LNG("Off","ｵﾌ"), "95MHz (HDTV II)", "35MHz (HDTV I)", "16MHz (EDTV)", "9MHz (SDTV)" };
static const char *ypbpr_cs_desc[] = { "Rec. 601", "Rec. 709", "Auto" };
static const char *s480p_mode_desc[] = { LNG("Auto","ｵｰﾄ"), "DTV 480p", "VESA 640x480@60", "PSP 480x272" };
static const char *s400p_mode_desc[] = { "VGA 640x400@70", "VGA 720x400@70" };
static const char *sync_lpf_desc[] = { LNG("2.5MHz (max)","2.5MHz (ｻｲﾀﾞｲ)"), LNG("10MHz (med)","10MHz (ﾁｭｳｲ)"), LNG("33MHz (min)","33MHz (ｻｲｼｮｳ)"), LNG("Off","ｵﾌ") };
static const char *stc_lpf_desc[] = { "4.8MHz (HDTV/PC)", "0.5MHz (SDTV)", "1.7MHz (EDTV)" };
static const char *pt_mode_desc[] = {"Normal", "High samplerate", LNG("512x240 optim.","512x240 ｻｲﾃｷｶ."), LNG("384x240 optim.","384x240 ｻｲﾃｷｶ."), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") };
static const char *l3_mode_desc[] = { LNG("Generic 16:9","ｼﾞｪﾈﾘｯｸ 16:9"), LNG("Generic 4:3","ｼﾞｪﾈﾘｯｸ 4:3"), LNG("512x240 optim.","512x240 ｻｲﾃｷｶ."), LNG("384x240 optim.","384x240 ｻｲﾃｷｶ."), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") };
static const char *l2l4l5l6_mode_desc[] = { LNG("Generic 4:3","ｼﾞｪﾈﾘｯｸ 4:3"), LNG("512x240 optim.","512x240 ｻｲﾃｷｶ."), LNG("384x240 optim.","384x240 ｻｲﾃｷｶ."), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") };
static const char *l5_fmt_desc[] = { "1920x1080", "1600x1200", "1920x1200" };
static const char *pm_240p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line3x", "Line4x", "Line5x", "Line6x" };
static const char *pm_480i_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x (bob)", "Line3x (laced)", "Line4x (bob)" };
static const char *pm_384p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line3x Generic", "Line2x 240x360", "Line3x 240x360" };
static const char *pm_480p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line3x Generic" };
static const char *pm_1080i_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x (bob)" };
static const char *ar_256col_desc[] = { "Pseudo 4:3 DAR", "1:1 PAR" };
static const char *tx_mode_desc[] = { "HDMI (RGB)", "HDMI (YCbCr444)", "DVI" };
static const char *sl_mode_desc[] = { LNG("Off","ｵﾌ"), LNG("Auto","ｵｰﾄ"), LNG("On","ｵﾝ") };
static const char *sl_method_desc[] = { LNG("Multiplication","Multiplication"), LNG("Subtraction","Subtraction") };
static const char *sl_type_desc[] = { LNG("Horizontal","ﾖｺ"), LNG("Vertical","ﾀﾃ"), "Horiz. + Vert.", "Custom" };
static const char *sl_id_desc[] = { LNG("Top","ｳｴ"), LNG("Bottom","ｼﾀ") };
static const char *audio_dw_sampl_desc[] = { LNG("Off (fs = 96kHz)","ｵﾌ (fs = 96kHz)"), "2x (fs = 48kHz)" };
static const char *lt_desc[] = { "Top-left", "Center", "Bottom-right" };
static const char *lcd_bl_timeout_desc[] = { "Off", "3s", "10s", "30s" };
static const char *osd_enable_desc[] = { "Off", "Full", "Simple" };
static const char *osd_status_desc[] = { "2s", "5s", "10s", "Off" };
static const char *rgsb_ypbpr_desc[] = { "RGsB", "YPbPr" };
static const char *auto_input_desc[] = { "Off", "Current input", "All inputs" };
static const char *mask_color_desc[] = { "Black", "Blue", "Green", "Cyan", "Red", "Magenta", "Yellow", "White" };
static const char *av3_alt_rgb_desc[] = { "Off", "AV1", "AV2" };
static const char *shmask_mode_desc[] = { "Off", "A-Grille", "TV", "PVM" };
static const char *lumacode_mode_desc[] = { "Off", "C64", "Spectrum", "Coleco/MSX", "NES", "Atari GTIA", "Atari VCS" };
static const char *adc_pll_bw_desc[] = { "High", "Medium", "Low", "Ultra low" };
static const char *fpga_pll_bw_desc[] = { "High", "Low" };
static const char* const off_on_desc[] = { LNG("Off","ｵﾌ"), LNG("On","ｵﾝ") };
static const char* const video_lpf_desc[] = { LNG("Auto","ｵｰﾄ"), LNG("Off","ｵﾌ"), "95MHz (HDTV II)", "35MHz (HDTV I)", "16MHz (EDTV)", "9MHz (SDTV)" };
static const char* const ypbpr_cs_desc[] = { "Rec. 601", "Rec. 709", "Auto" };
static const char* const s480p_mode_desc[] = { LNG("Auto","ｵｰﾄ"), "DTV 480p", "VESA 640x480@60", "PSP 480x272" };
static const char* const s400p_mode_desc[] = { "VGA 640x400@70", "VGA 720x400@70" };
static const char* const sync_lpf_desc[] = { LNG("2.5MHz (max)","2.5MHz (ｻｲﾀﾞｲ)"), LNG("10MHz (med)","10MHz (ﾁｭｳｲ)"), LNG("33MHz (min)","33MHz (ｻｲｼｮｳ)"), LNG("Off","ｵﾌ") };
static const char* const stc_lpf_desc[] = { "4.8MHz (HDTV/PC)", "0.5MHz (SDTV)", "1.7MHz (EDTV)" };
static const char* const pt_mode_desc[] = {"Normal", "High samplerate", LNG("512x240 optim.","512x240 ｻｲﾃｷｶ."), LNG("384x240 optim.","384x240 ｻｲﾃｷｶ."), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") };
static const char* const l3_mode_desc[] = { LNG("Generic 16:9","ｼﾞｪﾈﾘｯｸ 16:9"), LNG("Generic 4:3","ｼﾞｪﾈﾘｯｸ 4:3"), LNG("512x240 optim.","512x240 ｻｲﾃｷｶ."), LNG("384x240 optim.","384x240 ｻｲﾃｷｶ."), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") };
static const char* const l2l4l5l6_mode_desc[] = { LNG("Generic 4:3","ｼﾞｪﾈﾘｯｸ 4:3"), LNG("512x240 optim.","512x240 ｻｲﾃｷｶ."), LNG("384x240 optim.","384x240 ｻｲﾃｷｶ."), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") };
static const char* const l5_fmt_desc[] = { "1920x1080", "1600x1200", "1920x1200" };
static const char* const pm_240p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line3x", "Line4x", "Line5x", "Line6x" };
static const char* const pm_480i_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x (bob)", "Line3x (laced)", "Line4x (bob)" };
static const char* const pm_384p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line3x Generic", "Line2x 240x360", "Line3x 240x360" };
static const char* const pm_480p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line3x Generic" };
static const char* const pm_1080i_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x (bob)" };
static const char* const ar_256col_desc[] = { "Pseudo 4:3 DAR", "1:1 PAR" };
static const char* const tx_mode_desc[] = { "HDMI (RGB)", "HDMI (YCbCr444)", "DVI" };
static const char* const sl_mode_desc[] = { LNG("Off","ｵﾌ"), LNG("Auto","ｵｰﾄ"), LNG("On","ｵﾝ") };
static const char* const sl_method_desc[] = { LNG("Multiplication","Multiplication"), LNG("Subtraction","Subtraction") };
static const char* const sl_type_desc[] = { LNG("Horizontal","ﾖｺ"), LNG("Vertical","ﾀﾃ"), "Horiz. + Vert.", "Custom" };
static const char* const sl_id_desc[] = { LNG("Top","ｳｴ"), LNG("Bottom","ｼﾀ") };
static const char* const audio_dw_sampl_desc[] = { LNG("Off (fs = 96kHz)","ｵﾌ (fs = 96kHz)"), "2x (fs = 48kHz)" };
static const char* const lt_desc[] = { "Top-left", "Center", "Bottom-right" };
static const char* const lcd_bl_timeout_desc[] = { "Off", "3s", "10s", "30s" };
static const char* const osd_enable_desc[] = { "Off", "Full", "Simple" };
static const char* const osd_status_desc[] = { "2s", "5s", "10s", "Off" };
static const char* const rgsb_ypbpr_desc[] = { "RGsB", "YPbPr" };
static const char* const auto_input_desc[] = { "Off", "Current input", "All inputs" };
static const char* const mask_color_desc[] = { "Black", "Blue", "Green", "Cyan", "Red", "Magenta", "Yellow", "White" };
static const char* const av3_alt_rgb_desc[] = { "Off", "AV1", "AV2" };
static const char* const shmask_mode_desc[] = { "Off", "A-Grille", "TV", "PVM" };
static const char* const lumacode_mode_desc[] = { "Off", "C64", "Spectrum", "Coleco/MSX", "NES", "Atari GTIA", "Atari VCS" };
static const char* const adc_pll_bw_desc[] = { "High", "Medium", "Low", "Ultra low" };
static const char* const fpga_pll_bw_desc[] = { "High", "Low" };
static void sync_vth_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%d mV", (v*1127)/100); }
static void intclks_to_time_disp(alt_u8 v) { sniprintf(menu_row2, LCD_ROW_LEN+1, "%u.%.2u us", (unsigned)(((1000000U*v)/(TVP_INTCLK_HZ/1000))/1000), (unsigned)((((1000000U*v)/(TVP_INTCLK_HZ/1000))%1000)/10)); }
@ -298,7 +298,7 @@ void init_menu() {
}
void write_option_value(menuitem_t *item, int func_called, int retval)
void write_option_value(const menuitem_t *item, int func_called, int retval)
{
switch (item->type) {
case OPT_AVCONFIG_SELECTION:
@ -335,7 +335,7 @@ void write_option_value(menuitem_t *item, int func_called, int retval)
void render_osd_page() {
int i;
menuitem_t *item;
const menuitem_t *item;
uint32_t row_mask[2] = {0, 0};
if (!menu_active || (osd_enable != 1))
@ -360,7 +360,7 @@ void render_osd_page() {
void display_menu(alt_u8 forcedisp)
{
menucode_id code = NO_ACTION;
menuitem_t *item;
const menuitem_t *item;
alt_u8 *val, val_wrap, val_min, val_max;
alt_u16 *val_u16, val_u16_min, val_u16_max;
int i, func_called = 0, retval = 0;

6
software/sys_controller/ossc/menu.h
View File

@ -55,7 +55,7 @@ typedef struct {
alt_u8 wrap_cfg;
alt_u8 min;
alt_u8 max;
const char **setting_str;
const char *const *const setting_str;
} opt_avconfig_selection;
typedef struct {
@ -100,11 +100,11 @@ typedef struct {
struct menustruct {
alt_u8 num_items;
menuitem_t *items;
const menuitem_t *items;
};
#define SETTING_ITEM(x) 0, sizeof(x)/sizeof(char*)-1, x
#define MENU(X, Y) menuitem_t X##_items[] = Y; const menu_t X = { sizeof(X##_items)/sizeof(menuitem_t), X##_items };
#define MENU(X, Y) const menuitem_t X##_items[] = Y; const menu_t X = { sizeof(X##_items)/sizeof(menuitem_t), X##_items };
#define P99_PROTECT(...) __VA_ARGS__
typedef enum {

17
software/sys_controller/ossc/userdata.c
View File

@ -50,7 +50,6 @@ extern alt_u8 lcd_bl_timeout;
extern alt_u8 auto_input, auto_av1_ypbpr, auto_av2_ypbpr, auto_av3_ypbpr;
extern alt_u8 osd_enable, osd_status_timeout, phase_hotkey_enable;
extern SD_DEV sdcard_dev;
extern alt_flash_dev *epcq_dev;
extern char menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
char target_profile_name[PROFILE_NAME_LEN+1];
@ -92,9 +91,9 @@ int write_userdata(alt_u8 entry)
memcpy(((ude_initcfg*)databuf)->keys, rc_keymap, sizeof(rc_keymap));
for (i=0; i<sizeof(ude_initcfg); i++)
databuf[i] = bitswap8(databuf[i]);
retval = alt_epcq_controller2_write(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), databuf, sizeof(ude_initcfg));
/*retval = alt_epcq_controller2_write(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), databuf, sizeof(ude_initcfg));
if (retval != 0)
return retval;
return retval;*/
printf("Initconfig data written (%u bytes)\n", sizeof(ude_initcfg) - offsetof(ude_initcfg, last_profile));
break;
@ -122,9 +121,9 @@ int write_userdata(alt_u8 entry)
vm_to_write -= PAGESIZE-pageoffset;
for (i=0; i<PAGESIZE; i++)
databuf[i] = bitswap8(databuf[i]);
retval = alt_epcq_controller2_write(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), databuf, PAGESIZE);
/*retval = alt_epcq_controller2_write(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), databuf, PAGESIZE);
if (retval != 0)
return retval;
return retval;*/
// then write the rest page by page
pageno = 1;
@ -132,9 +131,9 @@ int write_userdata(alt_u8 entry)
memcpy(databuf, (char*)video_modes_plm+srcoffset, (vm_to_write > PAGESIZE) ? PAGESIZE : vm_to_write);
for (i=0; i<PAGESIZE; i++)
databuf[i] = bitswap8(databuf[i]);
retval = alt_epcq_controller2_write_block(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), (USERDATA_OFFSET+entry*SECTORSIZE+pageno*PAGESIZE), databuf, (vm_to_write > PAGESIZE) ? PAGESIZE : vm_to_write);
/*retval = alt_epcq_controller2_write_block(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), (USERDATA_OFFSET+entry*SECTORSIZE+pageno*PAGESIZE), databuf, (vm_to_write > PAGESIZE) ? PAGESIZE : vm_to_write);
if (retval != 0)
return retval;
return retval;*/
srcoffset += PAGESIZE;
vm_to_write = (vm_to_write < PAGESIZE) ? 0 : (vm_to_write - PAGESIZE);
@ -165,7 +164,7 @@ int read_userdata(alt_u8 entry, int dry_run)
return -1;
}
retval = alt_epcq_controller2_read(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), databuf, PAGESIZE);
//retval = alt_epcq_controller2_read(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE), databuf, PAGESIZE);
for (i=0; i<PAGESIZE; i++)
databuf[i] = bitswap8(databuf[i]);
if (retval != 0)
@ -236,7 +235,7 @@ int read_userdata(alt_u8 entry, int dry_run)
pageoffset = 0;
pageno++;
// check
retval = alt_epcq_controller2_read(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE+pageno*PAGESIZE), databuf, PAGESIZE);
//retval = alt_epcq_controller2_read(epcq_dev, (USERDATA_OFFSET+entry*SECTORSIZE+pageno*PAGESIZE), databuf, PAGESIZE);
for (i=0; i<PAGESIZE; i++)
databuf[i] = bitswap8(databuf[i]);
if (retval != 0)

8
software/sys_controller/ossc/userdata.h
View File

@ -30,6 +30,14 @@
#define PROFILE_NAME_LEN 12
// EPCS16 pagesize is 256 bytes
// Flash is split 50-50 to FW and userdata, 1MB each
#define PAGESIZE 256
#define PAGES_PER_SECTOR 256 //EPCS "sector" corresponds to "block" on Spansion flash
#define SECTORSIZE (PAGESIZE*PAGES_PER_SECTOR)
#define USERDATA_OFFSET 0x100000
#define MAX_USERDATA_ENTRY 15 // 16 sectors for userdata
#define MAX_PROFILE (MAX_USERDATA_ENTRY-1)
#define INIT_CONFIG_SLOT MAX_USERDATA_ENTRY

24
software/sys_controller_bsp/HAL/src/alt_busy_sleep.c
View File

@ -49,7 +49,16 @@
#include "priv/alt_busy_sleep.h"
unsigned int alt_busy_sleep (unsigned int us)
#define TIMER_BASED_SLEEP
#ifdef TIMER_BASED_SLEEP
#include "altera_avalon_timer.h"
#include "sys/alt_timestamp.h"
#endif
unsigned int __attribute__((noinline, flatten, __section__(".text_bram"))) alt_busy_sleep (unsigned int us)
{
/*
* Only delay if ALT_SIM_OPTIMIZE is not defined; i.e., if software
@ -57,6 +66,18 @@ unsigned int alt_busy_sleep (unsigned int us)
* skipped to speed up simulation.
*/
#ifndef ALT_SIM_OPTIMIZE
/*unsigned long i, loops;
// 1 loop >= 7 cyc
loops = ((ALT_CPU_FREQ/1000000)*us)/120;
for (i=7; i<loops; i++)
asm volatile ("nop");*/
#ifdef TIMER_BASED_SLEEP
alt_timestamp_type start_ts = alt_timestamp();
while (alt_timestamp() < start_ts + us*(TIMER_0_FREQ/1000000)) {}
#else
unsigned long i, loops;
// 1 loop >= 7 cyc
@ -64,6 +85,7 @@ unsigned int alt_busy_sleep (unsigned int us)
for (i=7; i<loops; i++)
asm volatile ("nop");
#endif
#endif /* #ifndef ALT_SIM_OPTIMIZE */
return 0;
}

28
software/sys_controller_bsp/HAL/src/alt_load.c
View File

@ -47,13 +47,15 @@
* Specifying __attribute__((section(".data"))) will force these
* in .data. (CASE:258384.)
*/
extern alt_u32 __flash_text_bram_start __attribute__((section(".data")));
extern alt_u32 __ram_text_start __attribute__((section(".data")));
extern alt_u32 __ram_text_end __attribute__((section(".data")));
extern alt_u32 __flash_rwdata_start __attribute__((section(".data")));
extern alt_u32 __ram_rwdata_start __attribute__((section(".data")));
extern alt_u32 __ram_rwdata_end __attribute__((section(".data")));
extern alt_u32 __flash_rodata_start __attribute__((section(".data")));
/*extern alt_u32 __flash_rodata_start __attribute__((section(".data")));
extern alt_u32 __ram_rodata_start __attribute__((section(".data")));
extern alt_u32 __ram_rodata_end __attribute__((section(".data")));
extern alt_u32 __ram_rodata_end __attribute__((section(".data")));*/
extern alt_u32 __flash_exceptions_start __attribute__((section(".data")));
extern alt_u32 __ram_exceptions_start __attribute__((section(".data")));
extern alt_u32 __ram_exceptions_end __attribute__((section(".data")));
@ -66,6 +68,14 @@ extern alt_u32 __ram_exceptions_end __attribute__((section(".data")));
void alt_load (void)
{
/*
* Copy the .text_bram section.
*/
alt_load_section (&__flash_text_bram_start,
&__ram_text_start,
&__ram_text_end);
/*
* Copy the .rwdata section.
*/
@ -78,22 +88,22 @@ void alt_load (void)
* Copy the exception handler.
*/
alt_load_section (&__flash_exceptions_start,
/*alt_load_section (&__flash_exceptions_start,
&__ram_exceptions_start,
&__ram_exceptions_end);
&__ram_exceptions_end);*/
/*
* Copy the .rodata section.
*/
alt_load_section (&__flash_rodata_start,
/*alt_load_section (&__flash_rodata_start,
&__ram_rodata_start,
&__ram_rodata_end);
&__ram_rodata_end);*/
/*
* Now ensure that the caches are in synch.
*/
alt_dcache_flush_all();
alt_icache_flush_all();
/*alt_dcache_flush_all();
alt_icache_flush_all();*/
}

9
software/sys_controller_bsp/Makefile
View File

@ -225,13 +225,6 @@ altera_avalon_timer_driver_C_LIB_SRCS := \
$(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_ts.c \
$(altera_avalon_timer_driver_SRCS_ROOT)/src/altera_avalon_timer_vars.c
# altera_epcq_controller2_driver sources root
altera_epcq_controller2_driver_SRCS_ROOT := drivers
# altera_epcq_controller2_driver sources
altera_epcq_controller2_driver_C_LIB_SRCS := \
$(altera_epcq_controller2_driver_SRCS_ROOT)/src/altera_epcq_controller2.c
# altera_nios2_gen2_hal_driver sources root
altera_nios2_gen2_hal_driver_SRCS_ROOT := HAL
@ -259,6 +252,7 @@ hal_C_LIB_SRCS := \
$(hal_SRCS_ROOT)/src/alt_dev_llist_insert.c \
$(hal_SRCS_ROOT)/src/alt_errno.c \
$(hal_SRCS_ROOT)/src/alt_flash_dev.c \
$(hal_SRCS_ROOT)/src/alt_load.c \
$(hal_SRCS_ROOT)/src/alt_main.c
# i2c_opencores_driver sources root
@ -276,7 +270,6 @@ nios2_hw_crc32_driver_SRCS_ROOT := drivers
COMPONENT_C_LIB_SRCS += \
$(altera_avalon_jtag_uart_driver_C_LIB_SRCS) \
$(altera_avalon_timer_driver_C_LIB_SRCS) \
$(altera_epcq_controller2_driver_C_LIB_SRCS) \
$(altera_nios2_gen2_hal_driver_C_LIB_SRCS) \
$(hal_C_LIB_SRCS) \
$(i2c_opencores_driver_C_LIB_SRCS) \

3
software/sys_controller_bsp/alt_sys_init.c
View File

@ -61,7 +61,6 @@
//#include "altera_nios2_gen2_irq.h"
#include "altera_avalon_jtag_uart.h"
#include "altera_avalon_timer.h"
#include "altera_epcq_controller2.h"
#include "i2c_opencores.h"
/*
@ -71,7 +70,6 @@
//ALTERA_NIOS2_GEN2_IRQ_INSTANCE ( NIOS2_QSYS_0, nios2_qsys_0);
ALTERA_AVALON_JTAG_UART_INSTANCE ( JTAG_UART_0, jtag_uart_0);
ALTERA_AVALON_TIMER_INSTANCE ( TIMER_0, timer_0);
ALTERA_EPCQ_CONTROLLER2_AVL_MEM_AVL_CSR_INSTANCE ( EPCQ_CONTROLLER2_0, EPCQ_CONTROLLER2_0_AVL_MEM, EPCQ_CONTROLLER2_0_AVL_CSR, epcq_controller2_0);
I2C_OPENCORES_INSTANCE ( I2C_OPENCORES_0, i2c_opencores_0);
I2C_OPENCORES_INSTANCE ( I2C_OPENCORES_1, i2c_opencores_1);
@ -98,7 +96,6 @@ void alt_sys_init( void )
{
ALTERA_AVALON_TIMER_INIT ( TIMER_0, timer_0);
ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART_0, jtag_uart_0);
ALTERA_EPCQ_CONTROLLER2_INIT ( EPCQ_CONTROLLER2_0, epcq_controller2_0);
I2C_OPENCORES_INIT ( I2C_OPENCORES_0, i2c_opencores_0);
I2C_OPENCORES_INIT ( I2C_OPENCORES_1, i2c_opencores_1);
}

126
software/sys_controller_bsp/drivers/inc/altera_epcq_controller2.h
View File

@ -1,126 +0,0 @@
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2015 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#ifndef __ALT_EPCQ_CONTROLLER2_H__
#define __ALT_EPCQ_CONTROLLER2_H__
#include "alt_types.h"
#include "sys/alt_flash_dev.h"
#include "sys/alt_llist.h"
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
/**
* Description of the EPCQ controller
*/
typedef struct alt_epcq_controller2_dev
{
alt_flash_dev dev;
alt_u32 data_base; /** base address of data slave */
alt_u32 data_end; /** end address of data slave (not inclusive) */
alt_u32 csr_base; /** base address of CSR slave */
alt_u32 size_in_bytes; /** size of memory in bytes */
alt_u32 is_epcs; /** 1 if device is an EPCS device */
alt_u32 number_of_sectors; /** number of flash sectors */
alt_u32 sector_size; /** size of each flash sector */
alt_u32 page_size; /** page size */
alt_u32 silicon_id; /** ID of silicon used with EPCQ IP */
} alt_epcq_controller2_dev;
/**
* Macros used by alt_sys_init.c to create data storage for driver instance
*/
#define ALTERA_EPCQ_CONTROLLER2_AVL_MEM_AVL_CSR_INSTANCE(epcq_name, avl_mem, avl_csr, epcq_dev) \
static alt_epcq_controller2_dev epcq_dev = \
{ \
.dev = { \
.llist = ALT_LLIST_ENTRY, \
.name = avl_mem##_NAME, \
.write = alt_epcq_controller2_write, \
.read = alt_epcq_controller2_read, \
.get_info = alt_epcq_controller2_get_info, \
.erase_block = alt_epcq_controller2_erase_block, \
.write_block = alt_epcq_controller2_write_block, \
.base_addr = ((void*)(avl_mem##_BASE)), \
.length = ((int)(avl_mem##_SPAN)), \
.lock = alt_epcq_controller2_lock , \
}, \
.data_base = ((alt_u32)(avl_mem##_BASE)), \
.data_end = ((alt_u32)(avl_mem##_BASE) + (alt_u32)(avl_mem##_SPAN)), \
.csr_base = ((alt_u32)(avl_csr##_BASE)), \
.size_in_bytes = ((alt_u32)(avl_mem##_SPAN)), \
.is_epcs = ((alt_u32)(avl_mem##_IS_EPCS)), \
.number_of_sectors = ((alt_u32)(avl_mem##_NUMBER_OF_SECTORS)), \
.sector_size = ((alt_u32)(avl_mem##_SECTOR_SIZE)), \
.page_size = ((alt_u32)(avl_mem##_PAGE_SIZE)) , \
}
/*
Public API
Refer to Using Flash Devices in the
Developing Programs Using the Hardware Abstraction Layer chapter
of the Nios II Software Developer's Handbook.
*/
int alt_epcq_controller2_read(alt_flash_dev *flash_info, int offset, void *dest_addr, int length);
int alt_epcq_controller2_get_info(alt_flash_fd *fd, flash_region **info, int *number_of_regions);
int alt_epcq_controller2_erase_block(alt_flash_dev *flash_info, int block_offset);
int alt_epcq_controller2_write_block(alt_flash_dev *flash_info, int block_offset, int data_offset, const void *data, int length);
int alt_epcq_controller2_write(alt_flash_dev *flash_info, int offset, const void *src_addr, int length);
int alt_epcq_controller2_lock(alt_flash_dev *flash_info, alt_u32 sectors_to_lock);
/*
* Initialization function
*/
extern alt_32 altera_epcq_controller2_init(alt_epcq_controller2_dev *dev);
/*
* alt_sys_init.c will call this macro automatically initialize the driver instance
*/
#define ALTERA_EPCQ_CONTROLLER2_INIT(name, dev) \
altera_epcq_controller2_init(&dev);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __ALT_EPCQ_CONTROLLER2_H__ */

261
software/sys_controller_bsp/drivers/inc/altera_epcq_controller2_regs.h
View File

@ -1,261 +0,0 @@
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2014 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#ifndef __ALTERA_EPCQ_CONTROLLER2_REGS_H__
#define __ALTERA_EPCQ_CONTROLLER2_REGS_H__
#include <io.h>
/*
* EPCQ_RD_STATUS register offset
*
* The EPCQ_RD_STATUS register contains information from the read status
* register operation. A full description of the register can be found in the
* data sheet,
*
*/
#define ALTERA_EPCQ_CONTROLLER2_STATUS_REG (0x0)
/*
* EPCQ_RD_STATUS register access macros
*/
#define IOADDR_ALTERA_EPCQ_CONTROLLER2_STATUS(base) \
__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_STATUS_REG)
#define IORD_ALTERA_EPCQ_CONTROLLER2_STATUS(base) \
IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_STATUS_REG)
#define IOWR_ALTERA_EPCQ_CONTROLLER2_STATUS(base, data) \
IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_STATUS_REG, data)
/*
* EPCQ_RD_STATUS register description macros
*/
/** Write in progress bit */
#define ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_MASK (0x00000001)
#define ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_AVAILABLE (0x00000000)
#define ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_BUSY (0x00000001)
/** When to time out a poll of the write in progress bit */
/* 0.7 sec time out */
#define ALTERA_EPCQ_CONTROLLER2_1US_TIMEOUT_VALUE 700000
/*
* EPCQ_RD_SID register offset
*
* The EPCQ_RD_SID register contains the information from the read silicon ID
* operation and can be used to determine what type of EPCS device we have.
* Only support in EPCS16 and EPCS64.
*
* This register is valid only if the device is an EPCS.
*
*/
#define ALTERA_EPCQ_CONTROLLER2_SID_REG (0x4)
/*
* EPCQ_RD_SID register access macros
*/
#define IOADDR_ALTERA_EPCQ_CONTROLLER2_SID(base) \
__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_SID_REG)
#define IORD_ALTERA_EPCQ_CONTROLLER2_SID(base) \
IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_SID_REG)
#define IOWR_ALTERA_EPCQ_CONTROLLER2_SID(base, data) \
IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_SID_REG, data)
/*
* EPCQ_RD_SID register description macros
*
* Specific device values obtained from Table 14 of:
* "Serial Configuration (EPCS) Devices Datasheet"
*/
#define ALTERA_EPCQ_CONTROLLER2_SID_MASK (0x000000FF)
#define ALTERA_EPCQ_CONTROLLER2_SID_EPCS16 (0x00000014)
#define ALTERA_EPCQ_CONTROLLER2_SID_EPCS64 (0x00000016)
#define ALTERA_EPCQ_CONTROLLER2_SID_EPCS128 (0x00000018)
/*
* EPCQ_RD_RDID register offset
*
* The EPCQ_RD_RDID register contains the information from the read memory
* capacity operation and can be used to determine what type of EPCQ device
* we have.
*
* This register is only valid if the device is an EPCQ.
*
*/
#define ALTERA_EPCQ_CONTROLLER2_RDID_REG (0x8)
/*
* EPCQ_RD_RDID register access macros
*/
#define IOADDR_ALTERA_EPCQ_CONTROLLER2_RDID(base) \
__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_RDID_REG)
#define IORD_ALTERA_EPCQ_CONTROLLER2_RDID(base) \
IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_RDID_REG)
#define IOWR_ALTERA_EPCQ_CONTROLLER2_RDID(base, data) \
IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_RDID_REG, data)
/*
* EPCQ_RD_RDID register description macros
*
* Specific device values obtained from Table 28 of:
* "Quad-Serial Configuration (EPCQ (www.altera.com/literature/hb/cfg/cfg_cf52012.pdf))
* Devices Datasheet"
*/
#define ALTERA_EPCQ_CONTROLLER2_RDID_MASK (0x000000FF)
#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ16 (0x00000015)
#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ32 (0x00000016)
#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ64 (0x00000017)
#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ128 (0x00000018)
#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ256 (0x00000019)
#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ512 (0x00000020)
#define ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ1024 (0x00000021)
/*
* EPCQ_MEM_OP register offset
*
* The EPCQ_MEM_OP register is used to do memory protect and erase operations
*
*/
#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_REG (0xC)
/*
* EPCQ_MEM_OP register access macros
*/
#define IOADDR_ALTERA_EPCQ_CONTROLLER2_MEM_OP(base) \
__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_MEM_OP_REG)
#define IORD_ALTERA_EPCQ_CONTROLLER2_MEM_OP(base) \
IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_MEM_OP_REG)
#define IOWR_ALTERA_EPCQ_CONTROLLER2_MEM_OP(base, data) \
IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_MEM_OP_REG, data)
/*
* EPCQ_MEM_OP register description macros
*/
#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_CMD_MASK (0x00000003)
#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_BULK_ERASE_CMD (0x00000001)
#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_ERASE_CMD (0x00000002)
#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_PROTECT_CMD (0x00000003)
#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_WRITE_ENABLE_CMD (0x00000004)
/** see datasheet for sector values */
#define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_VALUE_MASK (0x00FFFF00)
/*
* EPCQ_ISR register offset
*
* The EPCQ_ISR register is used to determine whether an invalid write or erase
* operation triggered an interrupt
*
*/
#define ALTERA_EPCQ_CONTROLLER2_ISR_REG (0x10)
/*
* EPCQ_ISR register access macros
*/
#define IOADDR_ALTERA_EPCQ_CONTROLLER2_ISR(base) \
__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_ISR_REG)
#define IORD_ALTERA_EPCQ_CONTROLLER2_ISR(base) \
IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_ISR_REG)
#define IOWR_ALTERA_EPCQ_CONTROLLER2_ISR(base, data) \
IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_ISR_REG, data)
/*
* EPCQ_ISR register description macros
*/
#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_MASK (0x00000001)
#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_ACTIVE (0x00000001)
#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_MASK (0x00000002)
#define ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_ACTIVE (0x00000002)
/*
* EPCQ_IMR register offset
*
* The EPCQ_IMR register is used to mask the invalid erase or the invalid write
* interrupts.
*
*/
#define ALTERA_EPCQ_CONTROLLER2_IMR_REG (0x14)
/*
* EPCQ_IMR register access macros
*/
#define IOADDR_ALTERA_EPCQ_CONTROLLER2_IMR(base) \
__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER2_IMR_REG)
#define IORD_ALTERA_EPCQ_CONTROLLER2_IMR(base) \
IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_IMR_REG)
#define IOWR_ALTERA_EPCQ_CONTROLLER2_IMR(base, data) \
IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER2_IMR_REG, data)
/*
* EPCQ_IMR register description macros
*/
#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_ERASE_MASK (0x00000001)
#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_ERASE_ENABLED (0x00000001)
#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_WRITE_MASK (0x00000002)
#define ALTERA_EPCQ_CONTROLLER2_IMR_ILLEGAL_WRITE_ENABLED (0x00000002)
/*
* EPCQ_CHIP_SELECT register offset
*
* The EPCQ_CHIP_SELECT register is used to issue chip select
*/
#define ALTERA_EPCQ_CHIP_SELECT_REG (0x18)
/*
* EPCQ_CHIP_SELECT register access macros
*/
#define IOADDR_ALTERA_EPCQ_CHIP_SELECT(base) \
__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CHIP_SELECT_REG)
#define IOWR_ALTERA_EPCQ_CHIP_SELECT(base, data) \
IOWR_32DIRECT(base, ALTERA_EPCQ_CHIP_SELECT_REG, data)
/*
* EPCQ_CHIP_SELECT register description macros
*/
#define ALTERA_EPCQ_CHIP1_SELECT (0x00000001)
#define ALTERA_EPCQ_CHIP2_SELECT (0x00000002)
#define ALTERA_EPCQ_CHIP3_SELECT (0x00000003)
#endif /* __ALTERA_EPCQ_CONTROLLER2_REGS_H__ */

2
software/sys_controller_bsp/drivers/src/altera_avalon_timer_ts.c
View File

@ -97,7 +97,7 @@ int alt_timestamp_start(void)
* was reset.
*/
alt_timestamp_type alt_timestamp(void)
alt_timestamp_type __attribute__((noinline, flatten, __section__(".text_bram"))) alt_timestamp(void)
{
void* base = altera_avalon_timer_ts_base;

810
software/sys_controller_bsp/drivers/src/altera_epcq_controller2.c
View File

@ -1,810 +0,0 @@
/******************************************************************************
* *
* License Agreement *
* *
* Copyright (c) 2015 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included in *
* all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
#include <errno.h>
#include <io.h>
#include <string.h>
#include <stddef.h>
#include "sys/param.h"
#include "alt_types.h"
#include "altera_epcq_controller2_regs.h"
#include "altera_epcq_controller2.h"
#include "priv/alt_busy_sleep.h"
#include "sys/alt_debug.h"
#include "sys/alt_cache.h"
ALT_INLINE alt_32 static alt_epcq_validate_read_write_arguments(alt_epcq_controller2_dev *flash_info,alt_u32 offset, alt_u32 length);
alt_32 static alt_epcq_poll_for_write_in_progress(alt_epcq_controller2_dev* epcq_flash_info);
/*
* Public API
*
* Refer to “Using Flash Devices” in the
* Developing Programs Using the Hardware Abstraction Layer chapter
* of the Nios II Software Developer’s Handbook.
*/
/**
* alt_epcq_controller2_lock
*
* Locks the range of the memory sectors, which
* protected from write and erase.
*
* Arguments:
* - *flash_info: Pointer to general flash device structure.
* - sectors_to_lock: Block protection bits in EPCQ ==> Bit4 | Bit3 | Bit2 | Bit1 | Bit0
* TB | BP3 | BP2 | BP1 | BP0
* For details of setting sectors protection, please refer to EPCQ datasheet.
*
* Returns:
* 0 -> success
* -EINVAL -> Invalid arguments
* -ETIME -> Time out and skipping the looping after 0.7 sec.
* -ENOLCK -> Sectors lock failed.
**/
int alt_epcq_controller2_lock(alt_flash_dev *flash_info, alt_u32 sectors_to_lock)
{
alt_u32 mem_op_value = 0; /* value to write to EPCQ_MEM_OP register */
alt_epcq_controller2_dev* epcq_flash_info = NULL;
alt_u32 result = 0;
alt_32 status = 0;
/* return -EINVAL if flash_info is NULL */
if(NULL == flash_info || 0 > sectors_to_lock)
{
return -EINVAL;
}
epcq_flash_info = (alt_epcq_controller2_dev*)flash_info;
/* sector value should occupy bits 17:8 */
mem_op_value = sectors_to_lock << 8;
/* sector protect commands 0b11 occupies lower 2 bits */
mem_op_value |= ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_PROTECT_CMD;
/* write sector protect command to EPCQ_MEM_OP register to protect sectors */
IOWR_ALTERA_EPCQ_CONTROLLER2_MEM_OP(epcq_flash_info->csr_base, mem_op_value);
/* poll write in progress to make sure no operation is in progress */
status = alt_epcq_poll_for_write_in_progress(epcq_flash_info);
if(status != 0)
{
return status;
}
status = IORD_ALTERA_EPCQ_CONTROLLER2_STATUS(epcq_flash_info->csr_base);
result |= (status >> 2) & 0x07; /* extract out BP3 - BP0 */
result |= (status >> 3) & 0x08; /* extract out BP4 */
result |= (status >> 1) & 0x10; /* extract out TOP/BOTTOM bit */
if(result != sectors_to_lock)
{
/*return -ENOLCK;*/
}
return 0;
}
/**
* alt_epcq_controller2_get_info
*
* Pass the table of erase blocks to the user. This flash will return a single
* flash_region that gives the number and size of sectors for the device used.
*
* Arguments:
* - *fd: Pointer to general flash device structure.
* - **info: Pointer to flash region
* - *number_of_regions: Pointer to number of regions
*
* For details of setting sectors protection, please refer to EPCQ datasheet.
*
* Returns:
* 0 -> success
* -EINVAL -> Invalid arguments
* -EIO -> Could be hardware problem.
**/
int alt_epcq_controller2_get_info
(
alt_flash_fd *fd, /** flash device descriptor */
flash_region **info, /** pointer to flash_region will be stored here */
int *number_of_regions /** number of regions will be stored here */
)
{
alt_flash_dev* flash = NULL;
/* return -EINVAL if fd,info and number_of_regions are NULL */
if(NULL == fd || NULL == info || NULL == number_of_regions)
{
return -EINVAL;
}
flash = (alt_flash_dev*)fd;
*number_of_regions = flash->number_of_regions;
if (!flash->number_of_regions)
{
return -EIO;
}
else
{
*info = &flash->region_info[0];
}
return 0;
}
/**
* alt_epcq_controller2_erase_block
*
* This function erases a single flash sector.
*
* Arguments:
* - *flash_info: Pointer to EPCQ flash device structure.
* - block_offset: byte-addressed offset, from start of flash, of the sector to be erased
*
* Returns:
* 0 -> success
* -EINVAL -> Invalid arguments
* -EIO -> write failed, sector might be protected
**/
int alt_epcq_controller2_erase_block(alt_flash_dev *flash_info, int block_offset)
{
alt_32 ret_code = 0;
alt_u32 mem_op_value = 0; /* value to write to EPCQ_MEM_OP register */
alt_epcq_controller2_dev* epcq_flash_info = NULL;
alt_u32 sector_number = 0;
/* return -EINVAL if flash_info is NULL */
if(NULL == flash_info)
{
return -EINVAL;
}
epcq_flash_info = (alt_epcq_controller2_dev*)flash_info;
/*
* Sanity checks that block_offset is within the flash memory span and that the
* block offset is sector aligned.
*
*/
if((block_offset < 0)
|| (block_offset >= epcq_flash_info->size_in_bytes)
|| (block_offset & (epcq_flash_info->sector_size - 1)) != 0)
{
return -EINVAL;
}
/* calculate current sector/block number */
sector_number = (block_offset/(epcq_flash_info->sector_size));
/* sector value should occupy bits 23:8 */
mem_op_value = (sector_number << 8) & ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_VALUE_MASK;
/* write enable command */
mem_op_value |= ALTERA_EPCQ_CONTROLLER2_MEM_OP_WRITE_ENABLE_CMD;
/* write sector erase command to EPCQ_MEM_OP register to erase sector "sector_number" */
IOWR_ALTERA_EPCQ_CONTROLLER2_MEM_OP(epcq_flash_info->csr_base, mem_op_value);
/* sector value should occupy bits 23:8 */
mem_op_value = (sector_number << 8) & ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_VALUE_MASK;
/* sector erase commands 0b10 occupies lower 2 bits */
mem_op_value |= ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_ERASE_CMD;
/* write sector erase command to EPCQ_MEM_OP register to erase sector "sector_number" */
IOWR_ALTERA_EPCQ_CONTROLLER2_MEM_OP(epcq_flash_info->csr_base, mem_op_value);
/* check whether erase triggered a illegal erase interrupt */
if((IORD_ALTERA_EPCQ_CONTROLLER2_ISR(epcq_flash_info->csr_base) &
ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_MASK) ==
ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_ACTIVE)
{
/* clear register */
/* EPCQ_ISR access is write one to clear (W1C) */
IOWR_ALTERA_EPCQ_CONTROLLER2_ISR(epcq_flash_info->csr_base,
ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_MASK );
return -EIO; /* erase failed, sector might be protected */
}
return ret_code;
}
/**
* alt_epcq_controller2_write_block
*
* This function writes one block/sector of data to flash. The length of the write can NOT
* spill into the adjacent sector.
*
* It assumes that someone has already erased the appropriate sector(s).
*
* Arguments:
* - *flash_info: Pointer to EPCQ flash device structure.
* - block_offset: byte-addressed offset, from the start of flash, of the sector to written to
* - data-offset: Byte offset (unaligned access) of write into flash memory.
* For best performance, word(32 bits - aligned access) offset of write is recommended.
* - *src_addr: source buffer
* - length: size of writing
*
* Returns:
* 0 -> success
* -EINVAL -> Invalid arguments
* -EIO -> write failed, sector might be protected
**/
int alt_epcq_controller2_write_block
(
alt_flash_dev *flash_info, /** flash device info */
int block_offset, /** sector/block offset in byte addressing */
int data_offset, /** offset of write from base address */
const void *data, /** data to be written */
int length /** bytes of data to be written, >0 */
)
{
alt_u32 buffer_offset = 0; /** offset into data buffer to get write data */
alt_u32 remaining_length = length; /** length left to write */
alt_u32 write_offset = data_offset; /** offset into flash to write too */
alt_epcq_controller2_dev *epcq_flash_info = (alt_epcq_controller2_dev*)flash_info;
/*
* Sanity checks that data offset is not larger then a sector, that block offset is
* sector aligned and within the valid flash memory range and a write doesn't spill into
* the adjacent flash sector.
*/
if(block_offset < 0
|| data_offset < 0
|| NULL == flash_info
|| NULL == data
|| data_offset >= epcq_flash_info->size_in_bytes
|| block_offset >= epcq_flash_info->size_in_bytes
|| length > (epcq_flash_info->sector_size - (data_offset - block_offset))
|| length < 0
|| (block_offset & (epcq_flash_info->sector_size - 1)) != 0)
{
return -EINVAL;
}
/*
* Do writes one 32-bit word at a time.
* We need to make sure that we pad the first few bytes so they're word aligned if they are
* not already.
*/
while (remaining_length > 0)
{
alt_u32 word_to_write = 0xFFFFFFFF; /** initialize word to write to blank word */
alt_u32 padding = 0; /** bytes to pad the next word that is written */
alt_u32 bytes_to_copy = sizeof(alt_u32); /** number of bytes from source to copy */
/*
* we need to make sure the write is word aligned
* this should only be true at most 1 time
*/
if (0 != (write_offset & (sizeof(alt_u32) - 1)))
{
/*
* data is not word aligned
* calculate padding bytes need to add before start of a data offset
*/
padding = write_offset & (sizeof(alt_u32) - 1);
/* update variables to account for padding being added */
bytes_to_copy -= padding;
if(bytes_to_copy > remaining_length)
{
bytes_to_copy = remaining_length;
}
write_offset = write_offset - padding;
if(0 != (write_offset & (sizeof(alt_u32) - 1)))
{
return -EINVAL;
}
}
else
{
if(bytes_to_copy > remaining_length)
{
bytes_to_copy = remaining_length;
}
}
/* prepare the word to be written */
memcpy((((void*)&word_to_write)) + padding, ((void*)data) + buffer_offset, bytes_to_copy);
/* update offset and length variables */
buffer_offset += bytes_to_copy;
remaining_length -= bytes_to_copy;
/* write to flash 32 bits at a time */
IOWR_32DIRECT(epcq_flash_info->data_base, write_offset, word_to_write);
if (IORD_32DIRECT(epcq_flash_info->data_base, write_offset) != word_to_write)
{
IOWR_32DIRECT(epcq_flash_info->data_base, write_offset, word_to_write);
}
/* check whether write triggered a illegal write interrupt */
if((IORD_ALTERA_EPCQ_CONTROLLER2_ISR(epcq_flash_info->csr_base) &
ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_MASK) ==
ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_ACTIVE)
{
/* clear register */
IOWR_ALTERA_EPCQ_CONTROLLER2_ISR(epcq_flash_info->csr_base,
ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_WRITE_MASK );
return -EIO; /** write failed, sector might be protected */
}
/* update current offset */
write_offset = write_offset + sizeof(alt_u32);
}
return 0;
}
/**
* alt_epcq_controller2_write
*
* Program the data into the flash at the selected address.
*
* The different between this function and alt_epcq_controller2_write_block function
* is that this function (alt_epcq_controller2_write) will automatically erase a block as needed
* Arguments:
* - *flash_info: Pointer to EPCQ flash device structure.
* - offset: Byte offset (unaligned access) of write to flash memory. For best performance,
* word(32 bits - aligned access) offset of write is recommended.
* - *src_addr: source buffer
* - length: size of writing
*
* Returns:
* 0 -> success
* -EINVAL -> Invalid arguments
* -EIO -> write failed, sector might be protected
*
**/
int alt_epcq_controller2_write(
alt_flash_dev *flash_info, /** device info */
int offset, /** offset of write from base address */
const void *src_addr, /** source buffer */
int length /** size of writing */
)
{
alt_32 ret_code = 0;
alt_epcq_controller2_dev *epcq_flash_info = NULL;
alt_u32 write_offset = offset; /** address of next byte to write */
alt_u32 remaining_length = length; /** length of write data left to be written */
alt_u32 buffer_offset = 0; /** offset into source buffer to get write data */
alt_u32 i = 0;
/* return -EINVAL if flash_info and src_addr are NULL */
if(NULL == flash_info || NULL == src_addr)
{
return -EINVAL;
}
epcq_flash_info = (alt_epcq_controller2_dev*)flash_info;
/* make sure the write parameters are within the bounds of the flash */
ret_code = alt_epcq_validate_read_write_arguments(epcq_flash_info, offset, length);
if(0 != ret_code)
{
return ret_code;
}
/*
* This loop erases and writes data one sector at a time. We check for write completion
* before starting the next sector.
*/
for(i = offset/epcq_flash_info->sector_size ; i < epcq_flash_info->number_of_sectors; i++)
{
alt_u32 block_offset = 0; /** block offset in byte addressing */
alt_u32 offset_within_current_sector = 0; /** offset into current sector to write */
alt_u32 length_to_write = 0; /** length to write to current sector */
if(0 >= remaining_length)
{
break; /* out of data to write */
}
/* calculate current sector/block offset in byte addressing */
block_offset = write_offset & ~(epcq_flash_info->sector_size - 1);
/* calculate offset into sector/block if there is one */
if(block_offset != write_offset)
{
offset_within_current_sector = write_offset - block_offset;
}
/* erase sector */
ret_code = alt_epcq_controller2_erase_block(flash_info, block_offset);
if(0 != ret_code)
{
return ret_code;
}
/* calculate the byte size of data to be written in a sector */
length_to_write = MIN(epcq_flash_info->sector_size - offset_within_current_sector,
remaining_length);
/* write data to erased block */
ret_code = alt_epcq_controller2_write_block(flash_info, block_offset, write_offset,
src_addr + buffer_offset, length_to_write);
if(0 != ret_code)
{
return ret_code;
}
/* update remaining length and buffer_offset pointer */
remaining_length -= length_to_write;
buffer_offset += length_to_write;
write_offset += length_to_write;
}
return ret_code;
}
/**
* alt_epcq_controller2_read
*
* There's no real need to use this function as opposed to using memcpy directly. It does
* do some sanity checks on the bounds of the read.
*
* Arguments:
* - *flash_info: Pointer to general flash device structure.
* - offset: offset read from flash memory.
* - *dest_addr: destination buffer
* - length: size of reading
*
* Returns:
* 0 -> success
* -EINVAL -> Invalid arguments
**/
int alt_epcq_controller2_read
(
alt_flash_dev *flash_info, /** device info */
int offset, /** offset of read from base address */
void *dest_addr, /** destination buffer */
int length /** size of read */
)
{
alt_32 ret_code = 0;
alt_epcq_controller2_dev *epcq_flash_info = NULL;
/* return -EINVAL if flash_info and dest_addr are NULL */
if(NULL == flash_info || NULL == dest_addr)
{
return -EINVAL;
}
epcq_flash_info = (alt_epcq_controller2_dev*)flash_info;
/* validate arguments */
ret_code = alt_epcq_validate_read_write_arguments(epcq_flash_info, offset, length);
/* copy data from flash to destination address */
if(0 == ret_code)
{
memcpy(dest_addr, (alt_u8*)epcq_flash_info->data_base + offset, length);
}
return ret_code;
}
/**
* altera_epcq_controller2_init
*
* alt_sys_init.c will call this function automatically through macro
*
* Information in system.h is checked against expected values that are determined by the silicon_id.
* If the information doesn't match then this system is configured incorrectly. Most likely the wrong
* type of EPCS or EPCQ device was selected when instantiating the soft IP.
*
* Arguments:
* - *flash: Pointer to EPCQ flash device structure.
*
* Returns:
* 0 -> success
* -EINVAL -> Invalid arguments.
* -ENODEV -> System is configured incorrectly.
**/
alt_32 altera_epcq_controller2_init(alt_epcq_controller2_dev *flash)
{
alt_u32 silicon_id = 0;
alt_u32 size_in_bytes = 0;
alt_u32 number_of_sectors = 0;
/* return -EINVAL if flash is NULL */
if(NULL == flash)
{
return -EINVAL;
}
/* return -ENODEV if CSR slave is not attached */
if(NULL == (void *)flash->csr_base)
{
return -ENODEV;
}
/*
* If flash is an EPCQ device, we read the EPCQ_RD_RDID register for the ID
* If flash is an EPCS device, we read the EPCQ_RD_SID register for the ID
*
* Whether or not the flash is a EPCQ or EPCS is indicated in the system.h. The system.h gets
* this value from the hw.tcl of the IP. If this value is set incorrectly, then things will go
* badly.
*
* In both cases, we can determine the number of sectors, which we can use
* to calculate a size. We compare that size to the system.h value to make sure
* the EPCQ soft IP was configured correctly.
*/
if(0 == flash->is_epcs)
{
/* If we're an EPCQ, we read EPCQ_RD_RDID for the silicon ID */
silicon_id = IORD_ALTERA_EPCQ_CONTROLLER2_RDID(flash->csr_base);
silicon_id &= ALTERA_EPCQ_CONTROLLER2_RDID_MASK;
/* Determine which EPCQ device so we can figure out the number of sectors */
/* EPCQ share the same ID for the same capacity*/
switch(silicon_id)
{
case ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ16:
{
number_of_sectors = 32;
break;
}
case ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ32:
{
number_of_sectors = 64;
break;
}
case ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ64:
{
number_of_sectors = 128;
break;
}
case ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ128:
{
number_of_sectors = 256;
break;
}
case ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ256:
{
number_of_sectors = 512;
break;
}
case ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ512:
{
number_of_sectors = 1024;
break;
}
case ALTERA_EPCQ_CONTROLLER2_RDID_EPCQ1024:
{
number_of_sectors = 2048;
break;
}
default:
{
return -ENODEV;
}
}
}
else {
/* If we're an EPCS, we read EPCQ_RD_SID for the silicon ID */
silicon_id = IORD_ALTERA_EPCQ_CONTROLLER2_SID(flash->csr_base);
silicon_id &= ALTERA_EPCQ_CONTROLLER2_SID_MASK;
/* Determine which EPCS device so we can figure out various properties */
switch(silicon_id)
{
case ALTERA_EPCQ_CONTROLLER2_SID_EPCS16:
{
number_of_sectors = 32;
break;
}
case ALTERA_EPCQ_CONTROLLER2_SID_EPCS64:
{
number_of_sectors = 128;
break;
}
case ALTERA_EPCQ_CONTROLLER2_SID_EPCS128:
{
number_of_sectors = 256;
break;
}
default:
{
return -ENODEV;
}
}
}
/* Calculate size of flash based on number of sectors */
size_in_bytes = number_of_sectors * flash->sector_size;
/*
* Make sure calculated size is the same size given in system.h
* Also check number of sectors is the same number given in system.h
* Otherwise the EPCQ IP was not configured correctly
*/
if( size_in_bytes != flash->size_in_bytes ||
number_of_sectors != flash->number_of_sectors)
{
flash->dev.number_of_regions = 0;
return -ENODEV;
}
else
{
flash->silicon_id = silicon_id;
flash->number_of_sectors = number_of_sectors;
/*
* populate fields of region_info required to conform to HAL API
* create 1 region that composed of "number_of_sectors" blocks
*/
flash->dev.number_of_regions = 1;
flash->dev.region_info[0].offset = 0;
flash->dev.region_info[0].region_size = size_in_bytes;
flash->dev.region_info[0].number_of_blocks = number_of_sectors;
flash->dev.region_info[0].block_size = flash->sector_size;
}
/*
* Register this device as a valid flash device type
*
* Only register the device if it's configured correctly.
*/
alt_flash_device_register(&(flash->dev));
return 0;
}
/*
* Private API
*
* Helper functions used by Public API functions.
*
* Arguments:
* - *flash_info: Pointer to EPCQ flash device structure.
* - offset: Offset of read/write from base address.
* - length: Length of read/write in bytes.
*
* Returns:
* 0 -> success
* -EINVAL -> Invalid arguments
*/
/**
* Used to check that arguments to a read or write are valid
*/
ALT_INLINE alt_32 static alt_epcq_validate_read_write_arguments
(
alt_epcq_controller2_dev *flash_info, /** device info */
alt_u32 offset, /** offset of read/write */
alt_u32 length /** length of read/write */
)
{
alt_epcq_controller2_dev *epcq_flash_info = NULL;
alt_u32 start_address = 0;
alt_32 end_address = 0;
/* return -EINVAL if flash_info is NULL */
if(NULL == flash_info)
{
return -EINVAL;
}
epcq_flash_info = (alt_epcq_controller2_dev*)flash_info;
start_address = epcq_flash_info->data_base + offset; /** first address of read or write */
end_address = start_address + length; /** last address of read or write (not inclusive) */
/* make sure start and end address is less then the end address of the flash */
if(
start_address >= epcq_flash_info->data_end ||
end_address > epcq_flash_info->data_end ||
offset < 0 ||
length < 0
)
{
return -EINVAL;
}
return 0;
}
/*
* Private function that polls write in progress bit EPCQ_RD_STATUS.
*
* Write in progress will be set if any of the following operations are in progress:
* -WRITE STATUS REGISTER
* -WRITE NONVOLATILE CONFIGURATION REGISTER
* -PROGRAM
* -ERASE
*
* Assumes EPCQ was configured correctly.
*
* If ALTERA_EPCQ_CONTROLLER2_1US_TIMEOUT_VALUE is set, the function will time out after
* a period of time determined by that value.
*
* Arguments:
* - *epcq_flash_info: Pointer to EPCQ flash device structure.
*
* Returns:
* 0 -> success
* -EINVAL -> Invalid arguments
* -ETIME -> Time out and skipping the looping after 0.7 sec.
*/
alt_32 static alt_epcq_poll_for_write_in_progress(alt_epcq_controller2_dev* epcq_flash_info)
{
/* we'll want to implement timeout if a timeout value is specified */
#if ALTERA_EPCQ_CONTROLLER2_1US_TIMEOUT_VALUE > 0
alt_u32 timeout = ALTERA_EPCQ_CONTROLLER2_1US_TIMEOUT_VALUE;
alt_u16 counter = 0;
#endif
/* return -EINVAL if epcq_flash_info is NULL */
if(NULL == epcq_flash_info)
{
return -EINVAL;
}
/* while Write in Progress bit is set, we wait */
while((IORD_ALTERA_EPCQ_CONTROLLER2_STATUS(epcq_flash_info->csr_base) &
ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_MASK) ==
ALTERA_EPCQ_CONTROLLER2_STATUS_WIP_BUSY)
{
alt_busy_sleep(1); /* delay 1us */
#if ALTERA_EPCQ_CONTROLLER2_1US_TIMEOUT_VALUE > 0
if(timeout <= counter )
{
return -ETIME;
}
counter++;
#endif
}
return 0;
}

BIN
software/sys_controller_bsp/libhal_bsp.a
View File

Binary file not shown.

2
software/sys_controller_bsp/public.mk
View File

@ -259,7 +259,7 @@ ALT_CPPFLAGS += -DSMALL_C_LIB
# or common. none
# setting hal.make.cflags_mgpopt is -mgpopt=global
#ALT_CFLAGS += -mgpopt=global
ALT_CFLAGS += -march=rv32emc -mabi=ilp32e
ALT_CFLAGS += -march=rv32emc_zicsr_zifencei -mabi=ilp32e
# Enable BSP generation to query if SOPC system is big endian. If true ignores
# export of 'ALT_CFLAGS += -meb' to public.mk if big endian system. none

60
software/sys_controller_bsp/system.h
View File

@ -52,7 +52,7 @@
#define __SYSTEM_H_
/* Include definitions from linker script generator */
#include "linker.h"
//#include "linker.h"
/*
@ -151,7 +151,7 @@
#define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_TIMER
#define __ALTERA_EPCQ_CONTROLLER2
#define __INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP
#define __ALTERA_NIOS2_GEN2
#define __ALTERA_NIOS_CUSTOM_INSTR_BITSWAP
#define __ALTERA_NIOS_CUSTOM_INSTR_ENDIANCONVERTER
@ -175,19 +175,19 @@
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
#define ALT_STDERR "/dev/jtag_uart_0"
#define ALT_STDERR_BASE 0x20020
#define ALT_STDERR_BASE 0x20040
#define ALT_STDERR_DEV jtag_uart_0
#define ALT_STDERR_IS_JTAG_UART
#define ALT_STDERR_PRESENT
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN "/dev/jtag_uart_0"
#define ALT_STDIN_BASE 0x20020
#define ALT_STDIN_BASE 0x20040
#define ALT_STDIN_DEV jtag_uart_0
#define ALT_STDIN_IS_JTAG_UART
#define ALT_STDIN_PRESENT
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT "/dev/jtag_uart_0"
#define ALT_STDOUT_BASE 0x20020
#define ALT_STDOUT_BASE 0x20040
#define ALT_STDOUT_DEV jtag_uart_0
#define ALT_STDOUT_IS_JTAG_UART
#define ALT_STDOUT_PRESENT
@ -196,43 +196,31 @@
/*
* epcq_controller2_0_avl_csr configuration
* intel_generic_serial_flash_interface_top_0_avl_csr configuration
*
*/
#define ALT_MODULE_CLASS_epcq_controller2_0_avl_csr altera_epcq_controller2
#define EPCQ_CONTROLLER2_0_AVL_CSR_BASE 0x20100
#define EPCQ_CONTROLLER2_0_AVL_CSR_FLASH_TYPE "EPCQ16"
#define EPCQ_CONTROLLER2_0_AVL_CSR_IRQ 2
#define EPCQ_CONTROLLER2_0_AVL_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
#define EPCQ_CONTROLLER2_0_AVL_CSR_IS_EPCS 0
#define EPCQ_CONTROLLER2_0_AVL_CSR_NAME "/dev/epcq_controller2_0_avl_csr"
#define EPCQ_CONTROLLER2_0_AVL_CSR_NUMBER_OF_SECTORS 32
#define EPCQ_CONTROLLER2_0_AVL_CSR_PAGE_SIZE 256
#define EPCQ_CONTROLLER2_0_AVL_CSR_SECTOR_SIZE 65536
#define EPCQ_CONTROLLER2_0_AVL_CSR_SPAN 64
#define EPCQ_CONTROLLER2_0_AVL_CSR_SUBSECTOR_SIZE 4096
#define EPCQ_CONTROLLER2_0_AVL_CSR_TYPE "altera_epcq_controller2"
#define ALT_MODULE_CLASS_intel_generic_serial_flash_interface_top_0_avl_csr intel_generic_serial_flash_interface_top
#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_BASE 0x00020100
#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_IRQ -1
#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_IRQ_INTERRUPT_CONTROLLER_ID -1
#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_NAME "/dev/intel_generic_serial_flash_interface_top_0_avl_csr"
#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_SPAN 256
#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_CSR_TYPE "intel_generic_serial_flash_interface_top"
/*
* epcq_controller2_0_avl_mem configuration
* intel_generic_serial_flash_interface_top_0_avl_mem configuration
*
*/
#define ALT_MODULE_CLASS_epcq_controller2_0_avl_mem altera_epcq_controller2
#define EPCQ_CONTROLLER2_0_AVL_MEM_BASE 0x800000
#define EPCQ_CONTROLLER2_0_AVL_MEM_FLASH_TYPE "EPCQ16"
#define EPCQ_CONTROLLER2_0_AVL_MEM_IRQ -1
#define EPCQ_CONTROLLER2_0_AVL_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define EPCQ_CONTROLLER2_0_AVL_MEM_IS_EPCS 0
#define EPCQ_CONTROLLER2_0_AVL_MEM_NAME "/dev/epcq_controller2_0_avl_mem"
#define EPCQ_CONTROLLER2_0_AVL_MEM_NUMBER_OF_SECTORS 32
#define EPCQ_CONTROLLER2_0_AVL_MEM_PAGE_SIZE 256
#define EPCQ_CONTROLLER2_0_AVL_MEM_SECTOR_SIZE 65536
#define EPCQ_CONTROLLER2_0_AVL_MEM_SPAN 2097152
#define EPCQ_CONTROLLER2_0_AVL_MEM_SUBSECTOR_SIZE 4096
#define EPCQ_CONTROLLER2_0_AVL_MEM_TYPE "altera_epcq_controller_mod"
#define ALT_MODULE_CLASS_intel_generic_serial_flash_interface_top_0_avl_mem intel_generic_serial_flash_interface_top
#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_MEM_BASE 0x02000000
#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_MEM_IRQ -1
#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_MEM_NAME "/dev/intel_generic_serial_flash_interface_top_0_avl_mem"
#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_MEM_SPAN 2097152
#define INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_MEM_TYPE "intel_generic_serial_flash_interface_top"
/*
@ -279,7 +267,7 @@
*/
#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart
#define JTAG_UART_0_BASE 0x20020
#define JTAG_UART_0_BASE 0x20040
#define JTAG_UART_0_IRQ 1
#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define JTAG_UART_0_NAME "/dev/jtag_uart_0"
@ -416,7 +404,7 @@
#define ALT_MODULE_CLASS_timer_0 altera_avalon_timer
#define TIMER_0_ALWAYS_RUN 0
#define TIMER_0_BASE 0x20000
#define TIMER_0_COUNTER_SIZE 32
#define TIMER_0_COUNTER_SIZE 64
#define TIMER_0_FIXED_PERIOD 0
#define TIMER_0_FREQ 27000000
#define TIMER_0_IRQ 0
@ -428,7 +416,7 @@
#define TIMER_0_PERIOD_UNITS "us"
#define TIMER_0_RESET_OUTPUT 0
#define TIMER_0_SNAPSHOT 1
#define TIMER_0_SPAN 32
#define TIMER_0_SPAN 64
#define TIMER_0_TICKS_PER_SEC 1000000
#define TIMER_0_TIMEOUT_PULSE_OUTPUT 0
#define TIMER_0_TYPE "altera_avalon_timer"

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