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https://github.com/marqs85/ossc
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Preliminary Line5x implementation
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@@ -10,35 +10,49 @@ set_false_path -to {sys:sys_inst|sys_pio_1:pio_1|readdata*}
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### Scanconverter clock constraints ###
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create_clock -period 108MHz -name pclk_hdtv [get_ports PCLK_in]
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create_clock -period 27MHz -name pclk_ldtv_hs_M0 [get_ports PCLK_in] -add
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create_clock -period 20MHz -name pclk_ldtv_hs_M1 [get_ports PCLK_in] -add
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create_clock -period 13.5MHz -name pclk_sdtv [get_ports PCLK_in] -add
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create_clock -period 13.5MHz -name pclk_sdtv_L2 [get_ports PCLK_in] -add
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create_clock -period 27MHz -name pclk_sdtv_L3 [get_ports PCLK_in] -add
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create_clock -period 27MHz -name pclk_sdtv_L4 [get_ports PCLK_in] -add
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create_clock -period 16MHz -name pclk_sdtv_L5 [get_ports PCLK_in] -add
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#derive_pll_clocks
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create_generated_clock -master_clock pclk_sdtv -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name pclk_2x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]}
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create_generated_clock -master_clock pclk_ldtv_hs_M0 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x_M0 {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]}
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create_generated_clock -master_clock pclk_ldtv_hs_M1 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x_M1 {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]} -add
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create_generated_clock -master_clock pclk_ldtv_hs_M1 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name pclk_4x_M1 {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[1]}
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create_generated_clock -master_clock pclk_sdtv_L2 -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name pclk_2x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]}
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create_generated_clock -master_clock pclk_sdtv_L3 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]}
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create_generated_clock -master_clock pclk_sdtv_L4 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name pclk_4x {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[1]}
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create_generated_clock -master_clock pclk_sdtv_L5 -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 5 -duty_cycle 50.00 -name pclk_5x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[1]}
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derive_clock_uncertainty
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# input delay constraints
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set TVP_dmin 0
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set TVP_dmax 1.5
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set critinputs [get_ports {R_in* G_in* B_in* HSYNC_in VSYNC_in FID_in}]
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set_input_delay -clock pclk_sdtv -min 0 $critinputs
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set_input_delay -clock pclk_sdtv -max 1.5 $critinputs
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set_input_delay -clock pclk_hdtv -min 0 $critinputs -add_delay
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set_input_delay -clock pclk_hdtv -max 1.5 $critinputs -add_delay
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set_input_delay -clock pclk_ldtv_hs_M0 -min 0 $critinputs -add_delay
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set_input_delay -clock pclk_ldtv_hs_M0 -max 1.5 $critinputs -add_delay
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set_input_delay -clock pclk_ldtv_hs_M1 -min 0 $critinputs -add_delay
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set_input_delay -clock pclk_ldtv_hs_M1 -max 1.5 $critinputs -add_delay
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set_input_delay -clock pclk_hdtv -min $TVP_dmin $critinputs
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set_input_delay -clock pclk_hdtv -max $TVP_dmax $critinputs
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set_input_delay -clock pclk_sdtv_L2 -min $TVP_dmin $critinputs -add_delay
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set_input_delay -clock pclk_sdtv_L2 -max $TVP_dmax $critinputs -add_delay
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set_input_delay -clock pclk_sdtv_L3 -min $TVP_dmin $critinputs -add_delay
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set_input_delay -clock pclk_sdtv_L3 -max $TVP_dmax $critinputs -add_delay
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set_input_delay -clock pclk_sdtv_L4 -min $TVP_dmin $critinputs -add_delay
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set_input_delay -clock pclk_sdtv_L4 -max $TVP_dmax $critinputs -add_delay
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set_input_delay -clock pclk_sdtv_L5 -min $TVP_dmin $critinputs -add_delay
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set_input_delay -clock pclk_sdtv_L5 -max $TVP_dmax $critinputs -add_delay
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# output delay constraints (TODO: add vsync)
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set IT_Tsu 1.0
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set IT_Th -0.5
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#todo VS
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set critoutputs_hdmi {HDMI_TX_RD* HDMI_TX_GD* HDMI_TX_BD* HDMI_TX_DE HDMI_TX_HS}
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_hdtv 0 $critoutputs_hdmi
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_2x 0 $critoutputs_hdmi -add_delay
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_3x_M0 0 $critoutputs_hdmi -add_delay
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_4x_M1 0 $critoutputs_hdmi -add_delay
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_hdtv -min $IT_Th $critoutputs_hdmi
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_hdtv -max $IT_Tsu $critoutputs_hdmi
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_2x -min $IT_Th $critoutputs_hdmi -add_delay
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_2x -max $IT_Tsu $critoutputs_hdmi -add_delay
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_3x -min $IT_Th $critoutputs_hdmi -add_delay
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_3x -max $IT_Tsu $critoutputs_hdmi -add_delay
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_4x -min $IT_Th $critoutputs_hdmi -add_delay
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_4x -max $IT_Tsu $critoutputs_hdmi -add_delay
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_5x -min $IT_Th $critoutputs_hdmi -add_delay
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set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_5x -max $IT_Tsu $critoutputs_hdmi -add_delay
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set_false_path -to [remove_from_collection [all_outputs] $critoutputs_hdmi]
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@@ -47,19 +61,18 @@ set_false_path -to [remove_from_collection [all_outputs] $critoutputs_hdmi]
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# Set pixel clocks as exclusive clocks
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set_clock_groups -exclusive \
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-group {pclk_hdtv} \
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-group {pclk_sdtv pclk_2x} \
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-group {pclk_ldtv_hs_M0 pclk_3x_M0} \
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-group {pclk_ldtv_hs_M1 pclk_3x_M1 pclk_4x_M1}
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-group {pclk_sdtv_L2 pclk_2x} \
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-group {pclk_sdtv_L3 pclk_3x} \
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-group {pclk_sdtv_L4 pclk_4x} \
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-group {pclk_sdtv_L5 pclk_5x}
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# Treat CPU clock asynchronous to pixel clocks
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set_clock_groups -asynchronous -group {clk27}
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# Filter out impossible output mux combinations
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set clkmuxregs [get_cells {scanconverter:scanconverter_inst|R_out[*] scanconverter:scanconverter_inst|G_out[*] scanconverter:scanconverter_inst|B_out[*] scanconverter:scanconverter_inst|HSYNC_out scanconverter:scanconverter_inst|DATA_enable scanconverter:scanconverter_inst|*_pp1*}]
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set clkmuxregs [get_cells {scanconverter:scanconverter_inst|R_out* scanconverter:scanconverter_inst|G_out* scanconverter:scanconverter_inst|B_out* scanconverter:scanconverter_inst|HSYNC_out* scanconverter:scanconverter_inst|VSYNC_out* scanconverter:scanconverter_inst|DE_out* scanconverter:scanconverter_inst|*_pp1* scanconverter:scanconverter_inst|*_pp2*}]
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set clkmuxnodes [get_pins {scanconverter_inst|linebuf_*|altsyncram_*|auto_generated|ram_*|portbaddr*}]
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set_false_path -from [get_clocks {pclk_ldtv* pclk_sdtv}] -through $clkmuxregs
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set_false_path -from pclk_3x_M1 -through [remove_from_collection $clkmuxregs {scanconverter:scanconverter_inst|DATA_enable_pp1* scanconverter:scanconverter_inst|HSYNC_pp1*}] -to pclk_4x_M1
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set_false_path -from pclk_3x_M1 -through $clkmuxnodes -to pclk_4x_M1
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set_false_path -from [get_clocks {pclk_sdtv_L2 pclk_sdtv_L3 pclk_sdtv_L4 pclk_sdtv_L5}] -through $clkmuxregs
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# Ignore paths from registers which are updated only at the end of vsync
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set_false_path -from [get_cells {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter:scanconverter_inst|lines_*}]
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@@ -71,9 +84,10 @@ set_false_path -from [get_cells {scanconverter:scanconverter_inst|vcnt_* scancon
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set_false_path -to [get_cells {scanconverter:scanconverter_inst|line_out_idx*}]
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# Ignore following clock transfers
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set_false_path -from [get_clocks pclk_2x] -to [get_clocks pclk_sdtv]
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set_false_path -from [get_clocks pclk_3x_M*] -to [get_clocks {pclk_ldtv_hs_M*}]
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set_false_path -from [get_clocks pclk_4x_M1] -to [get_clocks {pclk_ldtv_hs_M1 pclk_3x_M1}]
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set_false_path -from [get_clocks pclk_2x] -to [get_clocks pclk_sdtv_L2]
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set_false_path -from [get_clocks pclk_3x] -to [get_clocks {pclk_sdtv_L3}]
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set_false_path -from [get_clocks pclk_4x] -to [get_clocks {pclk_sdtv_L4}]
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set_false_path -from [get_clocks pclk_5x] -to [get_clocks {pclk_sdtv_L5}]
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### JTAG Signal Constraints ###
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