Improve SD card IO.

ip/i2c_opencores/i2c_master_bit_ctrl.v

@@ -587,7 +587,7 @@ module i2c_master_bit_ctrl(
 	            begin
 	                c_state <= #1 spi_wr_b;
 	                scl_oen <= #1 1'b0; // set SCL low
-	                sda_oen <= #1 1'b1; // keep SDA
+	                sda_oen <= #1 din;  // set SDA
 	                sda_chk <= #1 1'b0; // don't check SDA output
 	            end
 
@@ -595,7 +595,7 @@ module i2c_master_bit_ctrl(
 	            begin
 	                c_state <= #1 spi_wr_c;
 	                scl_oen <= #1 1'b0; // keep SCL low
-	                sda_oen <= #1 din;  // set SDA
+	                sda_oen <= #1 din;  // keep SDA
 	                sda_chk <= #1 1'b0; // don't check SDA output
 	            end
 
@@ -612,7 +612,7 @@ module i2c_master_bit_ctrl(
 	                c_state <= #1 idle;
 	                cmd_ack <= #1 1'b1;
 	                scl_oen <= #1 1'b1; // tri-state SCL
-	                sda_oen <= #1 1'b1; // tri-state SDA
+	                sda_oen <= #1 din;  // keep SDA
 	                sda_chk <= #1 1'b0; // don't check SDA output
 	            end
 

ip/i2c_opencores/i2c_opencores.v

@@ -11,7 +11,7 @@ module i2c_opencores
 	scl_pad_io, sda_pad_io, spi_miso_pad_i
 );
 
-parameter drive_scl_high = 0;
+parameter always_drive_io = 0;
 
 // Common bus signals
 input        wb_clk_i;		// WISHBONE clock
@@ -43,7 +43,7 @@ wire scl_padoen_o;
 
 assign wb_cyc_i = wb_stb_i;
 assign scl_pad_i = scl_pad_io;
-assign scl_pad_io = scl_padoen_o ? (drive_scl_high ? 1'b1 : 1'bZ) : scl_pad_o;
+assign scl_pad_io = scl_padoen_o ? (always_drive_io ? 1'b1 : 1'bZ) : scl_pad_o;
 
 wire sda_pad_i;
 wire sda_pad_o;
@@ -51,7 +51,7 @@ wire sda_pad_io;
 wire sda_padoen_o;
 
 assign sda_pad_i = sda_pad_io;
-assign sda_pad_io = sda_padoen_o ? 1'bZ : sda_pad_o;
+assign sda_pad_io = sda_padoen_o ? (always_drive_io ? 1'b1 : 1'bZ) : sda_pad_o;
 
 // Avalon doesn't have an asynchronous reset
 //  set it to be inactive and just use synchronous reset

ip/i2c_opencores/i2c_opencores_hw.tcl

@@ -59,13 +59,13 @@ add_fileset_file timescale.v VERILOG PATH timescale.v
 # 
 # parameters
 # 
-add_parameter drive_scl_high INTEGER 1
-set_parameter_property drive_scl_high DEFAULT_VALUE 0
-set_parameter_property drive_scl_high DISPLAY_NAME "Drive SCL high instead of tristate"
-set_parameter_property drive_scl_high DISPLAY_HINT boolean
-set_parameter_property drive_scl_high TYPE INTEGER
-set_parameter_property drive_scl_high UNITS None
-set_parameter_property drive_scl_high HDL_PARAMETER true
+add_parameter always_drive_io INTEGER 1
+set_parameter_property always_drive_io DEFAULT_VALUE 0
+set_parameter_property always_drive_io DISPLAY_NAME "Always drive IO lines (no tristate)"
+set_parameter_property always_drive_io DISPLAY_HINT boolean
+set_parameter_property always_drive_io TYPE INTEGER
+set_parameter_property always_drive_io UNITS None
+set_parameter_property always_drive_io HDL_PARAMETER true
 
 # 
 # display items