SD SPI implementation finished

software/sys_controller_bsp/system.h

@@ -4,7 +4,7 @@
  * Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys'
  * SOPC Builder design path: ../../sys.sopcinfo
  *
- * Generated: Sun Oct 16 12:18:06 EEST 2016
+ * Generated: Thu Oct 20 01:24:13 EEST 2016
  */
 
 /*
@@ -150,7 +150,6 @@
 #define __ALTERA_AVALON_JTAG_UART
 #define __ALTERA_AVALON_ONCHIP_MEMORY2
 #define __ALTERA_AVALON_PIO
-#define __ALTERA_AVALON_SPI
 #define __ALTERA_AVALON_TIMER
 #define __ALTERA_EPCQ_CONTROLLER_MOD
 #define __ALTERA_NIOS2_GEN2
@@ -176,19 +175,19 @@
 #define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
 #define ALT_NUM_INTERRUPT_CONTROLLERS 1
 #define ALT_STDERR "/dev/jtag_uart_0"
-#define ALT_STDERR_BASE 0x8210e0
+#define ALT_STDERR_BASE 0x8210d0
 #define ALT_STDERR_DEV jtag_uart_0
 #define ALT_STDERR_IS_JTAG_UART
 #define ALT_STDERR_PRESENT
 #define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
 #define ALT_STDIN "/dev/jtag_uart_0"
-#define ALT_STDIN_BASE 0x8210e0
+#define ALT_STDIN_BASE 0x8210d0
 #define ALT_STDIN_DEV jtag_uart_0
 #define ALT_STDIN_IS_JTAG_UART
 #define ALT_STDIN_PRESENT
 #define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
 #define ALT_STDOUT "/dev/jtag_uart_0"
-#define ALT_STDOUT_BASE 0x8210e0
+#define ALT_STDOUT_BASE 0x8210d0
 #define ALT_STDOUT_DEV jtag_uart_0
 #define ALT_STDOUT_IS_JTAG_UART
 #define ALT_STDOUT_PRESENT
@@ -243,7 +242,7 @@
 
 #define ALT_MAX_FD 32
 #define ALT_SYS_CLK none
-#define ALT_TIMESTAMP_CLK none
+#define ALT_TIMESTAMP_CLK TIMER_0
 
 
 /*
@@ -260,13 +259,27 @@
 #define I2C_OPENCORES_0_TYPE "i2c_opencores"
 
 
+/*
+ * i2c_opencores_1 configuration
+ *
+ */
+
+#define ALT_MODULE_CLASS_i2c_opencores_1 i2c_opencores
+#define I2C_OPENCORES_1_BASE 0x821000
+#define I2C_OPENCORES_1_IRQ 4
+#define I2C_OPENCORES_1_IRQ_INTERRUPT_CONTROLLER_ID 0
+#define I2C_OPENCORES_1_NAME "/dev/i2c_opencores_1"
+#define I2C_OPENCORES_1_SPAN 32
+#define I2C_OPENCORES_1_TYPE "i2c_opencores"
+
+
 /*
  * jtag_uart_0 configuration
  *
  */
 
 #define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart
-#define JTAG_UART_0_BASE 0x8210e0
+#define JTAG_UART_0_BASE 0x8210d0
 #define JTAG_UART_0_IRQ 1
 #define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
 #define JTAG_UART_0_NAME "/dev/jtag_uart_0"
@@ -313,7 +326,7 @@
  */
 
 #define ALT_MODULE_CLASS_pio_0 altera_avalon_pio
-#define PIO_0_BASE 0x8210d0
+#define PIO_0_BASE 0x8210c0
 #define PIO_0_BIT_CLEARING_EDGE_REGISTER 0
 #define PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
 #define PIO_0_CAPTURE 0
@@ -340,7 +353,7 @@
  */
 
 #define ALT_MODULE_CLASS_pio_1 altera_avalon_pio
-#define PIO_1_BASE 0x8210c0
+#define PIO_1_BASE 0x8210b0
 #define PIO_1_BIT_CLEARING_EDGE_REGISTER 0
 #define PIO_1_BIT_MODIFYING_OUTPUT_REGISTER 0
 #define PIO_1_CAPTURE 0
@@ -367,7 +380,7 @@
  */
 
 #define ALT_MODULE_CLASS_pio_2 altera_avalon_pio
-#define PIO_2_BASE 0x8210b0
+#define PIO_2_BASE 0x8210a0
 #define PIO_2_BIT_CLEARING_EDGE_REGISTER 0
 #define PIO_2_BIT_MODIFYING_OUTPUT_REGISTER 0
 #define PIO_2_CAPTURE 0
@@ -394,7 +407,7 @@
  */
 
 #define ALT_MODULE_CLASS_pio_3 altera_avalon_pio
-#define PIO_3_BASE 0x8210a0
+#define PIO_3_BASE 0x821090
 #define PIO_3_BIT_CLEARING_EDGE_REGISTER 0
 #define PIO_3_BIT_MODIFYING_OUTPUT_REGISTER 0
 #define PIO_3_CAPTURE 0
@@ -421,7 +434,7 @@
  */
 
 #define ALT_MODULE_CLASS_pio_4 altera_avalon_pio
-#define PIO_4_BASE 0x821090
+#define PIO_4_BASE 0x821080
 #define PIO_4_BIT_CLEARING_EDGE_REGISTER 0
 #define PIO_4_BIT_MODIFYING_OUTPUT_REGISTER 0
 #define PIO_4_CAPTURE 0
@@ -442,64 +455,6 @@
 #define PIO_4_TYPE "altera_avalon_pio"
 
 
-/*
- * pio_5 configuration
- *
- */
-
-#define ALT_MODULE_CLASS_pio_5 altera_avalon_pio
-#define PIO_5_BASE 0x821080
-#define PIO_5_BIT_CLEARING_EDGE_REGISTER 0
-#define PIO_5_BIT_MODIFYING_OUTPUT_REGISTER 0
-#define PIO_5_CAPTURE 0
-#define PIO_5_DATA_WIDTH 8
-#define PIO_5_DO_TEST_BENCH_WIRING 0
-#define PIO_5_DRIVEN_SIM_VALUE 0
-#define PIO_5_EDGE_TYPE "NONE"
-#define PIO_5_FREQ 27000000
-#define PIO_5_HAS_IN 0
-#define PIO_5_HAS_OUT 1
-#define PIO_5_HAS_TRI 0
-#define PIO_5_IRQ -1
-#define PIO_5_IRQ_INTERRUPT_CONTROLLER_ID -1
-#define PIO_5_IRQ_TYPE "NONE"
-#define PIO_5_NAME "/dev/pio_5"
-#define PIO_5_RESET_VALUE 0
-#define PIO_5_SPAN 16
-#define PIO_5_TYPE "altera_avalon_pio"
-
-
-/*
- * spi_0 configuration
- *
- */
-
-#define ALT_MODULE_CLASS_spi_0 altera_avalon_spi
-#define SPI_0_BASE 0x821000
-#define SPI_0_CLOCKMULT 1
-#define SPI_0_CLOCKPHASE 0
-#define SPI_0_CLOCKPOLARITY 0
-#define SPI_0_CLOCKUNITS "Hz"
-#define SPI_0_DATABITS 8
-#define SPI_0_DATAWIDTH 16
-#define SPI_0_DELAYMULT "1.0E-9"
-#define SPI_0_DELAYUNITS "ns"
-#define SPI_0_EXTRADELAY 0
-#define SPI_0_INSERT_SYNC 0
-#define SPI_0_IRQ 4
-#define SPI_0_IRQ_INTERRUPT_CONTROLLER_ID 0
-#define SPI_0_ISMASTER 1
-#define SPI_0_LSBFIRST 0
-#define SPI_0_NAME "/dev/spi_0"
-#define SPI_0_NUMSLAVES 1
-#define SPI_0_PREFIX "spi_"
-#define SPI_0_SPAN 32
-#define SPI_0_SYNC_REG_DEPTH 2
-#define SPI_0_TARGETCLOCK 13500000u
-#define SPI_0_TARGETSSDELAY "0.0"
-#define SPI_0_TYPE "altera_avalon_spi"
-
-
 /*
  * timer_0 configuration
  *