7 Commits

Author	SHA1	Message	Date
marqs	f55e9a877e	SD SPI implementation finished	2016-10-21 01:19:53 +03:00
marqs	71d60144e8	Timer and SPI added.	2016-10-16 12:53:54 +03:00
marqs	a488422089	* Fix scanline rendering issues ... * Add initial input and SDTV sync glitch filter settings * Modify input initialization logic * Fix debug build warnings	2016-08-14 18:57:50 +03:00
marqs	c8b542b917	* 480p/576p line2x ... * 480i/576i passthrough * alternating scanlines for interlaced material	2016-07-09 23:12:35 +03:00
marqs	6c5f753245	Misc updates ... -optimizations from Borti -more code refactoring -fix build warnings -change scanline mode logic	2016-06-12 23:43:24 +03:00
marqs	f502b2e46c	Release 0.67. ... - Code cleanup - Some project files added - PAL linetriple added - FPGA PLL parameters optimized - Reduced jitter on low video clock sources	2016-03-27 23:09:31 +03:00
marqs	388c464f63	Initial public release (FW 0.64)	2016-02-23 01:03:50 +02:00