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208 Commits 6 Branches 35 Tags 8.6 MiB
8e7236dc00
Commit Graph

51 Commits

Author SHA1 Message Date
marqs
8e7236dc00 timing optimizations 2019-10-10 01:00:48 +03:00
marqs
b22365af20 add timeout to pll_reconfig and update postprocess pipeline diagram 2019-10-07 23:20:44 +03:00
marqs
9d496383c3 optimize clock network 
* replace all clock muxes with a single cycloneive_clkctrl to minimize skew
* use a single dynamically configured PLL to comply with cycloneive_clkctrl
 2019-10-06 23:54:32 +03:00
marqs
d1fd30019f osd_generator: add M9K support to allow larger character array 2019-10-05 11:33:59 +03:00
marqs
a6bdd8cfab free up 1 M9K by modifying altera_jtag_avalon_master 2019-10-03 23:47:59 +03:00
marqs
6266976114 first OSD implementation 2019-10-03 02:03:43 +03:00
marqs
5e0277fb48 add Panasonic hack for improving line count tolerance with line2x 2019-07-01 19:15:57 +03:00
marqs
9e81fb5922 Scanline updates and fixes 
* Enable overlay pattern customization
* Fix non-alternating mode with line4x interlace sources
* Add alternate interval option for pre-linedoubled sources
 2019-03-23 00:09:46 +02:00
marqs
76d69d19bf switch to RV32E 2018-10-30 01:31:40 +02:00
marqs
0905620b4d update qsys+bsp build logic and instructions 2018-10-11 00:04:32 +03:00
marqs
7914a2ee83 clean up and update README 2018-10-08 00:37:42 +03:00
marqs
e8d5097ecb replace nios crcCI with hw_crc32 qsys module 2018-10-07 23:38:26 +03:00
marqs
4676cbd2f0 integrate zero-riscy 2018-10-06 13:19:12 +03:00
marqs
22e49300df fix line2x reverse LPF trigger 2018-04-18 23:14:24 +03:00
marqs
37650ca22b misc improvements 
* add character LCD backlight timeout option
* increase h.mask range
* show accurate (fpga-calculated) timings on infoscreen
 2018-03-28 20:09:40 +03:00
marqs
9ad696dbc3 optimize away one pp stage and unify code formatting 2018-03-12 01:25:23 +02:00
marqs
0ab31b30b4 simplify timing constraints 2018-03-07 09:21:19 +02:00
marqs
bc1b7419f2 pcm1862: add pre-ADC gain setting 2018-03-02 23:11:52 +02:00
paulb-nl
a39888845a Add 32 step grayramp to test pattern 2018-01-20 22:08:10 +01:00
marqs
dd4ffde231 update to Quartus 17.1 2017-12-07 21:35:08 +02:00
marqs
a24d6b0e3a Update latency tester 
* Enable operation with all sources
* Measure strobe length on low-persistence displays
 2017-10-28 12:10:54 +03:00
marqs
1bf279b2a7 Initial latency tester implementation 2017-10-22 22:45:29 +03:00
marqs
75e072d622 Revert some drive strength adjustments to meet timing requirements 2017-10-13 21:03:48 +03:00
marqs
4b21a354b4 Fix and optimize reverse lpf activation 2017-10-12 02:31:19 +03:00
paulb-nl
ac16008076 Add reverse LPF feature 
reverse LPF can be used to mostly reverse the blur on pre 1-CHIP SNES.
For best results use 256x240 optimized mode.
 2017-09-27 22:43:26 +02:00
marqs
9d14cc776e Misc small fixes and improvements 
* Disable 480p scanlines in auto mode
* Remove inoperable 3x/4x processing modes from 1080i list
* Add 640x512 mode to 480p group and limit 480p sampler option to 525-line modes
* Fix occasional pixel repetion issue after HDMI<->DVI TX switch
* Add "Allow upsample2x" option
* Add comments to some unclear sections
 2017-08-10 00:06:35 +03:00
marqs
2cd36cdd37 Fix PCM1862 input selection. 2017-06-12 01:00:34 +03:00
marqs
cabc04b3b0 Add support for v1.6 pcb with PCM1862. 2017-06-05 00:02:01 +03:00
marqs
2aee3294e3 Fix HDTV mode parameters 2017-05-30 21:16:03 +03:00
marqs
d98c23c8c1 Update project files to Quartus 17.0. 2017-05-29 19:15:34 +03:00
marqs
4f36278cb7 Sync processing rewritten and some issues fixed 
* add 480i/576i line3x/4x
* clean up RTL and SDC
* update AVI infoframe properly
* add HDMI IT content option
 2017-05-18 23:36:37 +03:00
marqs
01b5fe20ee Sync and masking improvements 
* detect VSM=1 properly
* increase mask brightness
* add L2 optimized modes
* fix internal vsync alignment
 2017-05-18 23:36:37 +03:00
marqs
2c934c9dd0 Fix line3x 4:3 mode and VGA interlace detection 2017-02-09 23:14:24 +02:00
marqs
6e043ef577 Improve input mode handling 
* New options and better compatibility for Line5x
* Add support for 960i and 1080i
* Make TVP HPLL2x option user-selectable
 2017-02-07 23:04:30 +02:00
marqs
3b19b2843c Preliminary Line5x implementation 2017-01-29 13:02:12 +02:00
marqs
d41c7522a0 Misc updates 
* Fix mask placement and make its brightness adjustable
* Line4x
 2017-01-24 00:18:15 +02:00
marqs
434186d64e Improve lo-res mode processing features 
* workaround for phase shift issue on optimized modes
* add hscale option for 256x240 opt Line3x mode
* distribute video modes to groups and allow passthru for all modes
 2017-01-23 00:56:17 +02:00
marqs
d77c293b70 * Clean up some FPGA code 
* Wrap sampling phase setting
* Enable hal.enable_lightweight_device_driver_api to reduce CPU code size
 2016-12-31 14:18:21 +02:00
marqs
03bf4c2c9a Update to Quartus 16.1. 2016-12-13 20:55:10 +02:00
marqs
d548d53272 Add dedicated SPI mode option to i2c_opencores. 2016-11-05 15:39:36 +02:00
marqs
611c8763c2 Improve SD card IO. 2016-10-27 01:08:23 +03:00
marqs
f55e9a877e SD SPI implementation finished 2016-10-21 01:19:53 +03:00
marqs
71d60144e8 Timer and SPI added. 2016-10-16 12:53:54 +03:00
marqs
9f086828ac Release 0.73 
* Fixed adv. timing tweaker using previous values when updating parameters
* Added "Hsync tolerance" option to fix detection of certain Neo-Geo models
 2016-09-05 20:49:41 +03:00
marqs
2dee0a2eb5 * R/G/B gain/offset controls added 
* misc optimizations
 2016-08-20 15:54:28 +03:00
marqs
827df7930f * L3 optimized mode scanlines fixed 
* Advanced timing tweaker implemented
 2016-08-16 22:45:23 +03:00
marqs
a488422089 * Fix scanline rendering issues 
* Add initial input and SDTV sync glitch filter settings
* Modify input initialization logic
* Fix debug build warnings
 2016-08-14 18:57:50 +03:00
marqs
c8b542b917 * 480p/576p line2x 
* 480i/576i passthrough
* alternating scanlines for interlaced material
 2016-07-09 23:12:35 +03:00
marqs
c83653c880 Release 0.69 
* Improved remote control handling code
* Fixed occasional mode change loop when switching to a non-interlace mode utilizing odd-field sync signal
* Fixed randomly missing blue channel at power-on when using DVI output mode
* Added H-PLL coast options
* Finer tuning range for scanline strength and mask
 2016-04-15 22:05:53 +03:00
marqs
f502b2e46c Release 0.67. 
- Code cleanup
- Some project files added
- PAL linetriple added
- FPGA PLL parameters optimized
- Reduced jitter on low video clock sources
 2016-03-27 23:09:31 +03:00