RomanRom2/ossc
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mirror of https://github.com/marqs85/ossc synced 2026-10-30 19:57:20 +03:00
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203 Commits 8 Branches 38 Tags
b22365af2006b2695ca591e8b4c879baf47df66c
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2 Commits
Author SHA1 Message Date
marqs b22365af20 add timeout to pll_reconfig and update postprocess pipeline diagram 2019-10-07 23:20:44 +03:00
marqs 9d496383c3 optimize clock network 
* replace all clock muxes with a single cycloneive_clkctrl to minimize skew
* use a single dynamically configured PLL to comply with cycloneive_clkctrl
 2019-10-06 23:54:32 +03:00