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3 Commits
Author SHA1 Message Date
marqs 3d5e849fcd update flash imem addr for 2nd firmware 2026-02-05 21:57:51 +02:00
marqs bb4932fc28 update FW image creation instructions 2026-02-02 22:42:13 +02:00
marqs 5a8b914c84 fix multi-sector SD_Write 2026-01-08 00:52:58 +02:00
8 changed files with 15 additions and 10 deletions

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+7 -3
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@@ -111,12 +111,16 @@ cd tools && gcc create_fw_img.c -o create_fw_img
~~~~
where
* \<rbf\> is RBF format bitstream file (typically ../output_files/ossc.rbf)
* \<sw_image\> is SW image binary (typically ../output_files/ossc.rbf)
* \<offset\> is target offset for the SW image binary (typically 0x50000)
* \<sw_image\> is SW image binary (typically ../software/sys_controller/mem_init/flash.bin)
* \<offset\> is relative offset for the SW image binary
* \<version\> is version string (e.g. 1.20)
* \[version_suffix\] is optional max. 8 character suffix name (e.g. "mytest")
The command creates ossc_\<version\>-\<version_suffix\>.bin which can be copied to fw folder of SD card. A secondary FW (identified by specific key in header) gets automatically installed at flash address 0x00080000.
The primary firmware has FPGA bitstream at offset 0x0 and SW image at 0x50000 so the command is typically as follows:
~~~~
./create_fw_img ../output_files/ossc.rbf ../software/sys_controller/mem_init/flash.bin 0x50000 1.21 mytest
~~~~
The command creates ossc_\<version\>-\<version_suffix\>.bin which can be copied to fw folder of SD card. A secondary FW (identified by specific key in header) gets automatically installed at flash base address 0x00080000.
Debugging
--------------------------
+1
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@@ -7,6 +7,7 @@
<width>1</width>
<mode>7</mode>
<sof_data>
<start_address>00080000</start_address>
<user_name>Page_0</user_name>
<page_flags>1</page_flags>
<bit0>
+1 -1
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@@ -377,7 +377,7 @@ sys sys_inst(
.reset_po_reset_n (po_reset_n),
.ibex_0_ndm_ndmreset_o (ndmreset_req),
.ibex_0_ndm_ndmreset_ack_i (ndmreset_ack),
.ibex_0_config_boot_addr_i (32'h02050000),
.ibex_0_config_boot_addr_i (32'h020D0000),
.ibex_0_config_core_sleep_o (),
.master_0_master_reset_reset (jtagm_reset_req),
.i2c_opencores_0_export_scl_pad_io (scl),
+1 -1
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@@ -1,6 +1,6 @@
# flash details
set flash_base 0x02000000
set flash_imem_offset 0x00050000
set flash_imem_offset 0x000D0000
set flash_imem_base [format 0x%.8x [expr $flash_base + $flash_imem_offset]]
set flash_secsize 65536
+2 -2
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@@ -1150,8 +1150,8 @@ src/userdata_sjis.c: src/userdata.c
iconv -f UTF-8 -t SHIFT-JIS src/userdata.c > src/userdata_sjis.c
mem_init/flash.hex: sys_controller.elf
$(RV_OBJCOPY) --change-addresses -0x02050000 -O binary --gap-fill 0 $< mem_init/flash.bin
$(RV_OBJCOPY) --change-addresses -0x02050000 -O ihex --gap-fill 0 $< mem_init/flash.hex
$(RV_OBJCOPY) --change-addresses -0x020D0000 -O binary --gap-fill 0 $< mem_init/flash.bin
$(RV_OBJCOPY) --change-addresses -0x020D0000 -O ihex --gap-fill 0 $< mem_init/flash.hex
mkdir -p mem_init/chunks
rm -f mem_init/chunks/*
split -d -b 1024 -a 4 mem_init/flash.bin mem_init/chunks/flash.
@@ -99,7 +99,7 @@ DRESULT disk_write (
return STA_NOINIT;
for (i=0; i<count; i++) {
res = SD_Write(&sdcard_dev, (void*)&buff[i*SD_BLK_SIZE], sector);
res = SD_Write(&sdcard_dev, (void*)&buff[i*SD_BLK_SIZE], sector+i);
if (res != SD_OK)
return RES_PARERR;
}
+1 -1
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@@ -8,7 +8,7 @@ __DYNAMIC = 0;
Last 16 flash sectors reserved for userdata (16x 64KB). */
MEMORY
{
flash_imem : ORIGIN = 0x02050000, LENGTH = 196608
flash_imem : ORIGIN = 0x020D0000, LENGTH = 196608
dataram : ORIGIN = 0x00010000, LENGTH = 16384
}
+1 -1
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@@ -161,7 +161,7 @@ int main(int argc, char **argv)
return -1;
}
snprintf(hdr.fw_key, FW_KEY_SIZE+1, "OSSC");
snprintf(hdr.fw_key, FW_KEY_SIZE+1, "OSS2");
hdr.version_major = (uint8_t)fw_version_major;
hdr.version_minor = (uint8_t)fw_version_minor;
snprintf(hdr.version_suffix, FW_SUFFIX_MAX_SIZE, legacy_mode ? ((argc == 4) ? argv[3] : "") : ((argc == 6) ? argv[5] : ""));