1250 lines
45 KiB
Plaintext
1250 lines
45 KiB
Plaintext
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(pinDes (text (pt 2.58 -8.91) "7" (textStyleRef "(DefaultTTF)") (isFlipped True) (justify Left) (extent 2.1828 3.7703) )
|
|
)
|
|
(pinName (text (pt 8.83 -10.16) "A2" (textStyleRef "(DefaultTTF)") (isFlipped True) (justify Center) (extent 4.03488 3.7703) )
|
|
)
|
|
(defaultPinDes "8")
|
|
)
|
|
(pin (pinNum 10) (pt 5.08 -20.32) (rotation 180.0) (isFlipped True) (pinLength 5.08)
|
|
(pinDisplay (dispPinName True) )
|
|
(pinDes (text (pt 2.58 -19.07) "10" (textStyleRef "(DefaultTTF)") (isFlipped True) (justify Left) (extent 3.7703 3.7703) )
|
|
)
|
|
(pinName (text (pt 8.83 -20.32) "A4" (textStyleRef "(DefaultTTF)") (isFlipped True) (justify Center) (extent 4.03488 3.7703) )
|
|
)
|
|
(defaultPinDes "10")
|
|
)
|
|
(pin (pinNum 11) (pt 5.08 -25.4) (rotation 180.0) (isFlipped True) (pinLength 5.08)
|
|
(pinDisplay (dispPinName True) )
|
|
(pinDes (text (pt 2.58 -24.15) "11" (textStyleRef "(DefaultTTF)") (isFlipped True) (justify Left) (extent 3.7703 3.7703) )
|
|
)
|
|
(pinName (text (pt 8.83 -25.4) "A5" (textStyleRef "(DefaultTTF)") (isFlipped True) (justify Center) (extent 4.03488 3.7703) )
|
|
)
|
|
(defaultPinDes "11")
|
|
)
|
|
(line (pt 5.08 5.08) (pt 5.08 -81.28) (width 0.1) )
|
|
(line (pt 12.7 5.08) (pt 12.7 -81.28) (width 0.1) )
|
|
(line (pt 5.08 -81.28) (pt 30.48 -81.28) (width 0.1) )
|
|
(line (pt 5.08 -50.8) (pt 12.7 -50.8) (width 0.1) )
|
|
(text (pt 17.78 -5.08) "1Mx1" (textStyleRef "(DefaultTTF)") (justify Center) (extent 7.47447 3.7703) )
|
|
(text (pt 17.78 0.0) "DRAM" (textStyleRef "(DefaultTTF)") (justify Center) (extent 8.79738 3.7703) )
|
|
(line (pt 5.08 -71.12) (pt 12.7 -71.12) (width 0.1) )
|
|
(line (pt 22.86 -71.12) (pt 30.48 -71.12) (width 0.1) )
|
|
(line (pt 5.08 5.08) (pt 30.48 5.08) (width 0.1) )
|
|
(line (pt 22.86 -81.28) (pt 22.86 5.08) (width 0.1) )
|
|
(line (pt 30.48 -81.28) (pt 30.48 5.08) (width 0.1) )
|
|
(attr "Value" "" (pt 17.78 -83.82) (isVisible True) (justify Center) (textStyleRef "(DefaultTTF)") )
|
|
(attr "RefDes" "" (pt 17.78 7.62) (isVisible True) (justify Center) (textStyleRef "(DefaultTTF)") )
|
|
(attr "Type" "" (pt 17.5 -100.0) (justify Center) (textStyleRef "(DefaultTTF)") )
|
|
)
|
|
(symbolDef "GND_1"
|
|
(originalName "GND")
|
|
(pin (pinNum 1) (pt 0.0 -2.5) (rotation 90.0) (isFlipped True) (pinLength 2.5)
|
|
(pinDisplay (dispPinDes False) )
|
|
(pinDes (text (pt 0.0 -0.849) "1" (textStyleRef "(DefaultTTF)") (rotation 90.0) (isFlipped True) (extent 2.1828 3.7703) )
|
|
)
|
|
(pinName (text (pt 0.0 -3.008) "GND" (textStyleRef "(DefaultTTF)") (rotation 90.0) (isFlipped True) (justify Right) (extent 6.68072 3.7703) )
|
|
)
|
|
(defaultPinDes "1")
|
|
)
|
|
(line (pt -2.5 -2.5) (pt 2.5 -2.5) (width 0.1) )
|
|
(attr "Type" "" (pt -3.75 -7.5) (textStyleRef "(DefaultTTF)") )
|
|
(attr "RefDes" "" (pt 0.0 3.75) (justify Center) (textStyleRef "(DefaultTTF)") )
|
|
)
|
|
(compDef "SIMM-30-EDGE_1"
|
|
(originalName "SIMM-30-EDGE")
|
|
(compHeader
|
|
(sourceLibrary "R2-CONNECTORS.LIB")
|
|
(numPins 30)
|
|
(numParts 1)
|
|
(alts (ieeeAlt False) (deMorganAlt False))
|
|
(refDesPrefix "X")
|
|
(numType Numeric)
|
|
)
|
|
(compPin "1" (pinName "VCC") (partNum 1) (symPinNum 1) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "2" (pinName "~CAS") (partNum 1) (symPinNum 2) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "3" (pinName "D0") (partNum 1) (symPinNum 3) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "4" (pinName "A0") (partNum 1) (symPinNum 4) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "5" (pinName "A1") (partNum 1) (symPinNum 5) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "6" (pinName "D1") (partNum 1) (symPinNum 6) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "7" (pinName "A2") (partNum 1) (symPinNum 7) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "8" (pinName "A3") (partNum 1) (symPinNum 8) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "9" (pinName "GND") (partNum 1) (symPinNum 9) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "10" (pinName "D2") (partNum 1) (symPinNum 10) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "11" (pinName "A4") (partNum 1) (symPinNum 11) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "12" (pinName "A5") (partNum 1) (symPinNum 12) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "13" (pinName "D3") (partNum 1) (symPinNum 13) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "14" (pinName "A6") (partNum 1) (symPinNum 14) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "15" (pinName "A7") (partNum 1) (symPinNum 15) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "16" (pinName "D4") (partNum 1) (symPinNum 16) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "17" (pinName "A8") (partNum 1) (symPinNum 17) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "18" (pinName "A9") (partNum 1) (symPinNum 18) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "19" (pinName "A10") (partNum 1) (symPinNum 19) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "20" (pinName "D5") (partNum 1) (symPinNum 20) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "21" (pinName "~WE") (partNum 1) (symPinNum 21) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "22" (pinName "GND") (partNum 1) (symPinNum 22) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "23" (pinName "D6") (partNum 1) (symPinNum 23) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "24" (pinName "N.C.") (partNum 1) (symPinNum 24) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "25" (pinName "D7") (partNum 1) (symPinNum 25) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "26" (pinName "P") (partNum 1) (symPinNum 26) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "27" (pinName "~RAS") (partNum 1) (symPinNum 27) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "28" (pinName "~PCAS") (partNum 1) (symPinNum 28) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "29" (pinName "D") (partNum 1) (symPinNum 29) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(compPin "30" (pinName "VCC") (partNum 1) (symPinNum 30) (gateEq 0) (pinEq 0) (pinType Passive) )
|
|
(attachedSymbol (partNum 1) (altType Normal) (symbolName "SIMM-30-EDGE") )
|
|
(attachedPattern (patternNum 1) (patternName "SIMM-30")
|
|
(numPads 32)
|
|
(padPinMap
|
|
(padNum 1) (compPinRef "1")
|
|
(padNum 2) (compPinRef "2")
|
|
(padNum 3) (compPinRef "3")
|
|
(padNum 4) (compPinRef "4")
|
|
(padNum 5) (compPinRef "5")
|
|
(padNum 6) (compPinRef "6")
|
|
(padNum 7) (compPinRef "7")
|
|
(padNum 8) (compPinRef "8")
|
|
(padNum 9) (compPinRef "9")
|
|
(padNum 10) (compPinRef "10")
|
|
(padNum 11) (compPinRef "11")
|
|
(padNum 12) (compPinRef "12")
|
|
(padNum 13) (compPinRef "13")
|
|
(padNum 14) (compPinRef "14")
|
|
(padNum 15) (compPinRef "15")
|
|
(padNum 16) (compPinRef "16")
|
|
(padNum 17) (compPinRef "17")
|
|
(padNum 18) (compPinRef "18")
|
|
(padNum 19) (compPinRef "19")
|
|
(padNum 20) (compPinRef "20")
|
|
(padNum 21) (compPinRef "21")
|
|
(padNum 22) (compPinRef "22")
|
|
(padNum 23) (compPinRef "23")
|
|
(padNum 24) (compPinRef "24")
|
|
(padNum 25) (compPinRef "25")
|
|
(padNum 26) (compPinRef "26")
|
|
(padNum 27) (compPinRef "27")
|
|
(padNum 28) (compPinRef "28")
|
|
(padNum 29) (compPinRef "29")
|
|
(padNum 30) (compPinRef "30")
|
|
)
|
|
)
|
|
)
|
|
(compDef "GND_1"
|
|
(originalName "GND")
|
|
(compHeader
|
|
(sourceLibrary "R2-PASSIVE.LIB")
|
|
(compType Power)
|
|
(numPins 1)
|
|
(numParts 1)
|
|
(alts (ieeeAlt False) (deMorganAlt False))
|
|
(refDesPrefix "PWR")
|
|
(numType Numeric)
|
|
)
|
|
(compPin "1" (pinName "GND") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Power) )
|
|
(attachedSymbol (partNum 1) (altType Normal) (symbolName "GND") )
|
|
)
|
|
(compDef "DRAM-1MX1-DIP_1"
|
|
(originalName "DRAM-1MX1-DIP")
|
|
(compHeader
|
|
(sourceLibrary "R2-IC.LIB")
|
|
(numPins 18)
|
|
(numParts 1)
|
|
(alts (ieeeAlt False) (deMorganAlt False))
|
|
(refDesPrefix "DD")
|
|
(numType Numeric)
|
|
)
|
|
(compPin "1" (pinName "D") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) )
|
|
(compPin "2" (pinName "~W") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) )
|
|
(compPin "3" (pinName "~RAS") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) )
|
|
(compPin "4" (pinName "TF") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) )
|
|
(compPin "5" (pinName "A0") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) )
|
|
(compPin "6" (pinName "A1") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) )
|
|
(compPin "7" (pinName "A2") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) )
|
|
(compPin "8" (pinName "A3") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) )
|
|
(compPin "9" (pinName "VCC") (partNum 0) (symPinNum 0) (gateEq 0) (pinEq 0) (pinType Power) )
|
|
(compPin "10" (pinName "A4") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) )
|
|
(compPin "11" (pinName "A5") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) )
|
|
(compPin "12" (pinName "A6") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) )
|
|
(compPin "13" (pinName "A7") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) )
|
|
(compPin "14" (pinName "A8") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) )
|
|
(compPin "15" (pinName "A9") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) )
|
|
(compPin "16" (pinName "~CAS") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) )
|
|
(compPin "17" (pinName "Q") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Output) )
|
|
(compPin "18" (pinName "GND") (partNum 0) (symPinNum 0) (gateEq 0) (pinEq 0) (pinType Power) )
|
|
(attachedSymbol (partNum 1) (altType Normal) (symbolName "DRAM-1MX1") )
|
|
(attachedPattern (patternNum 1) (patternName "DIP-18")
|
|
(numPads 18)
|
|
(padPinMap
|
|
(padNum 1) (compPinRef "1")
|
|
(padNum 2) (compPinRef "2")
|
|
(padNum 3) (compPinRef "3")
|
|
(padNum 4) (compPinRef "4")
|
|
(padNum 5) (compPinRef "5")
|
|
(padNum 6) (compPinRef "6")
|
|
(padNum 7) (compPinRef "7")
|
|
(padNum 8) (compPinRef "8")
|
|
(padNum 9) (compPinRef "9")
|
|
(padNum 10) (compPinRef "10")
|
|
(padNum 11) (compPinRef "11")
|
|
(padNum 12) (compPinRef "12")
|
|
(padNum 13) (compPinRef "13")
|
|
(padNum 14) (compPinRef "14")
|
|
(padNum 15) (compPinRef "15")
|
|
(padNum 16) (compPinRef "16")
|
|
(padNum 17) (compPinRef "17")
|
|
(padNum 18) (compPinRef "18")
|
|
)
|
|
)
|
|
)
|
|
)
|
|
|
|
(netlist "Netlist_1"
|
|
(compInst "X1"
|
|
(compRef "SIMM-30-EDGE_1")
|
|
(originalName "SIMM-30-EDGE")
|
|
(compValue "SIMM-30-EDGE")
|
|
(patternName "SIMM-30")
|
|
)
|
|
(compInst "DD1"
|
|
(compRef "DRAM-1MX1-DIP_1")
|
|
(originalName "DRAM-1MX1-DIP")
|
|
(compValue "TC511000")
|
|
(patternName "DIP-18")
|
|
)
|
|
(compInst "DD2"
|
|
(compRef "DRAM-1MX1-DIP_1")
|
|
(originalName "DRAM-1MX1-DIP")
|
|
(compValue "TC511000")
|
|
(patternName "DIP-18")
|
|
)
|
|
(compInst "DD3"
|
|
(compRef "DRAM-1MX1-DIP_1")
|
|
(originalName "DRAM-1MX1-DIP")
|
|
(compValue "TC511000")
|
|
(patternName "DIP-18")
|
|
)
|
|
(compInst "DD4"
|
|
(compRef "DRAM-1MX1-DIP_1")
|
|
(originalName "DRAM-1MX1-DIP")
|
|
(compValue "TC511000")
|
|
(patternName "DIP-18")
|
|
)
|
|
(compInst "DD5"
|
|
(compRef "DRAM-1MX1-DIP_1")
|
|
(originalName "DRAM-1MX1-DIP")
|
|
(compValue "TC511000")
|
|
(patternName "DIP-18")
|
|
)
|
|
(compInst "DD6"
|
|
(compRef "DRAM-1MX1-DIP_1")
|
|
(originalName "DRAM-1MX1-DIP")
|
|
(compValue "TC511000")
|
|
(patternName "DIP-18")
|
|
)
|
|
(compInst "DD7"
|
|
(compRef "DRAM-1MX1-DIP_1")
|
|
(originalName "DRAM-1MX1-DIP")
|
|
(compValue "TC511000")
|
|
(patternName "DIP-18")
|
|
)
|
|
(compInst "DD8"
|
|
(compRef "DRAM-1MX1-DIP_1")
|
|
(originalName "DRAM-1MX1-DIP")
|
|
(compValue "TC511000")
|
|
(patternName "DIP-18")
|
|
)
|
|
(net "VCC"
|
|
(node "X1" "30")
|
|
(node "X1" "1")
|
|
(node "DD4" "9")
|
|
(node "DD3" "9")
|
|
(node "DD2" "9")
|
|
(node "DD1" "9")
|
|
(node "DD7" "9")
|
|
(node "DD6" "9")
|
|
(node "DD5" "9")
|
|
(node "DD8" "9")
|
|
)
|
|
(net "GND"
|
|
(node "X1" "9")
|
|
(node "X1" "22")
|
|
(node "DD4" "4")
|
|
(node "DD3" "4")
|
|
(node "DD2" "4")
|
|
(node "DD1" "4")
|
|
(node "DD5" "4")
|
|
(node "DD6" "4")
|
|
(node "DD7" "4")
|
|
(node "DD8" "4")
|
|
(node "DD4" "18")
|
|
(node "DD3" "18")
|
|
(node "DD2" "18")
|
|
(node "DD1" "18")
|
|
(node "DD7" "18")
|
|
(node "DD6" "18")
|
|
(node "DD5" "18")
|
|
(node "DD8" "18")
|
|
)
|
|
(net "A1"
|
|
(node "X1" "5")
|
|
(node "DD4" "6")
|
|
(node "DD3" "6")
|
|
(node "DD2" "6")
|
|
(node "DD1" "6")
|
|
(node "DD5" "6")
|
|
(node "DD6" "6")
|
|
(node "DD7" "6")
|
|
(node "DD8" "6")
|
|
)
|
|
(net "A2"
|
|
(node "X1" "7")
|
|
(node "DD4" "7")
|
|
(node "DD3" "7")
|
|
(node "DD2" "7")
|
|
(node "DD1" "7")
|
|
(node "DD5" "7")
|
|
(node "DD6" "7")
|
|
(node "DD7" "7")
|
|
(node "DD8" "7")
|
|
)
|
|
(net "A3"
|
|
(node "X1" "8")
|
|
(node "DD4" "8")
|
|
(node "DD3" "8")
|
|
(node "DD2" "8")
|
|
(node "DD1" "8")
|
|
(node "DD5" "8")
|
|
(node "DD6" "8")
|
|
(node "DD7" "8")
|
|
(node "DD8" "8")
|
|
)
|
|
(net "A4"
|
|
(node "X1" "11")
|
|
(node "DD4" "10")
|
|
(node "DD3" "10")
|
|
(node "DD2" "10")
|
|
(node "DD1" "10")
|
|
(node "DD5" "10")
|
|
(node "DD6" "10")
|
|
(node "DD7" "10")
|
|
(node "DD8" "10")
|
|
)
|
|
(net "A5"
|
|
(node "X1" "12")
|
|
(node "DD4" "11")
|
|
(node "DD3" "11")
|
|
(node "DD2" "11")
|
|
(node "DD1" "11")
|
|
(node "DD5" "11")
|
|
(node "DD6" "11")
|
|
(node "DD7" "11")
|
|
(node "DD8" "11")
|
|
)
|
|
(net "A6"
|
|
(node "X1" "14")
|
|
(node "DD4" "12")
|
|
(node "DD3" "12")
|
|
(node "DD2" "12")
|
|
(node "DD1" "12")
|
|
(node "DD5" "12")
|
|
(node "DD6" "12")
|
|
(node "DD7" "12")
|
|
(node "DD8" "12")
|
|
)
|
|
(net "A7"
|
|
(node "X1" "15")
|
|
(node "DD4" "13")
|
|
(node "DD3" "13")
|
|
(node "DD2" "13")
|
|
(node "DD1" "13")
|
|
(node "DD5" "13")
|
|
(node "DD6" "13")
|
|
(node "DD7" "13")
|
|
(node "DD8" "13")
|
|
)
|
|
(net "A8"
|
|
(node "X1" "17")
|
|
(node "DD4" "14")
|
|
(node "DD3" "14")
|
|
(node "DD2" "14")
|
|
(node "DD1" "14")
|
|
(node "DD5" "14")
|
|
(node "DD6" "14")
|
|
(node "DD7" "14")
|
|
(node "DD8" "14")
|
|
)
|
|
(net "~RAS"
|
|
(node "X1" "27")
|
|
(node "DD4" "3")
|
|
(node "DD3" "3")
|
|
(node "DD2" "3")
|
|
(node "DD1" "3")
|
|
(node "DD5" "3")
|
|
(node "DD6" "3")
|
|
(node "DD7" "3")
|
|
(node "DD8" "3")
|
|
)
|
|
(net "~CAS"
|
|
(node "X1" "2")
|
|
(node "DD4" "16")
|
|
(node "DD3" "16")
|
|
(node "DD2" "16")
|
|
(node "DD1" "16")
|
|
(node "DD5" "16")
|
|
(node "DD6" "16")
|
|
(node "DD7" "16")
|
|
(node "DD8" "16")
|
|
)
|
|
(net "~WE"
|
|
(node "X1" "21")
|
|
(node "DD4" "2")
|
|
(node "DD3" "2")
|
|
(node "DD2" "2")
|
|
(node "DD1" "2")
|
|
(node "DD5" "2")
|
|
(node "DD6" "2")
|
|
(node "DD7" "2")
|
|
(node "DD8" "2")
|
|
)
|
|
(net "A9"
|
|
(node "X1" "18")
|
|
(node "DD4" "15")
|
|
(node "DD3" "15")
|
|
(node "DD2" "15")
|
|
(node "DD1" "15")
|
|
(node "DD5" "15")
|
|
(node "DD6" "15")
|
|
(node "DD7" "15")
|
|
(node "DD8" "15")
|
|
)
|
|
(net "A0"
|
|
(node "X1" "4")
|
|
(node "DD4" "5")
|
|
(node "DD3" "5")
|
|
(node "DD2" "5")
|
|
(node "DD1" "5")
|
|
(node "DD5" "5")
|
|
(node "DD6" "5")
|
|
(node "DD7" "5")
|
|
(node "DD8" "5")
|
|
)
|
|
(net "DQ1"
|
|
(node "X1" "6")
|
|
(node "DD2" "17")
|
|
(node "DD2" "1")
|
|
)
|
|
(net "DQ5"
|
|
(node "X1" "20")
|
|
(node "DD6" "17")
|
|
(node "DD6" "1")
|
|
)
|
|
(net "DQ6"
|
|
(node "X1" "23")
|
|
(node "DD7" "17")
|
|
(node "DD7" "1")
|
|
)
|
|
(net "DQ7"
|
|
(node "X1" "25")
|
|
(node "DD8" "17")
|
|
(node "DD8" "1")
|
|
)
|
|
(net "DQ4"
|
|
(node "X1" "16")
|
|
(node "DD5" "17")
|
|
(node "DD5" "1")
|
|
)
|
|
(net "DQ3"
|
|
(node "X1" "13")
|
|
(node "DD4" "17")
|
|
(node "DD4" "1")
|
|
)
|
|
(net "DQ0"
|
|
(node "X1" "3")
|
|
(node "DD1" "17")
|
|
(node "DD1" "1")
|
|
)
|
|
(net "DQ2"
|
|
(node "X1" "10")
|
|
(node "DD3" "17")
|
|
(node "DD3" "1")
|
|
)
|
|
)
|
|
|