init repo

README.md

@@ -0,0 +1,56 @@
+# Sprinter 97
+
+## Прототип
+
+Начало эпохи спринтера было положено в 1995-1996 годах. До наших дней дошла одна единственная фотография прототипа.
+
+<img src="photos/sp_proto.jpg" width="600" /><br>
+
+Возможно именно это было представлено на фестивале [Enlight'96](https://www.enlight.ru/enlight/) в Санкт-Петербурге, но это доподлинно неизвестно. К сожалению, в фотоотчетах Enlight нет ни одной фотографии, хоть как-то свидельствующих о том, что Спринтер там вообще был. Остается только на правдивость статьи в журнале [ZX-News #32](https://zxpress.ru/article.php?id=2923):
+
+```
+Первое знакомство "пишущих" людей - кодеров и мьюзикмейкеров (извините за такую англификацию :) с компьютером Peters'ов произошло в августе прошлого года, когда в Санкт-Петербурге проходило всем известное мероприятие Enlight-96. Тогда был представлен Scorpion'оподобный компьютер, тогда у него был реализован лишь один режим расширенной графики.
+```
+
+## Ранняя версия 1997 года
+
+<img src="photos/sp97_top.jpg" width="300" />&nbsp;&nbsp;<img src="photos/sp97_bot.jpg" width="300" /><br>
+
+Ни одного живого экземпляра на сегодняшний день не было обнаружено, однако печатные платы очень редко еще встречаются в продаже. 
+Это настолько редкое и удивительное явление, что на момент создания [SprinterTeam сообщества](https://t.me/zx_sprinter) в 2020 году только один раз за 5 лет эта плата живьем [появилась](https://zx-pk.com/forum/viewtopic.php?f=4&t=24329) в продаже. Однако сканы этой платы уже были доступны в архивах.
+
+Плата очень сильно отличается от классических версий. Видео модуль состоит из дополнительных микросхем, возможно буферов типа 555АП6. 
+Расположение периферийной ПЛИС Altera MAX прямо возле процессора, слева от разъема simm модуля памяти.
+
+Схемы нет. Ни в сканах, ни в ФИДО переписках, ни в упоминаниях. Возможно её еще и не существовало, а появилась она начиная с классической версии. 
+Печатной платы в файлах каких либо КАДах так же не обнаружено.
+
+## Классическая версия 1998 года
+
+Наибольшее распространение получила плата с небольшим количеством навесных исправлений.
+
+<img src="photos/sp98_top.jpg" width="300" />&nbsp;&nbsp;<img src="photos/sp98_bot.jpg" width="300" />&nbsp;&nbsp;<img src="photos/sp98_mont.jpg" width="300" /><br>
+
+Хоть эти фотографии и называются sp97 во всех [мастер-архивах](https://winglion.sprinter.ru/), это все же больше похоже именно на версию 1998 года. Это так же подтверждает файл sp98_mont.bmp из тех же архивов. На этой монтажке указаны все доработки, которые требуется сделать на классической плате. А так как название "Sprinter 97" к этому времени уже закрепилось за этим компьютером, то и файлы именовались так же. Именно эту версию все еще можно встретить на барахолках.
+
+Схема была отрисована в OrCAD 2.10, там же была разработана и плата. Однако оркадовского файла схемы не сохранилось, а картинка со схемой, опубликованная авторами еще во времена ФИДО, получилась крайне низкого разрешения, что породило массу шуток (Nothing to see!). А возможно это было сделано Иваном Мак намеренно, что бы не отдавать общественности схему своего детища.
+
+<img src="pcb/sp97-sch-v1.jpg" width="600" /><br>
+
+Попытка применить современные нейронные сети для восстановления данных не улучшила ситуацию. К сожалению, можно констатировать что схема утеряна навсегда, нужно отрисовывать всё заново.
+
+## Версия 1999 года
+
+В [мастер-архивах](https://winglion.sprinter.ru/) есть файл SPRINT05.PCB - это файл печатной платы, которая выполнена в старом OrCAD 2.10 еще для MS-DOS. Открыть этот файл и что-либо сделать с этим файлом в наше время не так просто. Можно перерыть весь Интернет и все равно не найти нужную версию OrCAD. Вроде бы версия 4.40 должна была открыть файл, но она не смогла, чем окончательно запутала, чем же вообще этот файл открывать. 
+
+<img src="photos/orcad440.jpg" width="300" />&nbsp;&nbsp;<img src="photos/orcad440of.jpg" width="300" /><br>
+
+В [какой-то момент](https://t.me/zx_sprinter/237164) было принято решение просто разобрать формат этого файла путем реверс-инжиниринга и написать конвертор в более современные CAD системы. Можно отследить все этапы реверса по телеграм чату, на странице Sprinter Reverse Team [создан раздел](https://reverse.sprinter.ru/orcad210) с подробным разбором формата и онлайн парсером. 
+
+Используя результаты работы парсера теперь необходимо сгенерировать файл печатной платы для более современных КАД систем. Был выбран формат p-cad ascii format 7.5, который понимает и множество других программ. Генератор выдал результат, который потом без проблем прочитался современным Altium Designer v21.
+
+<img src="pcb/parsed/sprint05_pcad_fixed_top.png" width="300" />&nbsp;&nbsp;<img src="pcb/parsed/sprint05_pcad_fixed_bot.png" width="300" />&nbsp;&nbsp;<img src="photos/altium.jpg" width="300" /><br>
+
+Похоже, что это плата одна из самых последних версий, от 18 августа 1999 года и скорее всего никогда не производилась. На плате видны изменения, они касаются навесных исправлений, которые делались для классической платы 1998 года.
+
+Таким образом получена точная конверсия печатной платы из старого OrCAD формата в современный и теперь можно попробовать воссоздать Sprinter 97 в железе, как это было в оригинале.

fw/protect/protect05.dpr

@@ -0,0 +1,163 @@
+program protect05;
+{$R-}
+{$APPTYPE CONSOLE}
+
+uses
+  Classes,
+  SysUtils;
+
+function GetFileSize(const FileName: String): Cardinal;
+var
+  AFile: File of Byte;
+begin
+  AssignFile(AFile, FileName);
+  Reset(AFile);
+  try
+    Result := System.FileSize(AFile);
+  finally
+    CloseFile(AFile);
+  end;
+end;
+procedure help;
+begin
+  writeln('Usage:');
+  writeln('       protect05.exe <INPUT FILE>');
+  writeln;
+end;
+function bit(const aValue: Cardinal; const BitPos: Byte): byte;
+begin
+  if ((aValue and (1 shl BitPos)) <> 0) then
+    result:= 1
+  else
+    result:= 0;
+end;
+
+const
+  MAX_BUF_SIZE = 1024 * 15;
+
+var
+  data_len: longint;
+  o_file_name, i_file_name: string;
+  o_file, i_file: file of byte;
+  b,i, readed: longint;
+  buf_in, buf_out: array of byte;
+  CODE, D, D0_in, D0_out, todo: byte;
+  unprotected: boolean;
+
+begin
+  writeln('PROTECT05: Sprinter-97 FW bitstream protector/decoder');
+  writeln('Copyright (c) 2024 Sprinter Team');
+
+  // check incoming values
+  if ParamCount < 1 then
+  begin
+    help;
+    exit;
+  end;
+
+  i_file_name:= ParamStr(1);
+  if trim(i_file_name) = '' then
+  begin
+    writeln('ERROR: input file name is not specified');
+    exit;
+  end;
+
+  // check buffer size
+  data_len:= GetFileSize(i_file_name);
+  if (data_len > MAX_BUF_SIZE) then
+  begin
+    writeln('ERROR: DATA_LENGTH='+inttostr(data_len)+', MAX_BUF_SIZE='+inttostr(MAX_BUF_SIZE));
+    exit;
+  end;
+
+  // create buffers
+  SetLength(buf_in, MAX_BUF_SIZE);
+  FillChar(buf_in[0], length(buf_in), 0);
+
+  SetLength(buf_out, MAX_BUF_SIZE);
+  FillChar(buf_out[0], length(buf_out), 0);
+
+  // load src file
+{$I-}
+  FileMode:= fmOpenRead;
+  AssignFile(i_file, i_file_name);
+  reset(i_file);
+  seek(i_file, 0);
+  BlockRead(i_file, buf_in[0], length(buf_in), readed);
+  CloseFile(i_file);
+{$I+}
+  i:= IOResult;
+  if (i > 0) then
+  begin
+    writeln('ERROR: IOResult='+inttostr(i)+' during loading input file. Readed '+inttostr(readed));
+    exit;
+  end;
+  writeln('readed '+inttostr(readed)+' bytes');
+
+  data_len:= readed;
+  unprotected:= false;
+  if (buf_in[0] = $FF) and (buf_in[1] = $FF) and (buf_in[2] = $62) and (buf_in[3] = $7B) then
+    unprotected:= true;
+
+
+  // protect / unprotect
+  CODE:= 0;
+
+  if unprotected then
+    writeln('protecting ...')
+  else
+    writeln('decoding ...');
+
+  for b:= 0 to data_len-1 do
+  begin
+    D:= buf_in[b];
+
+    for i:= 0 to 7 do
+    begin
+      D0_in:= bit(D, i);
+
+      D0_out:= bit(CODE,4) xor D0_in;
+      buf_out[b]:= buf_out[b] or (D0_out shl i);
+
+      if unprotected then
+        todo:= D0_in // protect
+      else
+        todo:= D0_out; // unprotect
+
+      CODE:= (CODE shl 1) or (bit(CODE,2) xor todo);
+
+    end;
+
+    // just header output
+    if b < 8 then
+      write(inttohex(buf_out[b])+' ');
+
+  end;
+  writeln;
+
+  // write buffer to output file
+  if unprotected then
+    o_file_name:= ParamStr(1)+'.protected'
+  else
+    o_file_name:= ParamStr(1)+'.decoded';
+
+{$I-}
+  FileMode:= fmOpenReadWrite;
+  AssignFile(o_file, o_file_name);
+  reset(o_file);
+  if IOResult <> 0 then
+    rewrite(o_file);
+  seek(o_file, 0);
+  BlockWrite(o_file, buf_out[0], data_len);
+  CloseFile(o_file);
+{$I+}
+  i:= IOResult;
+  if (i > 0) then
+  begin
+    writeln('ERROR: IOResult='+inttostr(i)+' during writing to output file');
+    exit;
+  end;
+
+  // finish
+  writeln('');
+end.

fw/protect/readme.txt

@@ -0,0 +1,4 @@
+у sprinter-97 битстрим алтеры шифровался. 
+декодирование производилось аппаратно во время его загрузки из ПЗУ.
+
+алгоритм разобран, написана новая универсальная утилита для шифрования и расшифровывания.

fw/src/flex/KBD_INI2.MIF

@@ -0,0 +1,167 @@
+DEPTH = 256;	% Memory depth and width are required	%
+WIDTH = 8;	% Enter a decimal number	%
+
+ADDRESS_RADIX = HEX;	% Address and value radixes are optional	%
+DATA_RADIX = BIN;	% Enter BIN, DEC, HEX, or OCT; unless 	%
+			% otherwise specified, radixes = HEX	%
+
+-- Specify values for addresses, which can be single address or range
+
+CONTENT
+	BEGIN
+[0..FF]	: 11111111;
+0	:
+	11111111	% ..   %
+	00100001	% F9   %
+	11111111	% ..   %
+	00011100	% F5   %
+	00011010	% F3   %
+	00011000	% F1   %
+	00011001	% F2   %
+	11111111	% F12  %
+	11111111	% ..   %
+	00100000	% F10  %
+
+	00100010	% F8          %
+	00100100	% F6          %
+    00011011	% F4          %
+    01011000	% Tab         %
+    10001000	% ~`          %
+    11111111	% ..          %
+    11111111	% ..          %
+    01111001	% Alt         %
+    11000000	% Left Shift  %
+    11111111	% ..          %
+
+    11111001	% Ctrl   %
+    11010000	% 'Q'    %
+    11011000	% '1'    %
+    11111111	% ..     %
+    11111111	% ..     %
+    11111111	% ..     %
+    11000001	% 'Z'    %
+    11001001	% 'S'    %
+    11001000	% 'A'    %
+    11010001	% 'W'    %
+
+    11011001	% '2'   	%
+    01110000	% left WIN  %
+    11111111	% ..     	%
+    11000011	% 'C'    	%
+    11000010	% 'X'    	%
+    11001010	% 'D'    	%
+    11010010	% 'E'    	%
+    11011011	% '4'    	%
+    11011010	% '3'    	%
+    10110000	% Right WIN %
+
+    11111111	% ..     		%
+    11111000	% ' '    		%
+    11000100	% 'V'    		%
+    11001011	% 'F'    		%
+    11010100	% 'T'    		%
+    11010011	% 'R'    		%
+    11011100	% '5'    		%
+    10111000	% Right Mouse	%
+    11111111	% ..     		%
+    11111011	% 'N'    		%
+
+    11111100	% 'B'    %
+    11110100	% 'H'    %
+    11001100	% 'G'    %
+    11101100	% 'Y'    %
+    11100100	% '6'    %
+    11111111	% ..     %
+    11111111	% ..     %
+    11111111	% ..     %
+    11111010	% 'M'    %
+    11110011	% 'J'    %
+
+    11101011	% 'U'    %
+    11100011	% '7'    %
+    11100010	% '8'    %
+    11111111	% ..     %
+    11111111	% ..     %
+    10111011	% ','    %
+    11110010	% 'K'    %
+    11101010	% 'I'    %
+    11101001	% 'O'    %
+    11100000	% '0'    %
+
+    11100001	% '9'    %
+    11111111	% ..     %
+    11111111	% ..     %
+    10111010	% '.'    %
+    10000100	% '/'    %
+    11110001	% 'L'    %
+    10101001	% ';'    %
+    11101000	% 'P'    %
+    10110011	% '-'    %
+    11111111	% ..     %
+
+    11111111	% ..           %
+    11111111	% ..           %
+    10101000	% "'"          %
+    11111111	% ..           %
+    10101100	% '['          %
+    10110001	% '='          %
+    11111111	% ..           %
+    11111111	% ..           %
+    01011001	% Caps Lock    %
+    11000000	% Right SHIFT  %
+
+    11110000	% ENTER    %
+    10101011	% ']'      %
+    11111111	% ..       %
+    10001010	% '\'      %
+    11111111	% ..       %
+    11111111	% ..       %
+    11111111	% ..       %
+    11111111	% ..       %
+    11111111	% ..       %
+    11111111	% ..       %
+
+    11111111	% ..       %
+    11111111	% ..       %
+    01100000	% Back     %
+    11111111	% ..       %
+    11111111	% ..       %
+    10010010	% End      %
+    11111111	% ..       %
+    01011100	% <-       %
+    10010000	% Home     %
+    11111111	% ..       %
+
+	11111111	% ..       			 %
+    11111111	% ..       			 %
+    10010001	% ins      			 %
+    01100001	% DEL      			 %
+    01100100	% Dn       			 %
+    10101010	% grey 5 ; ctrl + I  %
+    01100010	% ->       			 %
+    01100011	% Up       			 %
+    01111000	% ESC      			 %
+    00111111	% Num      			 %
+
+	11111111	% F11                %
+    10110010	% G+                 %
+    01011011	% PDn	; caps + 4   %
+    10110011	% G-                 %
+    10111100	% G*                 %
+    01011010	% PUp	; caps + 3   %
+    00000000	% Scrol Lock         %
+    11111111	% ..                 %
+    11111111	% ..                 %
+    11111111	% ..                 %
+
+    11111111	% ..    %
+    00100011	% F7    %	;
+%	!! DATA FOR CAPS !! %
+C0	:
+	11111101		% Function shift	%
+	11000000    	% Left Shift		%
+	11111001    	% Ctrl				%
+	11111111	;	% no shift			%
+END ;
+
+

fw/src/flex/PGA_INI4.MIF

@@ -0,0 +1,60 @@
+DEPTH = 256;	% Memory depth and width are required	%
+WIDTH = 8;		% Enter a decimal number	%
+
+ADDRESS_RADIX = HEX;	% Address and value radixes are optional	%
+DATA_RADIX = HEX;		% Enter BIN, DEC, HEX, or OCT; unless 	%
+						% otherwise specified, radixes = HEX	%
+
+-- Specify values for addresses, which can be single address or range
+
+CONTENT
+BEGIN
+	[0..FF]	: 0;
+
+	0		: 40	% DCP PAGE %;
+
+	10		:
+			C0 % WG93 1F,0F %
+			C2 % WG93 3F %
+			C4 % WG93 5F %
+			C6 % WG93 7F %
+			80 % WR_PDOS FF %
+			9F % RD_KEYS/ WR_A20 %;
+	18		:
+			B0 % CMOS_DAT %
+			B2 % CMOS_ADR %
+			B4 % CMOS_XX1 %
+			B6 % CMOS_XX1 %
+			B8
+			BA
+			BC
+			BE;
+	20		:
+			A0 % HD_CS1 ports %
+			A2
+			A4
+			A6
+			A8
+			AA
+			AC
+			AE
+			AD % HD_CS3 3F6 port %
+			AF % HD_CS3 3F7 port %;
+	30		:
+			D0 % slot 1 mem   %
+			D2 % slot 2 mem   %
+			D4 % slot 1 ports %
+			D6 % slot 2 ports %
+			;
+
+--	40		: FF % kb read %;
+--	80		: 7F 7F 7F 7F 7F 7F 7F 7F % KBD_DAT %;
+--	90		: 7F % PORT FF %;
+
+	C0		: 00 00 00 00 % SYS PORTS COPYES %;
+
+	D0		: 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F; % RAM PAGES %
+	E0		: E0 E2 E4 E6 E8 EA EC EE 00 05 02 E0 F0 00 00 E8; % ROM PAGES %
+	F0		: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F; % RAM PAGES %
+
+END ;

fw/src/flex/PGA_INI5.MIF

@@ -0,0 +1,50 @@
+DEPTH = 256;	% Memory depth and width are required	%
+WIDTH = 8;		% Enter a decimal number	%
+
+ADDRESS_RADIX = HEX;	% Address and value radixes are optional	%
+DATA_RADIX = HEX;		% Enter BIN, DEC, HEX, or OCT; unless 	%
+						% otherwise specified, radixes = HEX	%
+
+-- Specify values for addresses, which can be single address or range
+
+CONTENT
+BEGIN
+	[0..FF]	: 0;
+
+	0		: 40	% DCP PAGE %;
+
+	10		:
+			C0 % WG93 1F,0F %
+			C2 % WG93 3F %
+			C4 % WG93 5F %
+			C6 % WG93 7F %
+			80 % WR_PDOS FF %
+			9F % RD_KEYS/ WR_A20 %;
+	18		:
+			B0 % CMOS_DAT %
+			B2 % CMOS_ADR %
+			B4 % CMOS_XX1 %
+			B6 % CMOS_XX1 %;
+	20		:
+			A0 % HD_CS1 ports %
+			A2
+			A4
+			A6
+			A8
+			AA
+			AC
+			AE
+			AD % HD_CS3 3F6 port %
+			AF % HD_CS3 3F7 port %;
+--	40		: FF % kb read %;
+--	80		: 7F 7F 7F 7F 7F 7F 7F 7F % KBD_DAT %;
+--	90		: 7F % PORT FF %;
+
+	C0		: 00 00 00 00 % SYS PORTS COPYES %;
+
+
+	E0		: E0 E2 E4 E6 E8 EA EC EE 00 05 02 10 00 00 00 11; % ROM PAGES %
+	F0		: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F; % RAM PAGES %
+
+END ;
+

fw/src/flex/SND_INI.MIF

@@ -0,0 +1,28 @@
+DEPTH = 256;	% Memory depth and width are required	%
+WIDTH = 8;	% Enter a decimal number	%
+
+ADDRESS_RADIX = HEX;	% Address and value radixes are optional	%
+DATA_RADIX = HEX;	% Enter BIN, DEC, HEX, or OCT; unless 	%
+			% otherwise specified, radixes = HEX	%
+
+-- Specify values for addresses, which can be single address or range
+
+CONTENT
+BEGIN
+	[0..FF]	: 00;
+	00		: 80 00 04 06;
+	04		: 00 00 04 06;
+	08		: 80 40 00 06;
+	0C		: 00 40 00 06;
+
+	40		: 00 00 00 88;
+	44		: 00 00 00 88;
+	48		: 00 00 00 88;
+	4C		: 00 00 00 88;
+
+--	D0		: 00 80 40 C0 20 A0 60 E0 10 90 50 D0 30 B0 70 F0;
+--	E0		: 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0;
+--	F0		: 00 10 30 50 70 90 B0 C0 C0 B0 90 70 50 30 10 00;
+
+END ;
+

fw/src/flex/SPRINT08.ACF

@@ -0,0 +1,792 @@
+--
+--  Copyright (C) 1988-1998 Altera Corporation
+--  Any megafunction design, and related net list (encrypted or decrypted),
+--  support information, device programming or simulation file, and any other
+--  associated documentation or information provided by Altera or a partner
+--  under Altera's Megafunction Partnership Program may be used only to
+--  program PLD devices (but not masked PLD devices) from Altera.  Any other
+--  use of such megafunction design, net list, support information, device
+--  programming or simulation file, or any other related documentation or
+--  information is prohibited for any other purpose, including, but not
+--  limited to modification, reverse engineering, de-compiling, or use with
+--  any other silicon devices, unless such use is explicitly licensed under
+--  a separate agreement with Altera or a megafunction partner.  Title to
+--  the intellectual property, including patents, copyrights, trademarks,
+--  trade secrets, or maskworks, embodied in any such megafunction design,
+--  net list, support information, device programming or simulation file, or
+--  any other related documentation or information provided by Altera or a
+--  megafunction partner, remains with Altera, the megafunction partner, or
+--  their respective licensors.  No other licenses, including any licenses
+--  needed under any third party's intellectual property, are provided herein.
+--
+CHIP sprint08
+BEGIN
+	DEVICE = EPF10K10QC208-4;
+	|SINC_H :	OUTPUT_PIN = 175;
+	|KBD_CLK :	BIDIR_PIN = 193;
+	|KBD_DAT :	BIDIR_PIN = 196;
+	|BEEPER :	OUTPUT_PIN = 192;
+	|/WAIT :	BIDIR_PIN = 16;
+	|/INT :	BIDIR_PIN = 197;
+	|/NMI :	BIDIR_PIN = 195;
+	|MXA10 :	BIDIR_PIN = 200;
+	|MXA9 :	BIDIR_PIN = 199;
+	|MXA8 :	BIDIR_PIN = 198;
+	|MXA7 :	BIDIR_PIN = 187;
+	|MXA6 :	BIDIR_PIN = 174;
+	|MXA5 :	BIDIR_PIN = 172;
+	|MXA4 :	BIDIR_PIN = 170;
+	|MXA3 :	BIDIR_PIN = 169;
+	|MXA2 :	BIDIR_PIN = 168;
+	|MXA1 :	BIDIR_PIN = 167;
+	|MXA0 :	BIDIR_PIN = 166;
+	|/WE :	OUTPUT_PIN = 208;
+	|CAS_3 :	OUTPUT_PIN = 207;
+	|CAS_2 :	OUTPUT_PIN = 205;
+	|CAS_1 :	OUTPUT_PIN = 206;
+	|CAS_0 :	OUTPUT_PIN = 204;
+	|RAS_0 :	OUTPUT_PIN = 203;
+	|RAS_1 :	OUTPUT_PIN = 202;
+	|MS_MOUSE :	INPUT_PIN = 191;
+	|TAPE_OUT :	OUTPUT_PIN = 190;
+	|TURBO_LED :	OUTPUT_PIN = 189;
+	|SND_R1 :	OUTPUT_PIN = 176;
+	|MD0 :	BIDIR_PIN = 186;
+	|TAPE_IN :	INPUT_PIN = 182;
+	|MD1 :	BIDIR_PIN = 180;
+	|MD2 :	BIDIR_PIN = 179;
+	|MD3 :	BIDIR_PIN = 177;
+	|SINC :	OUTPUT_PIN = 173;
+	|MD4 :	BIDIR_PIN = 164;
+	|MD5 :	BIDIR_PIN = 163;
+	|MD6 :	BIDIR_PIN = 162;
+	|MD7 :	BIDIR_PIN = 161;
+	|SND_L1 :	OUTPUT_PIN = 160;
+	|SND_R0 :	OUTPUT_PIN = 159;
+	|SND_L0 :	OUTPUT_PIN = 158;
+	|CLK_PIX :	OUTPUT_PIN = 157;
+	|VA0 :	OUTPUT_PIN = 133;
+	|VA1 :	OUTPUT_PIN = 128;
+	|V_CS0 :	OUTPUT_PIN = 127;
+	|VA2 :	OUTPUT_PIN = 121;
+	|VA10 :	OUTPUT_PIN = 120;
+	|VA3 :	OUTPUT_PIN = 116;
+	|VA4 :	OUTPUT_PIN = 112;
+	|VA11 :	OUTPUT_PIN = 111;
+	|VA5 :	OUTPUT_PIN = 104;
+	|VA9 :	OUTPUT_PIN = 102;
+	|VA6 :	OUTPUT_PIN = 100;
+	|VA8 :	OUTPUT_PIN = 99;
+	|VA7 :	OUTPUT_PIN = 96;
+	|VA13 :	OUTPUT_PIN = 95;
+	|V_WR3 :	OUTPUT_PIN = 94;
+	|VA12 :	OUTPUT_PIN = 93;
+	|V_WR0 :	OUTPUT_PIN = 92;
+	|V_WR1 :	OUTPUT_PIN = 90;
+	|V_WR2 :	OUTPUT_PIN = 89;
+	|VA14 :	OUTPUT_PIN = 88;
+	|VA15 :	OUTPUT_PIN = 86;
+	|/MR :	INPUT_PIN = 184;
+	|TG42 :	INPUT_PIN = 183;
+	|VD03 :	BIDIR_PIN = 150;
+	|VD13 :	BIDIR_PIN = 149;
+	|VD02 :	BIDIR_PIN = 148;
+	|VD04 :	BIDIR_PIN = 147;
+	|VD14 :	BIDIR_PIN = 144;
+	|VD01 :	BIDIR_PIN = 143;
+	|VD05 :	BIDIR_PIN = 142;
+	|VD15 :	BIDIR_PIN = 141;
+	|VD00 :	BIDIR_PIN = 136;
+	|VD06 :	BIDIR_PIN = 135;
+	|VD16 :	BIDIR_PIN = 134;
+	|VD07 :	BIDIR_PIN = 132;
+	|VD17 :	BIDIR_PIN = 131;
+	|VD12 :	BIDIR_PIN = 122;
+	|VD11 :	BIDIR_PIN = 119;
+	|VD10 :	BIDIR_PIN = 115;
+	|VD22 :	BIDIR_PIN = 103;
+	|VD21 :	BIDIR_PIN = 101;
+	|VD20 :	BIDIR_PIN = 97;
+	|VD23 :	BIDIR_PIN = 87;
+	|VD24 :	BIDIR_PIN = 85;
+	|VD30 :	BIDIR_PIN = 83;
+	|/WR :	INPUT_PIN = 79;
+	|/RD :	INPUT_PIN = 80;
+	|/IO :	INPUT_PIN = 78;
+	|VD37 :	BIDIR_PIN = 75;
+	|VD25 :	BIDIR_PIN = 74;
+	|VD27 :	BIDIR_PIN = 73;
+	|VD36 :	BIDIR_PIN = 71;
+	|VD26 :	BIDIR_PIN = 70;
+	|VD31 :	BIDIR_PIN = 69;
+	|VD35 :	BIDIR_PIN = 68;
+	|VD32 :	BIDIR_PIN = 67;
+	|VD34 :	BIDIR_PIN = 65;
+	|VD33 :	BIDIR_PIN = 64;
+	|V_CS1 :	OUTPUT_PIN = 63;
+	|CLKZ1 :	OUTPUT_PIN = 62;
+	|D7 :	BIDIR_PIN = 61;
+	|D6 :	BIDIR_PIN = 60;
+	|D5 :	BIDIR_PIN = 58;
+	|D4 :	BIDIR_PIN = 57;
+	|D3 :	BIDIR_PIN = 56;
+	|D2 :	BIDIR_PIN = 55;
+	|D1 :	BIDIR_PIN = 54;
+	|D0 :	BIDIR_PIN = 53;
+	|A15 :	BIDIR_PIN = 47;
+	|A14 :	BIDIR_PIN = 46;
+	|A13 :	BIDIR_PIN = 45;
+	|A12 :	BIDIR_PIN = 44;
+	|A11 :	BIDIR_PIN = 41;
+	|A10 :	BIDIR_PIN = 40;
+	|A9 :	BIDIR_PIN = 39;
+	|A8 :	BIDIR_PIN = 38;
+	|A7 :	BIDIR_PIN = 31;
+	|A6 :	BIDIR_PIN = 30;
+	|A5 :	BIDIR_PIN = 29;
+	|A4 :	BIDIR_PIN = 28;
+	|A3 :	BIDIR_PIN = 27;
+	|A2 :	BIDIR_PIN = 26;
+	|A1 :	BIDIR_PIN = 25;
+	|A0 :	BIDIR_PIN = 24;
+	|/RF :	INPUT_PIN = 19;
+	|/M1 :	INPUT_PIN = 18;
+	|/RESET :	BIDIR_PIN = 17;
+	|XA2 :	OUTPUT_PIN = 12;
+	|XA1 :	OUTPUT_PIN = 11;
+	|XA0 :	OUTPUT_PIN = 10;
+	|XACS :	OUTPUT_PIN = 13;
+END;
+
+DEFAULT_DEVICES
+BEGIN
+	AUTO_DEVICE = EPF10K50GC403;
+	AUTO_DEVICE = EPF10K50GC403ES;
+	AUTO_DEVICE = EPF10K50RC240;
+	AUTO_DEVICE = EPF10K30RC240;
+	AUTO_DEVICE = EPF10K10QC208;
+	ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
+END;
+
+TIMING_POINT
+BEGIN
+	DEVICE_FOR_TIMING_SYNTHESIS = EPF10K10QC208-4;
+	CUT_ALL_CLEAR_PRESET = ON;
+	CUT_ALL_BIDIR = ON;
+	MAINTAIN_STABLE_SYNTHESIS = OFF;
+END;
+
+IGNORED_ASSIGNMENTS
+BEGIN
+	IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
+	IGNORE_CHIP_ASSIGNMENTS = OFF;
+	DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
+	IGNORE_DEVICE_ASSIGNMENTS = OFF;
+	IGNORE_LC_ASSIGNMENTS = OFF;
+	IGNORE_PIN_ASSIGNMENTS = OFF;
+	IGNORE_TIMING_ASSIGNMENTS = OFF;
+	IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
+	IGNORE_CLIQUE_ASSIGNMENTS = OFF;
+END;
+
+LOGIC_OPTIONS
+BEGIN
+	|ALU0 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|ALU1 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|ALU2 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|ALU3 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|ALU4 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|ALU5 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|ALU6 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|ALU7 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|ALU8 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|ALU9 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|ALU10 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|ALU11 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|ALU12 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|ALU13 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|ALU14 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|ALU15 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|AY_Q10 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|AY_Q11 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|AY_Q13 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|AY_Q12 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|AY_Q20 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|AY_Q21 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|AY_Q22 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|AY_Q23 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|AY_Q30 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|AY_Q31 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|AY_Q32 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|AY_Q33 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|MXA0 :	IGNORE_SOFT_BUFFERS = ON;
+	|MXA1 :	IGNORE_SOFT_BUFFERS = ON;
+	|MXA4 :	IGNORE_SOFT_BUFFERS = ON;
+	|MXA3 :	IGNORE_SOFT_BUFFERS = ON;
+	|MXA2 :	IGNORE_SOFT_BUFFERS = ON;
+	|MXA6 :	IGNORE_SOFT_BUFFERS = ON;
+	|MXA5 :	IGNORE_SOFT_BUFFERS = ON;
+	|MXA8 :	IGNORE_SOFT_BUFFERS = ON;
+	|MXA7 :	IGNORE_SOFT_BUFFERS = ON;
+	|MXA9 :	IGNORE_SOFT_BUFFERS = ON;
+	|MXA10 :	IGNORE_SOFT_BUFFERS = ON;
+	|SVA10 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|SVA11 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|SVA12 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|V_WR0 :	SLOW_SLEW_RATE = OFF;
+	|V_WR1 :	SLOW_SLEW_RATE = OFF;
+	|V_WR2 :	SLOW_SLEW_RATE = OFF;
+	|V_WR3 :	SLOW_SLEW_RATE = OFF;
+	|VA0 :	SLOW_SLEW_RATE = OFF;
+	|VA1 :	SLOW_SLEW_RATE = OFF;
+	|VA2 :	SLOW_SLEW_RATE = OFF;
+	|VA3 :	SLOW_SLEW_RATE = OFF;
+	|VA4 :	SLOW_SLEW_RATE = OFF;
+	|VA5 :	SLOW_SLEW_RATE = OFF;
+	|VA6 :	SLOW_SLEW_RATE = OFF;
+	|VA7 :	SLOW_SLEW_RATE = OFF;
+	|VA8 :	SLOW_SLEW_RATE = OFF;
+	|VA9 :	SLOW_SLEW_RATE = OFF;
+	|VA10 :	SLOW_SLEW_RATE = OFF;
+	|VA11 :	SLOW_SLEW_RATE = OFF;
+	|VA12 :	SLOW_SLEW_RATE = OFF;
+	|VA13 :	SLOW_SLEW_RATE = OFF;
+	|VA14 :	SLOW_SLEW_RATE = OFF;
+	|VA15 :	SLOW_SLEW_RATE = OFF;
+	|SVA2 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|RA18 :	IMPLEMENT_IN_EAB = ON;
+	|RA19 :	IMPLEMENT_IN_EAB = ON;
+	|RA20 :	IMPLEMENT_IN_EAB = ON;
+	|RA21 :	IMPLEMENT_IN_EAB = ON;
+	|VA0 :	FAST_IO = ON;
+	|VA1 :	FAST_IO = ON;
+	|VA2 :	FAST_IO = ON;
+	|VA4 :	FAST_IO = ON;
+	|VA3 :	FAST_IO = ON;
+	|VA6 :	FAST_IO = ON;
+	|VA5 :	FAST_IO = ON;
+	|VA8 :	FAST_IO = ON;
+	|VA7 :	FAST_IO = ON;
+	|VA10 :	FAST_IO = ON;
+	|VA9 :	FAST_IO = ON;
+	|VA12 :	FAST_IO = ON;
+	|VA11 :	FAST_IO = ON;
+	|VA13 :	FAST_IO = ON;
+	|VA14 :	FAST_IO = ON;
+	|VA15 :	FAST_IO = ON;
+	|VXA0 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|VXA1 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|VXA2 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|VXA3 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|VXA4 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|VXA5 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|VXA6 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|VXA7 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|VXA8 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|VXA9 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|VXA10 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|VXA11 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|VXA12 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|VXA13 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|VXA14 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|VXA15 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|VXA16 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|VXA17 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|SVA0 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|SVA1 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|SVA3 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|SVA4 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|SVA5 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|MPGS0 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|MPGS1 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|MPGS2 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|MPGS3 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+	|MPGS4 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
+END;
+
+GLOBAL_PROJECT_DEVICE_OPTIONS
+BEGIN
+	FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
+	FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
+	FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
+	FLEX6000_ENABLE_JTAG = OFF;
+	CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
+	LOW_VOLTAGE_IO = OFF;
+	nCEO = UNRESERVED;
+	CONFIG_SCHEME_10K = PASSIVE_SERIAL;
+	FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
+	CONFIG_SCHEME = PASSIVE_PARALLEL_SYNCHRONOUS;
+	DISABLE_TIME_OUT = ON;
+	RELEASE_CLEARS = ON;
+	AUTO_RESTART = ON;
+	SDOUT = UNRESERVED;
+	DATA0 = UNRESERVED;
+	MAX7000S_USER_CODE = FFFF;
+	FLEX10K_JTAG_USER_CODE = 7F;
+	ENABLE_INIT_DONE_OUTPUT = OFF;
+	ENABLE_CHIP_WIDE_OE = OFF;
+	ENABLE_CHIP_WIDE_RESET = OFF;
+	CLKUSR = UNRESERVED;
+	ADD17 = UNRESERVED;
+	ADD16 = UNRESERVED;
+	ADD15 = UNRESERVED;
+	ADD14 = UNRESERVED;
+	ADD13 = UNRESERVED;
+	ADD0_TO_ADD12 = UNRESERVED;
+	RDCLK = UNRESERVED;
+	RDYnBUSY = UNRESERVED;
+	nWS_nRS_nCS_CS = UNRESERVED;
+	DATA1_TO_DATA7 = UNRESERVED;
+	FLEX8000_ENABLE_JTAG = OFF;
+	MAX7000S_ENABLE_JTAG = OFF;
+	ENABLE_DCLK_OUTPUT = OFF;
+	USER_CLOCK = OFF;
+	SECURITY_BIT = OFF;
+	RESERVED_PINS_PERCENT = 0;
+	RESERVED_LCELLS_PERCENT = 0;
+END;
+
+GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
+BEGIN
+	OPTIMIZE_FOR_SPEED = 0;
+	AUTO_REGISTER_PACKING = OFF;
+	AUTO_FAST_IO = ON;
+	AUTO_GLOBAL_OE = ON;
+	AUTO_GLOBAL_PRESET = ON;
+	AUTO_GLOBAL_CLEAR = ON;
+	AUTO_GLOBAL_CLOCK = ON;
+	AUTO_IMPLEMENT_IN_EAB = OFF;
+	AUTO_OPEN_DRAIN_PINS = ON;
+	DEVICE_FAMILY = FLEX10K;
+	ONE_HOT_STATE_MACHINE_ENCODING = OFF;
+	STYLE = NORMAL;
+	MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
+	MULTI_LEVEL_SYNTHESIS_MAX9000 = OFF;
+END;
+
+COMPILER_PROCESSING_CONFIGURATION
+BEGIN
+	FITTER_SETTINGS = ADVANCED;
+	SMART_RECOMPILE = ON;
+	GENERATE_AHDL_TDO_FILE = OFF;
+	TIMING_SNF_EXTRACTOR = OFF;
+	OPTIMIZE_TIMING_SNF = OFF;
+	PRESERVE_ALL_NODE_NAME_SYNONYMS = ON;
+	RPT_FILE_USER_ASSIGNMENTS = ON;
+	RPT_FILE_LCELL_INTERCONNECT = ON;
+	RPT_FILE_HIERARCHY = ON;
+	RPT_FILE_EQUATIONS = ON;
+	LINKED_SNF_EXTRACTOR = OFF;
+	FUNCTIONAL_SNF_EXTRACTOR = OFF;
+	DESIGN_DOCTOR_RULES = EPLD;
+	DESIGN_DOCTOR = OFF;
+END;
+
+COMPILER_INTERFACES_CONFIGURATION
+BEGIN
+	VHDL_FLATTEN_BUS = OFF;
+	VERILOG_FLATTEN_BUS = OFF;
+	EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
+	VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
+	VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
+	VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
+	EDIF_BUS_DELIMITERS = [];
+	EDIF_FLATTEN_BUS = OFF;
+	VHDL_WRITER_VERSION = VHDL87;
+	VHDL_READER_VERSION = VHDL87;
+	SYNOPSYS_MAPPING_EFFORT = MEDIUM;
+	SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
+	SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
+	SYNOPSYS_DESIGNWARE = OFF;
+	SYNOPSYS_COMPILER = DESIGN;
+	USE_SYNOPSYS_SYNTHESIS = OFF;
+	NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
+	EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
+	EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
+	EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
+	EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
+	EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
+	EDIF_OUTPUT_USE_EDC = OFF;
+	EDIF_INPUT_USE_LMF2 = OFF;
+	EDIF_INPUT_USE_LMF1 = OFF;
+	EDIF_OUTPUT_GND = GND;
+	EDIF_OUTPUT_VCC = VCC;
+	EDIF_INPUT_GND = GND;
+	EDIF_INPUT_VCC = VCC;
+	EDIF_OUTPUT_EDC_FILE = *.edc;
+	EDIF_INPUT_LMF2 = *.lmf;
+	EDIF_INPUT_LMF1 = *.lmf;
+	VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
+	VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
+	VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
+	VHDL_NETLIST_WRITER = OFF;
+	VERILOG_NETLIST_WRITER = OFF;
+	XNF_GENERATE_AHDL_TDX_FILE = ON;
+	XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
+	XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
+	EDIF_OUTPUT_VERSION = 200;
+	EDIF_NETLIST_WRITER = OFF;
+END;
+
+CUSTOM_DESIGN_DOCTOR_RULES
+BEGIN
+	MASTER_RESET = OFF;
+	EXPANDER_NETWORKS = ON;
+	RACE_CONDITIONS = ON;
+	DELAY_CHAINS = ON;
+	ASYNCHRONOUS_INPUTS = ON;
+	PRESET_CLEAR_NETWORKS = ON;
+	STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
+	STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
+	MULTI_CLOCK_NETWORKS = ON;
+	MULTI_LEVEL_CLOCKS = ON;
+	GATED_CLOCKS = ON;
+	RIPPLE_CLOCKS = ON;
+END;
+
+SIMULATOR_CONFIGURATION
+BEGIN
+	END_TIME = 0.0ns;
+	START_TIME = 0.0ns;
+	GLITCH_TIME = 0.0ns;
+	GLITCH = OFF;
+	OSCILLATION_TIME = 0.0ns;
+	OSCILLATION = OFF;
+	CHECK_OUTPUTS = OFF;
+	SETUP_HOLD = OFF;
+	USE_DEVICE = OFF;
+END;
+
+TIMING_ANALYZER_CONFIGURATION
+BEGIN
+	REGISTERED_PERFORMANCE_OPTIONS = FREQUENCY_OF_PATHS;
+	LIST_PATH_FREQUENCY = 42.01MHz;
+	LIST_PATH_COUNT = 10;
+	INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
+	INCLUDE_PATHS_LESS_THAN = OFF;
+	INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
+	INCLUDE_PATHS_GREATER_THAN = OFF;
+	DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
+	CELL_WIDTH = 18;
+	LIST_ONLY_LONGEST_PATH = ON;
+	CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
+	CUT_OFF_IO_PIN_FEEDBACK = ON;
+	AUTO_RECALCULATE = OFF;
+	ANALYSIS_MODE = DELAY_MATRIX;
+END;
+
+OTHER_CONFIGURATION
+BEGIN
+	ROW_PINS_PERCENT = 95;
+	CARRY_OUT_PINS_LCELL_INSERT = OFF;
+	LAST_MAXPLUS2_VERSION = 8.2;
+	LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
+	ROW_PINS_LCELL_INSERT = ON;
+	NORMAL_LCELL_INSERT = ON;
+	COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,0,0,1,1,1";
+	FLEX_10K_52_COLUMNS = 40;
+	EXPLICIT_FAMILY = 1;
+	DEFAULT_9K_EXP_PER_LCELL = 1/2;
+	LCELLS_PER_ROW_PERCENT = 100;
+	FAN_IN_PER_LCELL_PERCENT = 100;
+	EXP_PER_LCELL_PERCENT = 100;
+	ORIGINAL_MAXPLUS2_VERSION = 6.0;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
+BEGIN
+	REGISTER_OPTIMIZATION = ON;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = ON;
+	SUBFACTOR_EXTRACTION = ON;
+	REFACTORIZATION = ON;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = ON;
+	REDUCE_LOGIC = ON;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN = IGNORE;
+	MINIMIZATION = FULL;
+	FAST_IO = OFF;
+	IGNORE_SOFT_BUFFERS = OFF;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = OFF;
+	XOR_SYNTHESIS = ON;
+	SLOW_SLEW_RATE = OFF;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
+BEGIN
+	REGISTER_OPTIMIZATION = ON;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = ON;
+	SUBFACTOR_EXTRACTION = ON;
+	REFACTORIZATION = ON;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = ON;
+	REDUCE_LOGIC = ON;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN = IGNORE;
+	MINIMIZATION = FULL;
+	FAST_IO = OFF;
+	IGNORE_SOFT_BUFFERS = OFF;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = ON;
+	XOR_SYNTHESIS = ON;
+	SLOW_SLEW_RATE = OFF;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
+BEGIN
+	REGISTER_OPTIMIZATION = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = OFF;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = OFF;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN = IGNORE;
+	MINIMIZATION = FULL;
+	FAST_IO = OFF;
+	IGNORE_SOFT_BUFFERS = OFF;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = ON;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
+BEGIN
+	CARRY_CHAIN = AUTO;
+	CARRY_CHAIN_LENGTH = 32;
+	SLOW_SLEW_RATE = ON;
+	CASCADE_CHAIN = AUTO;
+	IGNORE_SOFT_BUFFERS = OFF;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	DECOMPOSE_GATES = ON;
+	REGISTER_OPTIMIZATION = ON;
+	DUPLICATE_LOGIC_EXTRACTION = ON;
+	MINIMIZATION = FULL;
+	CASCADE_CHAIN_LENGTH = 2;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = ON;
+	SUBFACTOR_EXTRACTION = ON;
+	REFACTORIZATION = ON;
+	NOT_GATE_PUSH_BACK = ON;
+	REDUCE_LOGIC = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = OFF;
+	XOR_SYNTHESIS = OFF;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
+BEGIN
+	IGNORE_SOFT_BUFFERS = OFF;
+	REGISTER_OPTIMIZATION = ON;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = ON;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = ON;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	FAST_IO = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = OFF;
+	XOR_SYNTHESIS = ON;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = FULL;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
+BEGIN
+	IGNORE_SOFT_BUFFERS = OFF;
+	REGISTER_OPTIMIZATION = ON;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = ON;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = ON;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	FAST_IO = OFF;
+	PARALLEL_EXPANDERS = ON;
+	TURBO_BIT = ON;
+	XOR_SYNTHESIS = ON;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = FULL;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
+BEGIN
+	IGNORE_SOFT_BUFFERS = OFF;
+	REGISTER_OPTIMIZATION = OFF;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = OFF;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = OFF;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	FAST_IO = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = ON;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = FULL;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
+BEGIN
+	IGNORE_SOFT_BUFFERS = OFF;
+	REGISTER_OPTIMIZATION = ON;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = ON;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = ON;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = OFF;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = FULL;
+	CARRY_CHAIN_LENGTH = 32;
+	CARRY_CHAIN = AUTO;
+	CASCADE_CHAIN_LENGTH = 2;
+	CASCADE_CHAIN = AUTO;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
+BEGIN
+	IGNORE_SOFT_BUFFERS = OFF;
+	REGISTER_OPTIMIZATION = OFF;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = OFF;
+	MULTI_LEVEL_FACTORING = OFF;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = OFF;
+	DECOMPOSE_GATES = OFF;
+	SOFT_BUFFER_INSERTION = OFF;
+	FAST_IO = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = OFF;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = PARTIAL;
+	CARRY_CHAIN_LENGTH = -1;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN_LENGTH = -1;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
+BEGIN
+	IGNORE_SOFT_BUFFERS = OFF;
+	REGISTER_OPTIMIZATION = OFF;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = OFF;
+	MULTI_LEVEL_FACTORING = OFF;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = OFF;
+	DECOMPOSE_GATES = OFF;
+	SOFT_BUFFER_INSERTION = OFF;
+	FAST_IO = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = ON;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = PARTIAL;
+	CARRY_CHAIN_LENGTH = -1;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN_LENGTH = -1;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
+BEGIN
+	IGNORE_SOFT_BUFFERS = OFF;
+	REGISTER_OPTIMIZATION = OFF;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = OFF;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = OFF;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = OFF;
+	FAST_IO = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = ON;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = PARTIAL;
+	CARRY_CHAIN_LENGTH = -1;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN_LENGTH = -1;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
+BEGIN
+	REGISTER_OPTIMIZATION = OFF;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = OFF;
+	MULTI_LEVEL_FACTORING = OFF;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = OFF;
+	DECOMPOSE_GATES = OFF;
+	SOFT_BUFFER_INSERTION = ON;
+	IGNORE_SOFT_BUFFERS = ON;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = OFF;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = PARTIAL;
+	CARRY_CHAIN_LENGTH = 32;
+	CARRY_CHAIN = MANUAL;
+	CASCADE_CHAIN_LENGTH = 2;
+	CASCADE_CHAIN = MANUAL;
+END;
+

fw/src/max/SP037032.ACF

@@ -0,0 +1,620 @@
+--
+--  Copyright (C) 1988-2000 Altera Corporation
+--  Any megafunction design, and related net list (encrypted or decrypted),
+--  support information, device programming or simulation file, and any other
+--  associated documentation or information provided by Altera or a partner
+--  under Altera's Megafunction Partnership Program may be used only to
+--  program PLD devices (but not masked PLD devices) from Altera.  Any other
+--  use of such megafunction design, net list, support information, device
+--  programming or simulation file, or any other related documentation or
+--  information is prohibited for any other purpose, including, but not
+--  limited to modification, reverse engineering, de-compiling, or use with
+--  any other silicon devices, unless such use is explicitly licensed under
+--  a separate agreement with Altera or a megafunction partner.  Title to
+--  the intellectual property, including patents, copyrights, trademarks,
+--  trade secrets, or maskworks, embodied in any such megafunction design,
+--  net list, support information, device programming or simulation file, or
+--  any other related documentation or information provided by Altera or a
+--  megafunction partner, remains with Altera, the megafunction partner, or
+--  their respective licensors.  No other licenses, including any licenses
+--  needed under any third party's intellectual property, are provided herein.
+--
+CHIP sp037032
+BEGIN
+	|CLK_WG :	OUTPUT_PIN = 33;
+	|HD_CS2 :	OUTPUT_PIN = 37;
+	|/RD :	INPUT_PIN = 2;
+	DEVICE = EPM7064SLC44-10;
+	|/WRH :	OUTPUT_PIN = 24;
+	|MA7 :	INPUT_PIN = 36;
+	|CLK_PRC :	OUTPUT_PIN = 27;
+	|/DTRB :	INPUT_PIN = 34;
+	|RDAT :	OUTPUT_PIN = 16;
+	|RDATA :	INPUT_PIN = 17;
+	|MA0 :	INPUT_PIN = 39;
+	|TG42_IN :	INPUT_PIN = 43;
+	|TG42_OUT :	OUTPUT_PIN = 41;
+	|/CONFIG :	OUTPUT_PIN = 40;
+	|CLKZZ :	OUTPUT_PIN = 31;
+	|/MR :	INPUT_PIN = 28;
+	|/IO :	INPUT_PIN = 29;
+	|HDD_CS :	INPUT_PIN = 26;
+	|/WR :	INPUT_PIN = 25;
+	|RSTB :	INPUT_PIN = 21;
+	|WSTB :	INPUT_PIN = 20;
+	|STE :	INPUT_PIN = 19;
+	|QDAT :	OUTPUT_PIN = 14;
+	|HD_CSS2 :	OUTPUT_PIN = 12;
+	|HD_CSS1 :	OUTPUT_PIN = 11;
+	|HD_OE1 :	OUTPUT_PIN = 8;
+	|HD_CS1 :	OUTPUT_PIN = 9;
+	|HD_WE1 :	OUTPUT_PIN = 6;
+	|HD_OE2 :	OUTPUT_PIN = 5;
+	|HD_WE2 :	OUTPUT_PIN = 4;
+	|D0 :	INPUT_PIN = 18;
+	|EPM_RES :	INPUT_PIN = 1;
+	|CNF_ON :	INPUT_PIN = 44;
+END;
+
+DEFAULT_DEVICES
+BEGIN
+	AUTO_DEVICE = EPM7256SQC208-7;
+	AUTO_DEVICE = EPM7256SRC208-7;
+	AUTO_DEVICE = EPM7192SQC160-7;
+	AUTO_DEVICE = EPM7160SQC160-7;
+	AUTO_DEVICE = EPM7160STC100-7;
+	AUTO_DEVICE = EPM7160SLC84-7;
+	AUTO_DEVICE = EPM7128SQC160-6;
+	AUTO_DEVICE = EPM7128STC100-6;
+	AUTO_DEVICE = EPM7128SQC100-6;
+	AUTO_DEVICE = EPM7128SLC84-6;
+	AUTO_DEVICE = EPM7064STC100-5;
+	AUTO_DEVICE = EPM7064SLC84-5;
+	AUTO_DEVICE = EPM7064STC44-5;
+	AUTO_DEVICE = EPM7064SLC44-5;
+	AUTO_DEVICE = EPM7032STC44-7;
+	AUTO_DEVICE = EPM7032SLC44-7;
+	ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
+END;
+
+TIMING_POINT
+BEGIN
+	DEVICE_FOR_TIMING_SYNTHESIS = EPM7064SLC44-10;
+	MAINTAIN_STABLE_SYNTHESIS = OFF;
+	CUT_ALL_CLEAR_PRESET = ON;
+	CUT_ALL_BIDIR = ON;
+END;
+
+IGNORED_ASSIGNMENTS
+BEGIN
+	FIT_IGNORE_TIMING = OFF;
+	IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
+	DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
+	IGNORE_DEVICE_ASSIGNMENTS = OFF;
+	IGNORE_LC_ASSIGNMENTS = OFF;
+	IGNORE_PIN_ASSIGNMENTS = OFF;
+	IGNORE_CHIP_ASSIGNMENTS = OFF;
+	IGNORE_TIMING_ASSIGNMENTS = OFF;
+	IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
+	IGNORE_CLIQUE_ASSIGNMENTS = OFF;
+END;
+
+LOGIC_OPTIONS
+BEGIN
+	|/WRH :	TURBO_BIT = OFF;
+	|10K_CLK :	TURBO_BIT = OFF;
+	|10K_D0 :	TURBO_BIT = OFF;
+	|/CONFIG :	TURBO_BIT = OFF;
+	|HD_CSS1 :	TURBO_BIT = OFF;
+	|HD_CSS2 :	TURBO_BIT = OFF;
+	|HD_CS1 :	TURBO_BIT = OFF;
+	|HD_CS2 :	TURBO_BIT = OFF;
+	|HD_OE1 :	TURBO_BIT = OFF;
+	|HD_OE2 :	TURBO_BIT = OFF;
+	|HD_WE1 :	TURBO_BIT = OFF;
+	|HD_WE2 :	TURBO_BIT = OFF;
+END;
+
+GLOBAL_PROJECT_DEVICE_OPTIONS
+BEGIN
+	MAX7000B_ENABLE_VREFB = OFF;
+	MAX7000B_ENABLE_VREFA = OFF;
+	MAX7000B_VCCIO_IOBANK2 = 3.3V;
+	MAX7000B_VCCIO_IOBANK1 = 3.3V;
+	CONFIG_EPROM_PULLUP_RESISTOR = ON;
+	CONFIG_EPROM_USER_CODE = FFFFFFFF;
+	FLEX_CONFIGURATION_EPROM = AUTO;
+	MAX7000AE_ENABLE_JTAG = ON;
+	MAX7000AE_USER_CODE = FFFFFFFF;
+	SECURITY_BIT = ON;
+	FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
+	FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
+	FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
+	FLEX6000_ENABLE_JTAG = OFF;
+	CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
+	MULTIVOLT_IO = OFF;
+	nCEO = UNRESERVED;
+	MAX7000S_ENABLE_JTAG = ON;
+	FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
+	MAX7000S_USER_CODE = FFFF;
+	CONFIG_SCHEME_10K = PASSIVE_SERIAL;
+	FLEX10K_JTAG_USER_CODE = 7F;
+	ENABLE_INIT_DONE_OUTPUT = OFF;
+	ENABLE_CHIP_WIDE_OE = OFF;
+	ENABLE_CHIP_WIDE_RESET = OFF;
+	CLKUSR = UNRESERVED;
+	ADD17 = UNRESERVED;
+	ADD16 = UNRESERVED;
+	ADD15 = UNRESERVED;
+	ADD14 = UNRESERVED;
+	ADD13 = UNRESERVED;
+	ADD0_TO_ADD12 = UNRESERVED;
+	SDOUT = RESERVED_DRIVES_OUT;
+	RDCLK = UNRESERVED;
+	RDYnBUSY = UNRESERVED;
+	nWS_nRS_nCS_CS = UNRESERVED;
+	DATA1_TO_DATA7 = UNRESERVED;
+	DATA0 = RESERVED_TRI_STATED;
+	FLEX8000_ENABLE_JTAG = OFF;
+	CONFIG_SCHEME = ACTIVE_SERIAL;
+	DISABLE_TIME_OUT = OFF;
+	ENABLE_DCLK_OUTPUT = OFF;
+	RELEASE_CLEARS = OFF;
+	AUTO_RESTART = OFF;
+	USER_CLOCK = OFF;
+	RESERVED_PINS_PERCENT = 0;
+	RESERVED_LCELLS_PERCENT = 0;
+END;
+
+GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
+BEGIN
+	DEVICE_FAMILY = MAX7000S;
+	AUTO_GLOBAL_OE = OFF;
+	AUTO_GLOBAL_PRESET = OFF;
+	AUTO_GLOBAL_CLEAR = OFF;
+	AUTO_GLOBAL_CLOCK = OFF;
+	OPTIMIZE_FOR_SPEED = 0;
+	MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
+	AUTO_IMPLEMENT_IN_EAB = OFF;
+	AUTO_OPEN_DRAIN_PINS = ON;
+	ONE_HOT_STATE_MACHINE_ENCODING = OFF;
+	AUTO_REGISTER_PACKING = OFF;
+	STYLE = NORMAL;
+	AUTO_FAST_IO = OFF;
+	MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
+END;
+
+COMPILER_PROCESSING_CONFIGURATION
+BEGIN
+	FITTER_SETTINGS = ADVANCED;
+	SMART_RECOMPILE = ON;
+	PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
+	GENERATE_AHDL_TDO_FILE = OFF;
+	RPT_FILE_USER_ASSIGNMENTS = ON;
+	RPT_FILE_LCELL_INTERCONNECT = ON;
+	RPT_FILE_HIERARCHY = ON;
+	RPT_FILE_EQUATIONS = ON;
+	LINKED_SNF_EXTRACTOR = OFF;
+	OPTIMIZE_TIMING_SNF = OFF;
+	TIMING_SNF_EXTRACTOR = ON;
+	FUNCTIONAL_SNF_EXTRACTOR = OFF;
+	DESIGN_DOCTOR_RULES = EPLD;
+	DESIGN_DOCTOR = OFF;
+END;
+
+COMPILER_INTERFACES_CONFIGURATION
+BEGIN
+	VHDL_FLATTEN_BUS = OFF;
+	VERILOG_FLATTEN_BUS = OFF;
+	NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
+	EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
+	EDIF_BUS_DELIMITERS = [];
+	EDIF_FLATTEN_BUS = OFF;
+	EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
+	EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
+	EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
+	EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
+	EDIF_OUTPUT_USE_EDC = OFF;
+	EDIF_INPUT_USE_LMF2 = OFF;
+	EDIF_INPUT_USE_LMF1 = OFF;
+	EDIF_OUTPUT_GND = GND;
+	EDIF_OUTPUT_VCC = VCC;
+	EDIF_INPUT_GND = GND;
+	EDIF_INPUT_VCC = VCC;
+	EDIF_OUTPUT_EDC_FILE = *.edc;
+	EDIF_INPUT_LMF2 = *.lmf;
+	EDIF_INPUT_LMF1 = *.lmf;
+	VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
+	VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
+	VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
+	EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
+	VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
+	VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
+	VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
+	VHDL_WRITER_VERSION = VHDL87;
+	VHDL_READER_VERSION = VHDL87;
+	SYNOPSYS_MAPPING_EFFORT = MEDIUM;
+	SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
+	SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
+	SYNOPSYS_DESIGNWARE = OFF;
+	SYNOPSYS_COMPILER = DESIGN;
+	USE_SYNOPSYS_SYNTHESIS = OFF;
+	VHDL_NETLIST_WRITER = OFF;
+	VERILOG_NETLIST_WRITER = OFF;
+	XNF_GENERATE_AHDL_TDX_FILE = ON;
+	XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
+	XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
+	EDIF_OUTPUT_VERSION = 200;
+	EDIF_NETLIST_WRITER = OFF;
+END;
+
+CUSTOM_DESIGN_DOCTOR_RULES
+BEGIN
+	MASTER_RESET = OFF;
+	EXPANDER_NETWORKS = ON;
+	RACE_CONDITIONS = ON;
+	DELAY_CHAINS = ON;
+	ASYNCHRONOUS_INPUTS = ON;
+	PRESET_CLEAR_NETWORKS = ON;
+	STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
+	STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
+	MULTI_CLOCK_NETWORKS = ON;
+	MULTI_LEVEL_CLOCKS = ON;
+	GATED_CLOCKS = ON;
+	RIPPLE_CLOCKS = ON;
+END;
+
+SIMULATOR_CONFIGURATION
+BEGIN
+	BIDIR_PIN = STRONG;
+	END_TIME = 0.0ns;
+	START_TIME = 0.0ns;
+	GLITCH_TIME = 0.0ns;
+	GLITCH = OFF;
+	OSCILLATION_TIME = 0.0ns;
+	OSCILLATION = OFF;
+	CHECK_OUTPUTS = OFF;
+	SETUP_HOLD = OFF;
+	USE_DEVICE = OFF;
+END;
+
+TIMING_ANALYZER_CONFIGURATION
+BEGIN
+	CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
+	LIST_PATH_FREQUENCY = 10MHz;
+	LIST_PATH_COUNT = 10;
+	REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
+	INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
+	INCLUDE_PATHS_LESS_THAN = OFF;
+	INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
+	INCLUDE_PATHS_GREATER_THAN = OFF;
+	DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
+	CELL_WIDTH = 18;
+	LIST_ONLY_LONGEST_PATH = ON;
+	CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
+	CUT_OFF_IO_PIN_FEEDBACK = ON;
+	AUTO_RECALCULATE = OFF;
+	ANALYSIS_MODE = DELAY_MATRIX;
+END;
+
+OTHER_CONFIGURATION
+BEGIN
+	LAST_MAXPLUS2_VERSION = 10.0;
+	ROW_PINS_LCELL_INSERT = ON;
+	CARRY_OUT_PINS_LCELL_INSERT = OFF;
+	NORMAL_LCELL_INSERT = ON;
+	EXPLICIT_FAMILY = 1;
+	ORIGINAL_MAXPLUS2_VERSION = 8.0;
+	LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
+	FLEX_10K_52_COLUMNS = 40;
+	DEFAULT_9K_EXP_PER_LCELL = 1/2;
+	LCELLS_PER_ROW_PERCENT = 100;
+	FAN_IN_PER_LCELL_PERCENT = 100;
+	EXP_PER_LCELL_PERCENT = 100;
+	ROW_PINS_PERCENT = 50;
+	COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
+BEGIN
+	REGISTER_OPTIMIZATION = ON;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = ON;
+	SUBFACTOR_EXTRACTION = ON;
+	REFACTORIZATION = ON;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = ON;
+	REDUCE_LOGIC = ON;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	FAST_IO = OFF;
+	IGNORE_SOFT_BUFFERS = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = OFF;
+	XOR_SYNTHESIS = ON;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = FULL;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
+BEGIN
+	TURBO_BIT = ON;
+	REGISTER_OPTIMIZATION = ON;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = ON;
+	SUBFACTOR_EXTRACTION = ON;
+	REFACTORIZATION = ON;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = ON;
+	REDUCE_LOGIC = ON;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	FAST_IO = OFF;
+	IGNORE_SOFT_BUFFERS = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	XOR_SYNTHESIS = ON;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = FULL;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
+BEGIN
+	REGISTER_OPTIMIZATION = OFF;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = OFF;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = OFF;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	FAST_IO = OFF;
+	IGNORE_SOFT_BUFFERS = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = ON;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = FULL;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
+BEGIN
+	REGISTER_OPTIMIZATION = ON;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = ON;
+	SUBFACTOR_EXTRACTION = ON;
+	REFACTORIZATION = ON;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = ON;
+	REDUCE_LOGIC = ON;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	IGNORE_SOFT_BUFFERS = ON;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = OFF;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = FULL;
+	CARRY_CHAIN_LENGTH = 32;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN_LENGTH = 2;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
+BEGIN
+	REGISTER_OPTIMIZATION = ON;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = ON;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = ON;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	FAST_IO = OFF;
+	IGNORE_SOFT_BUFFERS = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = OFF;
+	XOR_SYNTHESIS = ON;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = FULL;
+	CARRY_CHAIN_LENGTH = -1;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN_LENGTH = -1;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
+BEGIN
+	REGISTER_OPTIMIZATION = ON;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = ON;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = ON;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	FAST_IO = OFF;
+	IGNORE_SOFT_BUFFERS = OFF;
+	PARALLEL_EXPANDERS = ON;
+	TURBO_BIT = ON;
+	XOR_SYNTHESIS = ON;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = FULL;
+	CARRY_CHAIN_LENGTH = -1;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN_LENGTH = -1;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
+BEGIN
+	REGISTER_OPTIMIZATION = OFF;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = OFF;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = OFF;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	FAST_IO = OFF;
+	IGNORE_SOFT_BUFFERS = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = ON;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = FULL;
+	CARRY_CHAIN_LENGTH = -1;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN_LENGTH = -1;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
+BEGIN
+	REGISTER_OPTIMIZATION = ON;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = ON;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = ON;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	IGNORE_SOFT_BUFFERS = ON;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = OFF;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = FULL;
+	CARRY_CHAIN_LENGTH = 32;
+	CARRY_CHAIN = AUTO;
+	CASCADE_CHAIN_LENGTH = 2;
+	CASCADE_CHAIN = AUTO;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
+BEGIN
+	REGISTER_OPTIMIZATION = OFF;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = OFF;
+	MULTI_LEVEL_FACTORING = OFF;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = OFF;
+	DECOMPOSE_GATES = OFF;
+	SOFT_BUFFER_INSERTION = OFF;
+	FAST_IO = OFF;
+	IGNORE_SOFT_BUFFERS = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = OFF;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = PARTIAL;
+	CARRY_CHAIN_LENGTH = -1;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN_LENGTH = -1;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
+BEGIN
+	REGISTER_OPTIMIZATION = OFF;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = OFF;
+	MULTI_LEVEL_FACTORING = OFF;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = OFF;
+	DECOMPOSE_GATES = OFF;
+	SOFT_BUFFER_INSERTION = OFF;
+	FAST_IO = OFF;
+	IGNORE_SOFT_BUFFERS = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = ON;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = PARTIAL;
+	CARRY_CHAIN_LENGTH = -1;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN_LENGTH = -1;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
+BEGIN
+	REGISTER_OPTIMIZATION = OFF;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = OFF;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = OFF;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = OFF;
+	FAST_IO = OFF;
+	IGNORE_SOFT_BUFFERS = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = ON;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = PARTIAL;
+	CARRY_CHAIN_LENGTH = -1;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN_LENGTH = -1;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
+BEGIN
+	REGISTER_OPTIMIZATION = OFF;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = OFF;
+	MULTI_LEVEL_FACTORING = OFF;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = OFF;
+	DECOMPOSE_GATES = OFF;
+	SOFT_BUFFER_INSERTION = ON;
+	IGNORE_SOFT_BUFFERS = ON;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = OFF;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = PARTIAL;
+	CARRY_CHAIN_LENGTH = 32;
+	CARRY_CHAIN = MANUAL;
+	CASCADE_CHAIN_LENGTH = 2;
+	CASCADE_CHAIN = MANUAL;
+END;
+

fw/src/max/SP037032.TDF

@@ -0,0 +1,288 @@
+TITLE "SINC_controller";
+
+Constant HDD_TYPE = 1;
+
+SUBDESIGN SP037032
+	(
+	EPM_RES		: INPUT;
+	HD_WE[2..1]	: OUTPUT;
+	HD_OE[2..1]	: OUTPUT;
+	HD_CS[2..1]	: OUTPUT;
+	HD_CSS[2..1]: OUTPUT;
+
+	CLK_WG		: OUTPUT;
+	RDATA		: INPUT;
+	QDAT		: OUTPUT;
+	RDAT		: OUTPUT;
+
+	D0			: INPUT;
+	MA0			: INPUT;
+	STE			: INPUT;
+	WSTB,RSTB	: INPUT;
+
+	/WR			: INPUT;
+	/RD			: INPUT;
+	HDD_CS		: INPUT;
+
+	/MR,/IO		: INPUT;
+	CLKZZ		: OUTPUT;
+
+--	/RTSB,
+	/DTRB		: INPUT;
+
+--	10K_D0		: OUTPUT;
+--	10K_CLK		: OUTPUT;
+	/CONFIG		: OUTPUT;
+	CNF_ON		: INPUT;
+	TG42_OUT	: OUTPUT;
+	TG42_IN		: INPUT;
+
+	CLK_PRC		: OUTPUT;
+
+	MA7			: INPUT;
+
+--	/WRH		: INPUT;
+	/WRH		: OUTPUT;
+
+--	/RDH		: OUTPUT; -> NA HD_CS1
+
+	)
+VARIABLE
+
+	CT[2..0]	: DFF;
+	CLKZZ1		: NODE;
+	STWG[2..0]	: DFF;
+	WGR[4..0]	: DFF;
+	CT_WG		: NODE;
+	CT_WG1		: NODE;
+	TB_WG		: NODE;
+	CODE[4..0]	: DFF;
+	TURBING		: NODE;
+	RDAT_X		: NODE;
+	HD_CS_CLK	: NODE;
+	MXX			: NODE;
+	10K_D0		: NODE;
+	10K_CLK		: NODE;
+BEGIN
+
+--	====== Oscillator ==========
+	TG42_OUT 	= EXP(TG42_IN);
+--	TG42_OUT 	= !(TG42_IN);
+
+--	tG42_OUT 	= LCELL(EXP(TG42_IN));
+--	============================
+
+--	====== FLEX Loading ========
+
+	10K_CLK		= LCELL((/MR or /WR or CNF_ON) &
+--						(/IO or /WR or HDD_CS or !CNF_ON) &
+						(/MR or /RD or HDD_CS or !CNF_ON));
+	CODE[].clk	= 10K_CLK;
+	CODE[].clrn	= /CONFIG & (/IO or /RD);
+
+IF !CNF_ON THEN
+	CODE[].d	= (CODE[3..0],(CODE2 xor 10K_D0));
+ELSE
+	CODE[].d	= (CODE[3..0],!CODE0);
+END IF;
+
+	10K_D0		= LCELL(CODE4 xor D0);
+
+--	============================
+
+--	======= CP FRQ =============
+
+	CT[].clk	= (TG42_IN xor !CT1);
+	CT[].d		= CT[] + 1;
+
+--	IF CT[] == 2 THEN
+--		CT[].d		= GND;
+--	ELSE
+--		CT[].d		= CT[] + 1;
+--	END IF;
+
+	CLKZZ		= TRI(CT1,!CNF_ON);
+
+--	============================
+
+--	========	FDD controller	==================
+
+	TURBING		= EXP(EXP(TURBING & !WSTB & !RSTB) & !STE & !/DTRB);
+--	TURBING		= GND;
+--	TB_WG		= /DTRB or TURBING;
+	TB_WG		= /DTRB;
+
+--	CT_WG		= TFF(VCC,(CT1 xor (CT_WG & (/DTRB or TURBING))),,);
+	CT_WG		= TFF(VCC,(CT1 xor (CT_WG & TURBING)),,);
+
+	CT_WG1		= TFF(VCC,(CT1 xor (CT_WG1 & /DTRB)),,);
+--	STWG[].clk	= LCELL(CT_WG xor STWG2);
+
+	STWG[].clk	= (CT_WG xor STWG2);
+	STWG[].d	= STWG[] + 1;
+	CLK_WG		= STWG2;
+
+	CLK_PRC		= STWG0;
+--	CLK_PRC		= STWG1;
+
+	WGR[].clk	= CT_WG1;
+	IF !RDAT THEN
+		TABLE WGR[3..0] => WGR[3..0].d;
+			0 => 4; 1 => 5; 2 => 4; 3 => 5;
+			4 => 6; 5 => 7; 6 => 8; 7 => 8;
+			8 => 9; 9 => 9; 10 => 10; 11 => 11;
+		   12 => 12; 13 => 13; 14 => 14; 15 => 15;
+		END TABLE;
+		WGR4.d	= WGR4;
+
+--		IF WGR[3..0] == 0 THEN
+--			WGR[3..0].d		= 3;
+--			WGR4.d			= WGR4;
+--		ELSE
+--			WGR[].d			= WGR[] + 1;
+--		END IF;
+	ELSE
+		IF WGR[3..0] == 0 THEN
+			WGR[3..0].d		= 3;
+			WGR4.d			= WGR4;
+		ELSE
+			WGR[].d			= WGR[] + 1;
+		END IF;
+	END IF;
+
+
+--	RDAT_X	= DFF(RDATA,CT_WG1,,);
+	RDAT_X	= EXP(EXP(RDAT_X & EXP(!RDATA & !CT_WG1)) & EXP(RDATA & !CT_WG1));
+
+IF !CNF_ON THEN
+	QDAT	= 10K_CLK;
+	RDAT	= 10K_D0;
+ELSE
+	QDAT	= WGR4;
+	RDAT	= DFF((RDAT_X or !DFF(RDAT_X,CT_WG1,,)),CT_WG1,,);
+END IF;
+
+--	==============================================
+
+--	========= HDD Controller =========
+
+IF HDD_TYPE == 0 THEN
+
+	MXX	= CODE0;
+
+	HD_CS2		= LCELL(HDD_CS or EXP(!HDD_CS));
+
+	HD_CS_CLK	= HD_CS2 or EXP(EXP(EXP(EXP(EXP(!HD_CS2)))));
+
+	HD_CSS1		= HDD_CS or MA7;
+	HD_CSS2		= HDD_CS or !MA7;
+
+
+	HD_CS1		= (/RD or  MA0 or HD_CS_CLK or /IO) &
+					(/RD or CODE0 or HDD_CS or /MR) ;	% /RDH %
+
+	/WRH 		= (/WR or !MA0 or HD_CS_CLK or /IO);	% /WRH %
+
+
+	HD_OE1		= (HDD_CS or /RD or !MA0 or /IO) &
+					(HDD_CS or /RD or !CODE0 or /MR);
+
+	HD_WE1		= HDD_CS or /RD or (/IO & /MR);
+
+
+	HD_OE2		= HDD_CS or /WR or !MA0;
+
+
+	HD_WE2		= HDD_CS or /WR or MA0 or /IO;
+
+--	======= RECONFIG =========
+
+	/CONFIG	= LCELL(EPM_RES & (HDD_CS or /MR or /WR));
+
+ELSE
+
+	MXX	= CODE0;
+
+	HD_CS2		= LCELL(HDD_CS or EXP(!HDD_CS) or /WRH);
+
+	HD_CS_CLK	= HDD_CS or EXP(EXP(EXP(EXP(EXP(!HDD_CS)))));
+
+	HD_CSS1		= HDD_CS or MA7;
+	HD_CSS2		= HDD_CS or !MA7;
+
+	HD_CS1		= HDD_CS or /WR;
+
+	HD_OE1		= (HD_CS_CLK or /RD or !MA0 or /IO) &
+				   (HD_CS_CLK or /WR or !/WRH or !MA0 or /IO) &
+					(HDD_CS or /RD or !CODE0 or /MR);
+
+	HD_WE1		= (HDD_CS or (/RD & /WR) or /IO);
+
+
+--	HD_OE1		= (HDD_CS or /RD or !MA0) or (HDD_CS or /RD or );
+
+--	HD_WE1		= (HDD_CS or /RD or MA0 or /IO);
+
+
+	HD_WE2		= (/WR or !MA0 or HD_CS_CLK or /IO);	% /WRH %
+
+	HD_OE2		= (/RD or  MA0 or HD_CS_CLK or /IO) &
+					(/RD or CODE0 or HDD_CS or /MR) ;	% /RDH %
+
+
+	/WRH = DFF((/WRH or !MA0),(/IO or /WR or HDD_CS),(/IO or /RD),);
+
+%
+	HD_CS2		= LCELL(HDD_CS or EXP(!HDD_CS));
+
+	HD_CS_CLK	= EXP(EXP(EXP(EXP(EXP(!HD_CS2)))));
+
+	HD_CS1		= VCC;
+
+	HD_CSS1		= HDD_CS or MA7;
+	HD_CSS2		= HDD_CS or !MA7;
+
+	HD_OE1		= VCC;
+	HD_WE1		= VCC;
+
+	HD_OE2		= (/RD or HD_CS_CLK or /IO);
+	HD_WE2		= (/WR or HD_CS_CLK or /IO);
+%
+
+%
+	TABLE
+
+	(HDD_CS,/RD,/WR,/IO,/MR,MA7,MXX) => (HD_CS[] ,HD_CSS[] ,HD_OE[], HD_WE[]);
+	(VCC   ,X  ,X  ,X  ,X  ,X  ,X  ) => (VCC,VCC ,VCC,VCC  ,VCC,VCC, VCC,VCC);
+	(GND   ,X  ,X  ,VCC,VCC,X  ,X  ) => (VCC,VCC ,VCC,VCC  ,VCC,VCC, VCC,VCC);
+	(GND   ,X  ,X  ,GND,GND,X  ,X  ) => (VCC,VCC ,VCC,VCC  ,VCC,VCC, VCC,VCC);
+	(GND   ,VCC,VCC,GND,VCC,X  ,X  ) => (VCC,VCC ,VCC,VCC  ,VCC,VCC, VCC,VCC);
+	(GND   ,GND,GND,GND,VCC,X  ,X  ) => (VCC,VCC ,VCC,VCC  ,VCC,VCC, VCC,VCC);
+	(GND   ,VCC,VCC,VCC,GND,X  ,X  ) => (VCC,VCC ,VCC,VCC  ,VCC,VCC, VCC,VCC);
+	(GND   ,GND,GND,VCC,GND,X  ,X  ) => (VCC,VCC ,VCC,VCC  ,VCC,VCC, VCC,VCC);
+
+	(GND   ,X  ,X  ,VCC,GND,GND,X  ) => (VCC,VCC ,VCC,VCC  ,VCC,VCC, VCC,VCC);
+
+	(GND   ,GND,VCC,GND,VCC,VCC,X  ) => (GND,VCC ,GND,VCC  ,GND,VCC, VCC,VCC);
+	(GND   ,VCC,GND,GND,VCC,VCC,X  ) => (GND,VCC ,GND,VCC  ,VCC,VCC, GND,VCC);
+
+	(GND   ,GND,VCC,GND,VCC,GND,X  ) => (GND,VCC ,VCC,GND  ,GND,VCC, VCC,VCC);
+	(GND   ,VCC,GND,GND,VCC,GND,X  ) => (GND,VCC ,VCC,GND  ,VCC,VCC, GND,VCC);
+
+	(GND   ,GND,VCC,VCC,GND,VCC,GND) => (GND,VCC ,VCC,GND  ,GND,VCC, VCC,GND);
+	(GND   ,GND,VCC,VCC,GND,VCC,VCC) => (GND,VCC ,VCC,VCC  ,VCC,GND, VCC,VCC);
+
+	(GND   ,VCC,GND,VCC,GND,VCC,GND) => (VCC,GND ,VCC,VCC  ,VCC,VCC, VCC,GND);
+	(GND   ,VCC,GND,VCC,GND,VCC,VCC) => (VCC,GND ,VCC,GND  ,VCC,GND, GND,VCC);
+
+	END TABLE;
+%
+--	======= RECONFIG =========
+
+	/CONFIG	= LCELL(EPM_RES & (HDD_CS or /MR or MA7 or /WR));
+
+END IF;
+
+
+END;
+

fw/src/max/SP047032.ACF

@@ -0,0 +1,620 @@
+--
+--  Copyright (C) 1988-2000 Altera Corporation
+--  Any megafunction design, and related net list (encrypted or decrypted),
+--  support information, device programming or simulation file, and any other
+--  associated documentation or information provided by Altera or a partner
+--  under Altera's Megafunction Partnership Program may be used only to
+--  program PLD devices (but not masked PLD devices) from Altera.  Any other
+--  use of such megafunction design, net list, support information, device
+--  programming or simulation file, or any other related documentation or
+--  information is prohibited for any other purpose, including, but not
+--  limited to modification, reverse engineering, de-compiling, or use with
+--  any other silicon devices, unless such use is explicitly licensed under
+--  a separate agreement with Altera or a megafunction partner.  Title to
+--  the intellectual property, including patents, copyrights, trademarks,
+--  trade secrets, or maskworks, embodied in any such megafunction design,
+--  net list, support information, device programming or simulation file, or
+--  any other related documentation or information provided by Altera or a
+--  megafunction partner, remains with Altera, the megafunction partner, or
+--  their respective licensors.  No other licenses, including any licenses
+--  needed under any third party's intellectual property, are provided herein.
+--
+CHIP sp047032
+BEGIN
+	DEVICE = EPM7032LC44-12;
+	|/WRH :	OUTPUT_PIN = 24;
+	|/RD :	PIN = 32;
+	|MA7 :	INPUT_PIN = 36;
+	|/RTSB :	INPUT_PIN = 33;
+	|CLK_PRC :	OUTPUT_PIN = 27;
+	|/DTRB :	INPUT_PIN = 34;
+	|RDAT :	OUTPUT_PIN = 16;
+	|RDATA :	INPUT_PIN = 17;
+	|MA0 :	INPUT_PIN = 39;
+	|TG42_IN :	INPUT_PIN = 43;
+	|TG42_OUT :	OUTPUT_PIN = 41;
+	|/CONFIG :	OUTPUT_PIN = 40;
+	|10K_CLK :	OUTPUT_PIN = 38;
+	|10K_D0 :	OUTPUT_PIN = 37;
+	|CLKZZ :	OUTPUT_PIN = 31;
+	|/MR :	INPUT_PIN = 28;
+	|/IO :	INPUT_PIN = 29;
+	|HDD_CS :	INPUT_PIN = 26;
+	|/WR :	INPUT_PIN = 25;
+	|RSTB :	INPUT_PIN = 21;
+	|WSTB :	INPUT_PIN = 20;
+	|STE :	INPUT_PIN = 19;
+	|QDAT :	OUTPUT_PIN = 14;
+	|CLK_WG :	OUTPUT_PIN = 13;
+	|HD_CSS2 :	OUTPUT_PIN = 12;
+	|HD_CSS1 :	OUTPUT_PIN = 11;
+	|HD_OE1 :	OUTPUT_PIN = 8;
+	|HD_CS1 :	OUTPUT_PIN = 9;
+	|HD_CS2 :	OUTPUT_PIN = 7;
+	|HD_WE1 :	OUTPUT_PIN = 6;
+	|HD_OE2 :	OUTPUT_PIN = 5;
+	|HD_WE2 :	OUTPUT_PIN = 4;
+	|D0 :	INPUT_PIN = 18;
+	|EPM_RES :	INPUT_PIN = 1;
+	|CNF_ON :	INPUT_PIN = 44;
+END;
+
+DEFAULT_DEVICES
+BEGIN
+	AUTO_DEVICE = EPM7096QC100-7;
+	AUTO_DEVICE = EPM7096LC84-7;
+	AUTO_DEVICE = EPM7096LC68-7;
+	AUTO_DEVICE = EPM7064QC100-7;
+	AUTO_DEVICE = EPM7064LC84-7;
+	AUTO_DEVICE = EPM7064LC68-7;
+	AUTO_DEVICE = EPM7064TC44-7;
+	AUTO_DEVICE = EPM7064LC44-7;
+	AUTO_DEVICE = EPM7032VTC44-12;
+	AUTO_DEVICE = EPM7032VLC44-12;
+	AUTO_DEVICE = EPM7032TC44-6;
+	AUTO_DEVICE = EPM7032QC44-7;
+	AUTO_DEVICE = EPM7032LC44-6;
+	ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
+END;
+
+TIMING_POINT
+BEGIN
+	DEVICE_FOR_TIMING_SYNTHESIS = EPM7032LC44-12;
+	MAINTAIN_STABLE_SYNTHESIS = OFF;
+	CUT_ALL_CLEAR_PRESET = ON;
+	CUT_ALL_BIDIR = ON;
+END;
+
+IGNORED_ASSIGNMENTS
+BEGIN
+	FIT_IGNORE_TIMING = OFF;
+	DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
+	IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
+	IGNORE_DEVICE_ASSIGNMENTS = OFF;
+	IGNORE_LC_ASSIGNMENTS = OFF;
+	IGNORE_PIN_ASSIGNMENTS = OFF;
+	IGNORE_CHIP_ASSIGNMENTS = OFF;
+	IGNORE_TIMING_ASSIGNMENTS = OFF;
+	IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
+	IGNORE_CLIQUE_ASSIGNMENTS = OFF;
+END;
+
+LOGIC_OPTIONS
+BEGIN
+	|/WRH :	TURBO_BIT = OFF;
+	|10K_CLK :	TURBO_BIT = OFF;
+	|10K_D0 :	TURBO_BIT = OFF;
+	|/CONFIG :	TURBO_BIT = OFF;
+	|HD_CSS1 :	TURBO_BIT = OFF;
+	|HD_CSS2 :	TURBO_BIT = OFF;
+	|HD_CS1 :	TURBO_BIT = OFF;
+	|HD_CS2 :	TURBO_BIT = OFF;
+	|HD_OE1 :	TURBO_BIT = OFF;
+	|HD_OE2 :	TURBO_BIT = OFF;
+	|HD_WE1 :	TURBO_BIT = OFF;
+	|HD_WE2 :	TURBO_BIT = OFF;
+END;
+
+GLOBAL_PROJECT_DEVICE_OPTIONS
+BEGIN
+	MAX7000B_ENABLE_VREFB = OFF;
+	MAX7000B_ENABLE_VREFA = OFF;
+	MAX7000B_VCCIO_IOBANK2 = 3.3V;
+	MAX7000B_VCCIO_IOBANK1 = 3.3V;
+	CONFIG_EPROM_PULLUP_RESISTOR = ON;
+	CONFIG_EPROM_USER_CODE = FFFFFFFF;
+	FLEX_CONFIGURATION_EPROM = AUTO;
+	MAX7000AE_ENABLE_JTAG = ON;
+	MAX7000AE_USER_CODE = FFFFFFFF;
+	SECURITY_BIT = ON;
+	FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
+	FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
+	FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
+	FLEX6000_ENABLE_JTAG = OFF;
+	CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
+	MULTIVOLT_IO = OFF;
+	MAX7000S_ENABLE_JTAG = ON;
+	FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
+	MAX7000S_USER_CODE = FFFF;
+	CONFIG_SCHEME_10K = PASSIVE_SERIAL;
+	FLEX10K_JTAG_USER_CODE = 7F;
+	ENABLE_INIT_DONE_OUTPUT = OFF;
+	ENABLE_CHIP_WIDE_OE = OFF;
+	ENABLE_CHIP_WIDE_RESET = OFF;
+	nCEO = UNRESERVED;
+	CLKUSR = UNRESERVED;
+	ADD17 = UNRESERVED;
+	ADD16 = UNRESERVED;
+	ADD15 = UNRESERVED;
+	ADD14 = UNRESERVED;
+	ADD13 = UNRESERVED;
+	ADD0_TO_ADD12 = UNRESERVED;
+	SDOUT = RESERVED_DRIVES_OUT;
+	RDCLK = UNRESERVED;
+	RDYnBUSY = UNRESERVED;
+	nWS_nRS_nCS_CS = UNRESERVED;
+	DATA1_TO_DATA7 = UNRESERVED;
+	DATA0 = RESERVED_TRI_STATED;
+	FLEX8000_ENABLE_JTAG = OFF;
+	CONFIG_SCHEME = ACTIVE_SERIAL;
+	DISABLE_TIME_OUT = OFF;
+	ENABLE_DCLK_OUTPUT = OFF;
+	RELEASE_CLEARS = OFF;
+	AUTO_RESTART = OFF;
+	USER_CLOCK = OFF;
+	RESERVED_PINS_PERCENT = 0;
+	RESERVED_LCELLS_PERCENT = 0;
+END;
+
+GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
+BEGIN
+	AUTO_GLOBAL_OE = OFF;
+	AUTO_GLOBAL_PRESET = OFF;
+	AUTO_GLOBAL_CLEAR = OFF;
+	AUTO_GLOBAL_CLOCK = OFF;
+	OPTIMIZE_FOR_SPEED = 0;
+	DEVICE_FAMILY = MAX7000;
+	MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
+	AUTO_IMPLEMENT_IN_EAB = OFF;
+	AUTO_OPEN_DRAIN_PINS = ON;
+	ONE_HOT_STATE_MACHINE_ENCODING = OFF;
+	AUTO_REGISTER_PACKING = OFF;
+	STYLE = NORMAL;
+	AUTO_FAST_IO = OFF;
+	MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
+END;
+
+COMPILER_PROCESSING_CONFIGURATION
+BEGIN
+	FITTER_SETTINGS = ADVANCED;
+	SMART_RECOMPILE = ON;
+	PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
+	GENERATE_AHDL_TDO_FILE = OFF;
+	RPT_FILE_USER_ASSIGNMENTS = ON;
+	RPT_FILE_LCELL_INTERCONNECT = ON;
+	RPT_FILE_HIERARCHY = ON;
+	RPT_FILE_EQUATIONS = ON;
+	LINKED_SNF_EXTRACTOR = OFF;
+	OPTIMIZE_TIMING_SNF = OFF;
+	TIMING_SNF_EXTRACTOR = ON;
+	FUNCTIONAL_SNF_EXTRACTOR = OFF;
+	DESIGN_DOCTOR_RULES = EPLD;
+	DESIGN_DOCTOR = OFF;
+END;
+
+COMPILER_INTERFACES_CONFIGURATION
+BEGIN
+	VHDL_FLATTEN_BUS = OFF;
+	VERILOG_FLATTEN_BUS = OFF;
+	NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
+	EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
+	EDIF_BUS_DELIMITERS = [];
+	EDIF_FLATTEN_BUS = OFF;
+	EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
+	EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
+	EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
+	EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
+	EDIF_OUTPUT_USE_EDC = OFF;
+	EDIF_INPUT_USE_LMF2 = OFF;
+	EDIF_INPUT_USE_LMF1 = OFF;
+	EDIF_OUTPUT_GND = GND;
+	EDIF_OUTPUT_VCC = VCC;
+	EDIF_INPUT_GND = GND;
+	EDIF_INPUT_VCC = VCC;
+	EDIF_OUTPUT_EDC_FILE = *.edc;
+	EDIF_INPUT_LMF2 = *.lmf;
+	EDIF_INPUT_LMF1 = *.lmf;
+	VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
+	VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
+	VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
+	EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
+	VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
+	VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
+	VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
+	VHDL_WRITER_VERSION = VHDL87;
+	VHDL_READER_VERSION = VHDL87;
+	SYNOPSYS_MAPPING_EFFORT = MEDIUM;
+	SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
+	SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
+	SYNOPSYS_DESIGNWARE = OFF;
+	SYNOPSYS_COMPILER = DESIGN;
+	USE_SYNOPSYS_SYNTHESIS = OFF;
+	VHDL_NETLIST_WRITER = OFF;
+	VERILOG_NETLIST_WRITER = OFF;
+	XNF_GENERATE_AHDL_TDX_FILE = ON;
+	XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
+	XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
+	EDIF_OUTPUT_VERSION = 200;
+	EDIF_NETLIST_WRITER = OFF;
+END;
+
+CUSTOM_DESIGN_DOCTOR_RULES
+BEGIN
+	MASTER_RESET = OFF;
+	EXPANDER_NETWORKS = ON;
+	RACE_CONDITIONS = ON;
+	DELAY_CHAINS = ON;
+	ASYNCHRONOUS_INPUTS = ON;
+	PRESET_CLEAR_NETWORKS = ON;
+	STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
+	STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
+	MULTI_CLOCK_NETWORKS = ON;
+	MULTI_LEVEL_CLOCKS = ON;
+	GATED_CLOCKS = ON;
+	RIPPLE_CLOCKS = ON;
+END;
+
+SIMULATOR_CONFIGURATION
+BEGIN
+	BIDIR_PIN = STRONG;
+	END_TIME = 0.0ns;
+	START_TIME = 0.0ns;
+	GLITCH_TIME = 0.0ns;
+	GLITCH = OFF;
+	OSCILLATION_TIME = 0.0ns;
+	OSCILLATION = OFF;
+	CHECK_OUTPUTS = OFF;
+	SETUP_HOLD = OFF;
+	USE_DEVICE = OFF;
+END;
+
+TIMING_ANALYZER_CONFIGURATION
+BEGIN
+	CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF;
+	LIST_PATH_FREQUENCY = 10MHz;
+	LIST_PATH_COUNT = 10;
+	REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS;
+	INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
+	INCLUDE_PATHS_LESS_THAN = OFF;
+	INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
+	INCLUDE_PATHS_GREATER_THAN = OFF;
+	DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
+	CELL_WIDTH = 18;
+	LIST_ONLY_LONGEST_PATH = ON;
+	CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
+	CUT_OFF_IO_PIN_FEEDBACK = ON;
+	AUTO_RECALCULATE = OFF;
+	ANALYSIS_MODE = DELAY_MATRIX;
+END;
+
+OTHER_CONFIGURATION
+BEGIN
+	LAST_MAXPLUS2_VERSION = 10.0;
+	LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
+	ROW_PINS_LCELL_INSERT = ON;
+	CARRY_OUT_PINS_LCELL_INSERT = OFF;
+	NORMAL_LCELL_INSERT = ON;
+	EXPLICIT_FAMILY = 1;
+	FLEX_10K_52_COLUMNS = 40;
+	DEFAULT_9K_EXP_PER_LCELL = 1/2;
+	LCELLS_PER_ROW_PERCENT = 100;
+	FAN_IN_PER_LCELL_PERCENT = 100;
+	EXP_PER_LCELL_PERCENT = 100;
+	ROW_PINS_PERCENT = 50;
+	ORIGINAL_MAXPLUS2_VERSION = 8.0;
+	COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1";
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
+BEGIN
+	REGISTER_OPTIMIZATION = ON;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = ON;
+	SUBFACTOR_EXTRACTION = ON;
+	REFACTORIZATION = ON;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = ON;
+	REDUCE_LOGIC = ON;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	FAST_IO = OFF;
+	IGNORE_SOFT_BUFFERS = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = OFF;
+	XOR_SYNTHESIS = ON;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = FULL;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
+BEGIN
+	TURBO_BIT = ON;
+	REGISTER_OPTIMIZATION = ON;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = ON;
+	SUBFACTOR_EXTRACTION = ON;
+	REFACTORIZATION = ON;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = ON;
+	REDUCE_LOGIC = ON;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	FAST_IO = OFF;
+	IGNORE_SOFT_BUFFERS = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	XOR_SYNTHESIS = ON;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = FULL;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
+BEGIN
+	REGISTER_OPTIMIZATION = OFF;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = OFF;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = OFF;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	FAST_IO = OFF;
+	IGNORE_SOFT_BUFFERS = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = ON;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = FULL;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
+BEGIN
+	REGISTER_OPTIMIZATION = ON;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = ON;
+	SUBFACTOR_EXTRACTION = ON;
+	REFACTORIZATION = ON;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = ON;
+	REDUCE_LOGIC = ON;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	IGNORE_SOFT_BUFFERS = ON;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = OFF;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = FULL;
+	CARRY_CHAIN_LENGTH = 32;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN_LENGTH = 2;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
+BEGIN
+	REGISTER_OPTIMIZATION = ON;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = ON;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = ON;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	FAST_IO = OFF;
+	IGNORE_SOFT_BUFFERS = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = OFF;
+	XOR_SYNTHESIS = ON;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = FULL;
+	CARRY_CHAIN_LENGTH = -1;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN_LENGTH = -1;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
+BEGIN
+	REGISTER_OPTIMIZATION = ON;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = ON;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = ON;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	FAST_IO = OFF;
+	IGNORE_SOFT_BUFFERS = OFF;
+	PARALLEL_EXPANDERS = ON;
+	TURBO_BIT = ON;
+	XOR_SYNTHESIS = ON;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = FULL;
+	CARRY_CHAIN_LENGTH = -1;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN_LENGTH = -1;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
+BEGIN
+	REGISTER_OPTIMIZATION = OFF;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = OFF;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = OFF;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	FAST_IO = OFF;
+	IGNORE_SOFT_BUFFERS = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = ON;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = FULL;
+	CARRY_CHAIN_LENGTH = -1;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN_LENGTH = -1;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
+BEGIN
+	REGISTER_OPTIMIZATION = ON;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = ON;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = ON;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = ON;
+	IGNORE_SOFT_BUFFERS = ON;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = OFF;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = FULL;
+	CARRY_CHAIN_LENGTH = 32;
+	CARRY_CHAIN = AUTO;
+	CASCADE_CHAIN_LENGTH = 2;
+	CASCADE_CHAIN = AUTO;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
+BEGIN
+	REGISTER_OPTIMIZATION = OFF;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = OFF;
+	MULTI_LEVEL_FACTORING = OFF;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = OFF;
+	DECOMPOSE_GATES = OFF;
+	SOFT_BUFFER_INSERTION = OFF;
+	FAST_IO = OFF;
+	IGNORE_SOFT_BUFFERS = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = OFF;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = PARTIAL;
+	CARRY_CHAIN_LENGTH = -1;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN_LENGTH = -1;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
+BEGIN
+	REGISTER_OPTIMIZATION = OFF;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = OFF;
+	MULTI_LEVEL_FACTORING = OFF;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = OFF;
+	DECOMPOSE_GATES = OFF;
+	SOFT_BUFFER_INSERTION = OFF;
+	FAST_IO = OFF;
+	IGNORE_SOFT_BUFFERS = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = ON;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = PARTIAL;
+	CARRY_CHAIN_LENGTH = -1;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN_LENGTH = -1;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
+BEGIN
+	REGISTER_OPTIMIZATION = OFF;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = ON;
+	MULTI_LEVEL_FACTORING = OFF;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = OFF;
+	DECOMPOSE_GATES = ON;
+	SOFT_BUFFER_INSERTION = OFF;
+	FAST_IO = OFF;
+	IGNORE_SOFT_BUFFERS = OFF;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = ON;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = PARTIAL;
+	CARRY_CHAIN_LENGTH = -1;
+	CARRY_CHAIN = IGNORE;
+	CASCADE_CHAIN_LENGTH = -1;
+	CASCADE_CHAIN = IGNORE;
+END;
+
+DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
+BEGIN
+	REGISTER_OPTIMIZATION = OFF;
+	USE_LPM_FOR_AHDL_OPERATORS = OFF;
+	RESYNTHESIZE_NETWORK = OFF;
+	MULTI_LEVEL_FACTORING = OFF;
+	SUBFACTOR_EXTRACTION = OFF;
+	REFACTORIZATION = OFF;
+	NOT_GATE_PUSH_BACK = ON;
+	DUPLICATE_LOGIC_EXTRACTION = OFF;
+	REDUCE_LOGIC = OFF;
+	DECOMPOSE_GATES = OFF;
+	SOFT_BUFFER_INSERTION = ON;
+	IGNORE_SOFT_BUFFERS = ON;
+	PARALLEL_EXPANDERS = OFF;
+	TURBO_BIT = OFF;
+	XOR_SYNTHESIS = OFF;
+	SLOW_SLEW_RATE = OFF;
+	MINIMIZATION = PARTIAL;
+	CARRY_CHAIN_LENGTH = 32;
+	CARRY_CHAIN = MANUAL;
+	CASCADE_CHAIN_LENGTH = 2;
+	CASCADE_CHAIN = MANUAL;
+END;
+

fw/src/max/SP047032.TDF

@@ -0,0 +1,233 @@
+TITLE "SINC_controller";
+
+Constant HDD_TYPE = 1;
+
+SUBDESIGN SP047032
+	(
+	EPM_RES		: INPUT;
+	HD_WE[2..1]	: OUTPUT;
+	HD_OE[2..1]	: OUTPUT;
+	HD_CS[2..1]	: OUTPUT;
+	HD_CSS[2..1]: OUTPUT;
+
+	CLK_WG		: OUTPUT;
+	RDATA		: INPUT;
+	QDAT		: OUTPUT;
+	RDAT		: OUTPUT;
+
+	D0			: INPUT;
+	MA0			: INPUT;
+	STE			: INPUT;
+	WSTB,RSTB	: INPUT;
+
+	/WR			: INPUT;
+	/RD			: INPUT;
+	HDD_CS		: INPUT;
+
+	/MR,/IO		: INPUT;
+	CLKZZ		: OUTPUT;
+
+	/RTSB,/DTRB	: INPUT;
+
+	10K_D0		: OUTPUT;
+	10K_CLK		: OUTPUT;
+	/CONFIG		: OUTPUT;
+	CNF_ON		: INPUT;
+	TG42_OUT	: OUTPUT;
+	TG42_IN		: INPUT;
+
+	CLK_PRC		: OUTPUT;
+
+	MA7			: INPUT;
+
+--	/WRH		: INPUT;
+	/WRH		: OUTPUT;
+
+--	/RDH		: OUTPUT; -> NA HD_CS1
+
+	)
+VARIABLE
+
+	CT[2..0]	: DFF;
+	CLKZZ1		: NODE;
+	STWG[2..0]	: DFF;
+	WGR[4..0]	: DFF;
+	CT_WG		: NODE;
+	CT_WG1		: NODE;
+	TB_WG		: NODE;
+	CODE[4..0]	: DFF;
+	TURBING		: NODE;
+	RDAT_X		: NODE;
+	HD_CS_CLK	: NODE;
+	MXX			: NODE;
+
+BEGIN
+
+--	====== Oscillator ==========
+	TG42_OUT 	= EXP(TG42_IN);
+--	TG42_OUT 	= !(TG42_IN);
+
+--	tG42_OUT 	= LCELL(EXP(TG42_IN));
+--	============================
+
+--	====== FLEX Loading ========
+
+	10K_CLK		= LCELL((/MR or /WR or CNF_ON) &
+--						(/IO or /WR or HDD_CS or !CNF_ON) &
+						(/MR or /RD or HDD_CS or !CNF_ON));
+	CODE[].clk	= 10K_CLK;
+	CODE[].clrn	= /CONFIG & (/IO or /RD or HDD_CS);
+
+IF !CNF_ON THEN
+	CODE[].d	= (CODE[3..0],(CODE2 xor 10K_D0));
+ELSE
+	CODE[].d	= (CODE[3..0],!CODE0);
+END IF;
+	10K_D0		= LCELL(CODE4 xor D0);
+
+--	============================
+
+--	======= CP FRQ =============
+
+	CT[].clk	= (TG42_IN xor !CT1);
+	CT[].d		= CT[] + 1;
+
+--	IF CT[] == 2 THEN
+--		CT[].d		= GND;
+--	ELSE
+--		CT[].d		= CT[] + 1;
+--	END IF;
+
+	CLKZZ		= TRI(CT1,!CNF_ON);
+
+--	============================
+
+--	========	FDD controller	==================
+
+	TURBING		= EXP(EXP(TURBING & !WSTB & !RSTB) & !STE & !/DTRB);
+--	TURBING		= GND;
+--	TB_WG		= /DTRB or TURBING;
+	TB_WG		= /DTRB;
+
+--	CT_WG		= TFF(VCC,(CT1 xor (CT_WG & (/DTRB or TURBING))),,);
+	CT_WG		= TFF(VCC,(CT1 xor (CT_WG & TURBING)),,);
+
+	CT_WG1		= TFF(VCC,(CT1 xor (CT_WG1 & /DTRB)),,);
+--	STWG[].clk	= LCELL(CT_WG xor STWG2);
+
+	STWG[].clk	= (CT_WG xor STWG2);
+	STWG[].d	= STWG[] + 1;
+	CLK_WG		= STWG2;
+
+	CLK_PRC		= STWG0;
+--	CLK_PRC		= STWG1;
+
+	WGR[].clk	= CT_WG1;
+	IF !RDAT THEN
+		TABLE WGR[3..0] => WGR[3..0].d;
+			0 => 4; 1 => 5; 2 => 4; 3 => 5;
+			4 => 6; 5 => 7; 6 => 8; 7 => 8;
+			8 => 9; 9 => 9; 10 => 10; 11 => 11;
+		   12 => 12; 13 => 13; 14 => 14; 15 => 15;
+		END TABLE;
+		WGR4.d	= WGR4;
+
+--		IF WGR[3..0] == 0 THEN
+--			WGR[3..0].d		= 3;
+--			WGR4.d			= WGR4;
+--		ELSE
+--			WGR[].d			= WGR[] + 1;
+--		END IF;
+	ELSE
+		IF WGR[3..0] == 0 THEN
+			WGR[3..0].d		= 3;
+			WGR4.d			= WGR4;
+		ELSE
+			WGR[].d			= WGR[] + 1;
+		END IF;
+	END IF;
+
+	QDAT	= WGR4;
+--	RDAT_X	= DFF(RDATA,CT_WG1,,);
+	RDAT_X	= EXP(EXP(RDAT_X & EXP(!RDATA & !CT_WG1)) & EXP(RDATA & !CT_WG1));
+	RDAT	= DFF((RDAT_X or !DFF(RDAT_X,CT_WG1,,)),CT_WG1,,);
+
+--	==============================================
+
+--	========= HDD Controller =========
+
+IF HDD_TYPE == 0 THEN
+
+	MXX	= CODE0;
+
+	HD_CS2		= LCELL(HDD_CS or EXP(!HDD_CS));
+
+	HD_CS_CLK	= HD_CS2 or EXP(EXP(EXP(EXP(EXP(!HD_CS2)))));
+
+	HD_CSS1		= HDD_CS or MA7;
+	HD_CSS2		= HDD_CS or !MA7;
+
+
+	HD_CS1		= (/RD or  MA0 or HD_CS_CLK or /IO) &
+					(/RD or CODE0 or HDD_CS or /MR) ;	% /RDH %
+
+	/WRH 		= (/WR or !MA0 or HD_CS_CLK or /IO);	% /WRH %
+
+
+	HD_OE1		= (HDD_CS or /RD or !MA0 or /IO) &
+					(HDD_CS or /RD or !CODE0 or /MR);
+
+	HD_WE1		= HDD_CS or /RD or (/IO & /MR);
+
+
+	HD_OE2		= HDD_CS or /WR or !MA0;
+
+
+	HD_WE2		= HDD_CS or /WR or MA0 or /IO;
+
+--	======= RECONFIG =========
+
+	/CONFIG	= LCELL(EPM_RES & (HDD_CS or /MR or /WR));
+
+ELSE
+
+	MXX	= CODE0;
+
+	HD_CS2		= LCELL(HDD_CS or EXP(!HDD_CS) or /WRH);
+
+	HD_CS_CLK	= HDD_CS or EXP(EXP(EXP(EXP(EXP(!HDD_CS)))));
+
+	HD_CSS1		= HDD_CS or MA7;
+	HD_CSS2		= HDD_CS or !MA7;
+
+	HD_CS1		= HDD_CS or /WR;
+
+	HD_OE1		= (HD_CS_CLK or /RD or !MA0 or /IO) &
+				   (HD_CS_CLK or /WR or !/WRH or !MA0 or /IO) &
+					(HDD_CS or /RD or !CODE0 or /MR);
+
+--	HD_WE1		= (HDD_CS or (/RD & /WR) or /IO);
+
+	HD_WE1		= DFF(GND,!HDD_CS,,!(/RD & /WR));
+
+--	HD_OE1		= (HDD_CS or /RD or !MA0) or (HDD_CS or /RD or );
+
+--	HD_WE1		= (HDD_CS or /RD or MA0 or /IO);
+
+	HD_WE2		= (/WR or !MA0 or HD_CS_CLK or /IO);	% /WRH %
+
+	HD_OE2		= (/RD or  MA0 or HD_CS_CLK or /IO) &
+					(/RD or CODE0 or HDD_CS or /MR) ;	% /RDH %
+
+
+	/WRH = DFF((/WRH or !MA0),(/IO or /WR or HDD_CS),(/IO or /RD or HDD_CS),);
+
+--	======= RECONFIG =========
+
+	/CONFIG	= LCELL(EPM_RES & (HDD_CS or /MR or MA7 or /WR));
+
+END IF;
+
+
+END;
+

fw/src/max/sp037032.rpt

@@ -0,0 +1,910 @@
+Project Information               c:\prj\sprinter\firmware\97\max\sp037032.rpt
+
+MAX+plus II Compiler Report File
+Version 10.0 9/14/2000
+Compiled: 08/05/2024 18:38:47
+
+Copyright (C) 1988-2000 Altera Corporation
+Any megafunction design, and related net list (encrypted or decrypted),
+support information, device programming or simulation file, and any other
+associated documentation or information provided by Altera or a partner
+under Altera's Megafunction Partnership Program may be used only to
+program PLD devices (but not masked PLD devices) from Altera.  Any other
+use of such megafunction design, net list, support information, device
+programming or simulation file, or any other related documentation or
+information is prohibited for any other purpose, including, but not
+limited to modification, reverse engineering, de-compiling, or use with
+any other silicon devices, unless such use is explicitly licensed under
+a separate agreement with Altera or a megafunction partner.  Title to
+the intellectual property, including patents, copyrights, trademarks,
+trade secrets, or maskworks, embodied in any such megafunction design,
+net list, support information, device programming or simulation file, or
+any other related documentation or information provided by Altera or a
+megafunction partner, remains with Altera, the megafunction partner, or
+their respective licensors.  No other licenses, including any licenses
+needed under any third party's intellectual property, are provided herein.
+
+
+
+***** Project compilation was successful
+
+
+SINC_controller
+
+
+** DEVICE SUMMARY **
+
+Chip/                     Input   Output   Bidir         Shareable
+POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized
+
+sp037032  EPM7064SLC44-10  16       16       0      35      40          54 %
+
+User Pins:                 16       16       0  
+
+
+
+Project Information               c:\prj\sprinter\firmware\97\max\sp037032.rpt
+
+** PROJECT COMPILATION MESSAGES **
+
+Warning: Line 63, File c:\prj\sprinter\firmware\97\max\sp037032.tdf:
+   Symbolic name "MXX" was declared but never used
+Warning: Line 53, File c:\prj\sprinter\firmware\97\max\sp037032.tdf:
+   Symbolic name "CLKZZ1" was declared but never used
+Warning: Line 58, File c:\prj\sprinter\firmware\97\max\sp037032.tdf:
+   Symbolic name "TB_WG" was declared but never used
+Warning: Project has user pin or logic cell assignments, but has never been compiled before. For best fitting results, let the Compiler choose the first set of assignments instead.
+
+
+Project Information               c:\prj\sprinter\firmware\97\max\sp037032.rpt
+
+** PIN/LOCATION/CHIP ASSIGNMENTS **
+
+                  Actual                  
+    User       Assignments                
+Assignments   (if different)     Node Name
+
+sp037032@27                       CLK_PRC
+sp037032@33                       CLK_WG
+sp037032@31                       CLKZZ
+sp037032@44                       CNF_ON
+sp037032@40                       /CONFIG
+sp037032@34                       /DTRB
+sp037032@18                       D0
+sp037032@1                        EPM_RES
+sp037032@11                       HD_CSS1
+sp037032@12                       HD_CSS2
+sp037032@9                        HD_CS1
+sp037032@37                       HD_CS2
+sp037032@26                       HDD_CS
+sp037032@8                        HD_OE1
+sp037032@5                        HD_OE2
+sp037032@6                        HD_WE1
+sp037032@4                        HD_WE2
+sp037032@29                       /IO
+sp037032@39                       MA0
+sp037032@36                       MA7
+sp037032@28                       /MR
+sp037032@14                       QDAT
+sp037032@2                        /RD
+sp037032@16                       RDAT
+sp037032@17                       RDATA
+sp037032@21                       RSTB
+sp037032@19                       STE
+sp037032@43                       TG42_IN
+sp037032@41                       TG42_OUT
+sp037032@25                       /WR
+sp037032@24                       /WRH
+sp037032@20                       WSTB
+
+
+Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
+sp037032
+
+***** Logic for device 'sp037032' compiled without errors.
+
+
+
+
+Device: EPM7064SLC44-10
+
+Device Options:
+    Turbo Bit                                    = ON
+    Security Bit                                 = ON
+    Enable JTAG Support                        = ON
+    User Code                                  = ffff
+
+
+
+Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
+sp037032
+
+** ERROR SUMMARY **
+
+Info: Chip 'sp037032' in device 'EPM7064SLC44-10' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
+                                         T     
+                             E     T     G  /  
+              H  H  H        P  C  G     4  C  
+              D  D  D        M  N  4     2  O  
+              _  _  _        _  F  2     _  N  
+              W  O  W  V  /  R  _  _  G  O  F  
+              E  E  E  C  R  E  O  I  N  U  I  
+              1  2  2  C  D  S  N  N  D  T  G  
+            -----------------------------------_ 
+          /   6  5  4  3  2  1 44 43 42 41 40   | 
+    #TDI |  7                                39 | MA0 
+  HD_OE1 |  8                                38 | #TDO 
+  HD_CS1 |  9                                37 | HD_CS2 
+     GND | 10                                36 | MA7 
+ HD_CSS1 | 11                                35 | VCC 
+ HD_CSS2 | 12        EPM7064SLC44-10         34 | /DTRB 
+    #TMS | 13                                33 | CLK_WG 
+    QDAT | 14                                32 | #TCK 
+     VCC | 15                                31 | CLKZZ 
+    RDAT | 16                                30 | GND 
+   RDATA | 17                                29 | /IO 
+         |_  18 19 20 21 22 23 24 25 26 27 28  _| 
+           ------------------------------------ 
+              D  S  W  R  G  V  /  /  H  C  /  
+              0  T  S  S  N  C  W  W  D  L  M  
+                 E  T  T  D  C  R  R  D  K  R  
+                    B  B        H     _  _     
+                                      C  P     
+                                      S  R     
+                                         C     
+                                               
+
+
+N.C. = No Connect. This pin has no internal connection to the device.
+VCC = Dedicated power pin, which MUST be connected to VCC.
+GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
+RESERVED = Unused I/O pin, which MUST be left unconnected.
+
+^ = Dedicated configuration pin.
++ = Reserved configuration pin, which is tri-stated during user mode.
+* = Reserved configuration pin, which drives out in user mode.
+PDn = Power Down pin. 
+@ = Special-purpose pin. 
+# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
+& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.
+
+
+Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
+sp037032
+
+** RESOURCE USAGE **
+
+                                                Shareable     External
+Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect
+
+A:     LC1 - LC16    16/16(100%)   8/ 8(100%)  13/16( 81%)  22/36( 61%) 
+B:    LC17 - LC32     8/16( 50%)   8/ 8(100%)  16/16(100%)  15/36( 41%) 
+C:    LC33 - LC48     6/16( 37%)   8/ 8(100%)  13/16( 81%)  16/36( 44%) 
+D:    LC49 - LC64     5/16( 31%)   8/ 8(100%)   3/16( 18%)  11/36( 30%) 
+
+
+Total dedicated input pins used:                 4/4      (100%)
+Total I/O pins used:                            32/32     (100%)
+Total logic cells used:                         35/64     ( 54%)
+Total shareable expanders used:                 40/64     ( 62%)
+Total Turbo logic cells used:                   23/64     ( 35%)
+Total shareable expanders not available (n/a):   5/64     (  7%)
+Average fan-in:                                  4.65
+Total fan-in:                                   163
+
+Total input pins required:                      16
+Total fast input logic cells required:           0
+Total output pins required:                     16
+Total bidirectional pins required:               0
+Total reserved pins required                     4
+Total logic cells required:                     35
+Total flipflops required:                       20
+Total product terms required:                  126
+Total logic cells lending parallel expanders:    0
+Total shareable expanders in database:          38
+
+Synthesized logic cells:                         1/  64   (  1%)
+
+
+
+Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
+sp037032
+
+** INPUTS **
+
+                                         Shareable
+                                         Expanders     Fan-In    Fan-Out
+ Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
+  44      -   -       INPUT               0      0   0    0    0    2    8  CNF_ON
+  34   (51)  (D)      INPUT               0      0   0    0    0    0    2  /DTRB
+  18   (21)  (B)      INPUT               0      0   0    0    0    0    1  D0
+   1      -   -       INPUT               0      0   0    0    0    1    0  EPM_RES
+  26   (36)  (C)      INPUT               0      0   0    0    0   10    1  HDD_CS
+  29   (41)  (C)      INPUT               0      0   0    0    0    5    5  /IO
+  39   (57)  (D)      INPUT               0      0   0    0    0    4    0  MA0
+  36   (52)  (D)      INPUT               0      0   0    0    0    3    0  MA7
+  28   (40)  (C)      INPUT               0      0   0    0    0    3    1  /MR
+   2      -   -       INPUT               0      0   0    0    0    4    6  /RD
+  17   (24)  (B)      INPUT               0      0   0    0    0    0    2  RDATA
+  21   (17)  (B)      INPUT               0      0   0    0    0    0    1  RSTB
+  19   (20)  (B)      INPUT               0      0   0    0    0    0    1  STE
+  43      -   -       INPUT               0      0   0    0    0    2    1  TG42_IN
+  25   (35)  (C)      INPUT               0      0   0    0    0    6    1  /WR
+  20   (19)  (B)      INPUT               0      0   0    0    0    0    1  WSTB
+
+
+Code:
+
+s = Synthesized pin or logic cell
+t = Turbo logic cell
++ = Synchronous flipflop
+/ = Slow slew-rate output
+! = NOT gate push-back
+r = Fitter-inserted logic cell
+
+
+Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
+sp037032
+
+** OUTPUTS **
+
+                                         Shareable
+                                         Expanders     Fan-In    Fan-Out
+ Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
+  27     37    C         FF      t        2      2   0    0    2    1    1  CLK_PRC
+  33     49    D         FF      t        2      2   0    0    4    2    1  CLK_WG
+  31     46    C     TRI/FF      t        2      2   0    1    2    1    3  CLKZZ
+  40     62    D     OUTPUT               0      0   0    5    0    0    5  /CONFIG
+  11      3    A     OUTPUT               0      0   0    2    0    0    0  HD_CSS1
+  12      1    A     OUTPUT               0      0   0    2    0    0    0  HD_CSS2
+   9      4    A     OUTPUT               0      0   0    2    0    0    0  HD_CS1
+  37     53    D     OUTPUT               0      0   0    1    1    0    0  HD_CS2
+   8      5    A     OUTPUT               4      4   0    6    2    0    0  HD_OE1
+   5     14    A     OUTPUT               4      4   0    5    1    0    0  HD_OE2
+   6     11    A     OUTPUT               0      0   0    4    0    0    0  HD_WE1
+   4     16    A     OUTPUT               4      4   0    4    0    0    0  HD_WE2
+  14     30    B     OUTPUT      t        0      0   0    1    2    0    0  QDAT
+  16     25    B     OUTPUT      t        0      0   0    1    2    0    0  RDAT
+  41     64    D     OUTPUT      t        1      0   0    1    0    0    0  TG42_OUT
+  24     33    C         FF               1      0   0    5    1    3    0  /WRH
+
+
+Code:
+
+s = Synthesized pin or logic cell
+t = Turbo logic cell
++ = Synchronous flipflop
+/ = Slow slew-rate output
+! = NOT gate push-back
+r = Fitter-inserted logic cell
+
+
+Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
+sp037032
+
+** BURIED LOGIC **
+
+                                         Shareable
+                                         Expanders     Fan-In    Fan-Out
+ Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
+   -     12    A       DFFE      t        3      2   1    3    5    2    2  CODE0
+   -      9    A       DFFE      t        2      2   0    2    3    0    1  CODE1
+  (7)     8    A       DFFE      t        2      2   0    2    3    0    2  CODE2
+   -     13    A       DFFE      t        2      2   0    2    3    0    1  CODE3
+   -     15    A       DFFE      t        2      2   0    2    3    0    1  CODE4
+ (26)    36    C       TFFE      t        5      0   0    4    2    2    2  CT_WG
+   -     34    C       TFFE      t        3      0   0    1    2    0    8  CT_WG1
+ (25)    35    C       TFFE      t        2      2   0    1    1    1    0  CT0
+ (36)    52    D       TFFE      t        2      2   0    0    3    1    0  STWG1
+   -      7    A       TFFE      t        1      0   1    1    7    0    5  WGR0
+ (20)    19    B       DFFE      t        5      1   1    1    8    0    6  WGR1
+   -     22    B       TFFE      t        8      1   0    1    7    0    6  WGR2
+   -      6    A       DFFE      t        4      0   1    1    7    0    6  WGR3
+ (21)    17    B       TFFE      t        0      0   0    1    7    1    0  WGR4
+   -      2    A      LCELL               0      0   0    5    0    1    5  10K_CLK
+   -     18    B      LCELL               0      0   0    1    1    1    7  10K_D0
+   -     23    B       DFFE      t        4      4   0    1    2    1    6  :97
+ (17)    24    B       DFFE      t        4      4   0    1    1    0    1  :98
+   -     10    A       SOFT    s t        1      0   1    1    5    0    1  ~389~1
+
+
+Code:
+
+s = Synthesized pin or logic cell
+t = Turbo logic cell
++ = Synchronous flipflop
+/ = Slow slew-rate output
+! = NOT gate push-back
+r = Fitter-inserted logic cell
+
+
+Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
+sp037032
+
+** LOGIC CELL INTERCONNECTIONS **
+
+Logic Array Block 'A':
+
+                                         Logic cells placed in LAB 'A'
+        +------------------------------- LC12 CODE0
+        | +----------------------------- LC9 CODE1
+        | | +--------------------------- LC8 CODE2
+        | | | +------------------------- LC13 CODE3
+        | | | | +----------------------- LC15 CODE4
+        | | | | | +--------------------- LC3 HD_CSS1
+        | | | | | | +------------------- LC1 HD_CSS2
+        | | | | | | | +----------------- LC4 HD_CS1
+        | | | | | | | | +--------------- LC5 HD_OE1
+        | | | | | | | | | +------------- LC14 HD_OE2
+        | | | | | | | | | | +----------- LC11 HD_WE1
+        | | | | | | | | | | | +--------- LC16 HD_WE2
+        | | | | | | | | | | | | +------- LC7 WGR0
+        | | | | | | | | | | | | | +----- LC6 WGR3
+        | | | | | | | | | | | | | | +--- LC2 10K_CLK
+        | | | | | | | | | | | | | | | +- LC10 ~389~1
+        | | | | | | | | | | | | | | | | 
+        | | | | | | | | | | | | | | | |   Other LABs fed by signals
+        | | | | | | | | | | | | | | | |   that feed LAB 'A'
+LC      | | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'A':
+LC12 -> * * - - - - - - * * - - - - - - | * - - - | <-- CODE0
+LC9  -> - - * - - - - - - - - - - - - - | * - - - | <-- CODE1
+LC8  -> * - - * - - - - - - - - - - - - | * - - - | <-- CODE2
+LC13 -> - - - - * - - - - - - - - - - - | * - - - | <-- CODE3
+LC7  -> - - - - - - - - - - - - * * - - | * * - - | <-- WGR0
+LC6  -> - - - - - - - - - - - - * * - * | * * - - | <-- WGR3
+LC2  -> * * * * * - - - - - - - - - - - | * * - - | <-- 10K_CLK
+
+Pin
+44   -> * - - - - - - - - - - - * * * * | * * - - | <-- CNF_ON
+1    -> - - - - - - - - - - - - - - - - | - - - * | <-- EPM_RES
+26   -> - - - - - * * * * * * * - - * - | * - * * | <-- HDD_CS
+29   -> * * * * * - - - * * * * - - - - | * - * - | <-- /IO
+39   -> - - - - - - - - * * - * - - - - | * - * - | <-- MA0
+36   -> - - - - - * * - - - - - - - - - | * - - * | <-- MA7
+28   -> - - - - - - - - * * - - - - * - | * - - * | <-- /MR
+2    -> * * * * * - - - * * * - - - * - | * - * - | <-- /RD
+43   -> - - - - - - - - - - - - - - - - | - - * * | <-- TG42_IN
+25   -> - - - - - - - * * - * * - - * - | * - * * | <-- /WR
+LC62 -> * * * * * - - - - - - - - - - - | * - - - | <-- /CONFIG
+LC34 -> - - - - - - - - - - - - * * - - | * * * - | <-- CT_WG1
+LC19 -> - - - - - - - - - - - - * * - * | * * - - | <-- WGR1
+LC22 -> - - - - - - - - - - - - * * - * | * * - - | <-- WGR2
+LC33 -> - - - - - - - - * - - - - - - - | * - * * | <-- /WRH
+LC18 -> * - - - - - - - - - - - * * - * | * * - - | <-- 10K_D0
+LC23 -> - - - - - - - - - - - - * * - * | * * - - | <-- :97
+
+
+* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
+- = The logic cell or pin is not an input to the logic cell (or LAB).
+
+
+Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
+sp037032
+
+** LOGIC CELL INTERCONNECTIONS **
+
+Logic Array Block 'B':
+
+                         Logic cells placed in LAB 'B'
+        +--------------- LC30 QDAT
+        | +------------- LC25 RDAT
+        | | +----------- LC19 WGR1
+        | | | +--------- LC22 WGR2
+        | | | | +------- LC17 WGR4
+        | | | | | +----- LC18 10K_D0
+        | | | | | | +--- LC23 :97
+        | | | | | | | +- LC24 :98
+        | | | | | | | | 
+        | | | | | | | |   Other LABs fed by signals
+        | | | | | | | |   that feed LAB 'B'
+LC      | | | | | | | | | A B C D |     Logic cells that feed LAB 'B':
+LC19 -> - - * * * - - - | * * - - | <-- WGR1
+LC22 -> - - * * * - - - | * * - - | <-- WGR2
+LC17 -> * - - - * - - - | - * - - | <-- WGR4
+LC18 -> - * * * * - - - | * * - - | <-- 10K_D0
+LC23 -> - * * * * - - - | * * - - | <-- :97
+LC24 -> - - - - - - * - | - * - - | <-- :98
+
+Pin
+44   -> * * * * * - - - | * * - - | <-- CNF_ON
+18   -> - - - - - * - - | - * - - | <-- D0
+1    -> - - - - - - - - | - - - * | <-- EPM_RES
+2    -> - - - - - - - - | * - * - | <-- /RD
+17   -> - - - - - - * * | - * - - | <-- RDATA
+43   -> - - - - - - - - | - - * * | <-- TG42_IN
+LC15 -> - - - - - * - - | - * - - | <-- CODE4
+LC34 -> - - * * * - * * | * * * - | <-- CT_WG1
+LC7  -> - - * * * - - - | * * - - | <-- WGR0
+LC6  -> - - * * * - - - | * * - - | <-- WGR3
+LC2  -> * - - - - - - - | * * - - | <-- 10K_CLK
+LC10 -> - - * - - - - - | - * - - | <-- ~389~1
+
+
+* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
+- = The logic cell or pin is not an input to the logic cell (or LAB).
+
+
+Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
+sp037032
+
+** LOGIC CELL INTERCONNECTIONS **
+
+Logic Array Block 'C':
+
+                     Logic cells placed in LAB 'C'
+        +----------- LC37 CLK_PRC
+        | +--------- LC46 CLKZZ
+        | | +------- LC36 CT_WG
+        | | | +----- LC34 CT_WG1
+        | | | | +--- LC35 CT0
+        | | | | | +- LC33 /WRH
+        | | | | | | 
+        | | | | | |   Other LABs fed by signals
+        | | | | | |   that feed LAB 'C'
+LC      | | | | | | | A B C D |     Logic cells that feed LAB 'C':
+LC46 -> - * * * * - | - - * - | <-- CLKZZ
+LC36 -> * - * - - - | - - * * | <-- CT_WG
+LC34 -> - - - * - - | * * * - | <-- CT_WG1
+LC35 -> - * - - * - | - - * - | <-- CT0
+LC33 -> - - - - - * | * - * * | <-- /WRH
+
+Pin
+44   -> - - - - - - | * * - - | <-- CNF_ON
+34   -> - - * * - - | - - * - | <-- /DTRB
+1    -> - - - - - - | - - - * | <-- EPM_RES
+26   -> - - - - - * | * - * * | <-- HDD_CS
+29   -> - - - - - * | * - * - | <-- /IO
+39   -> - - - - - * | * - * - | <-- MA0
+2    -> - - - - - * | * - * - | <-- /RD
+21   -> - - * - - - | - - * - | <-- RSTB
+19   -> - - * - - - | - - * - | <-- STE
+43   -> - * - - * - | - - * * | <-- TG42_IN
+25   -> - - - - - * | * - * * | <-- /WR
+20   -> - - * - - - | - - * - | <-- WSTB
+LC49 -> * - - - - - | - - * * | <-- CLK_WG
+
+
+* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
+- = The logic cell or pin is not an input to the logic cell (or LAB).
+
+
+Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
+sp037032
+
+** LOGIC CELL INTERCONNECTIONS **
+
+Logic Array Block 'D':
+
+                   Logic cells placed in LAB 'D'
+        +--------- LC49 CLK_WG
+        | +------- LC62 /CONFIG
+        | | +----- LC53 HD_CS2
+        | | | +--- LC52 STWG1
+        | | | | +- LC64 TG42_OUT
+        | | | | | 
+        | | | | |   Other LABs fed by signals
+        | | | | |   that feed LAB 'D'
+LC      | | | | | | A B C D |     Logic cells that feed LAB 'D':
+LC49 -> * - - * - | - - * * | <-- CLK_WG
+LC52 -> * - - * - | - - - * | <-- STWG1
+
+Pin
+44   -> - - - - - | * * - - | <-- CNF_ON
+1    -> - * - - - | - - - * | <-- EPM_RES
+26   -> - * * - - | * - * * | <-- HDD_CS
+36   -> - * - - - | * - - * | <-- MA7
+28   -> - * - - - | * - - * | <-- /MR
+2    -> - - - - - | * - * - | <-- /RD
+43   -> - - - - * | - - * * | <-- TG42_IN
+25   -> - * - - - | * - * * | <-- /WR
+LC37 -> * - - * - | - - - * | <-- CLK_PRC
+LC36 -> * - - * - | - - * * | <-- CT_WG
+LC33 -> - - * - - | * - * * | <-- /WRH
+
+
+* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
+- = The logic cell or pin is not an input to the logic cell (or LAB).
+
+
+Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
+sp037032
+
+** EQUATIONS **
+
+CNF_ON   : INPUT;
+D0       : INPUT;
+EPM_RES  : INPUT;
+HDD_CS   : INPUT;
+MA0      : INPUT;
+MA7      : INPUT;
+RDATA    : INPUT;
+RSTB     : INPUT;
+STE      : INPUT;
+TG42_IN  : INPUT;
+WSTB     : INPUT;
+/DTRB    : INPUT;
+/IO      : INPUT;
+/MR      : INPUT;
+/RD      : INPUT;
+/WR      : INPUT;
+
+-- Node name is 'CLK_PRC' = 'STWG0' from file "sp037032.tdf" line 54, column 6
+-- Equation name is 'CLK_PRC', location is LC037, type is output.
+ CLK_PRC = TFFE( VCC,  _EQ001,  VCC,  VCC,  VCC);
+  _EQ001 =  _X001 &  _X002;
+  _X001  = EXP(!CLK_WG & !CT_WG);
+  _X002  = EXP( CLK_WG &  CT_WG);
+
+-- Node name is 'CLK_WG' = 'STWG2' from file "sp037032.tdf" line 54, column 6
+-- Equation name is 'CLK_WG', location is LC049, type is output.
+ CLK_WG  = TFFE( _EQ002,  _EQ003,  VCC,  VCC,  VCC);
+  _EQ002 =  CLK_PRC &  STWG1;
+  _EQ003 =  _X001 &  _X002;
+  _X001  = EXP(!CLK_WG & !CT_WG);
+  _X002  = EXP( CLK_WG &  CT_WG);
+
+-- Node name is 'CLKZZ' = 'CT1' from file "sp037032.tdf" line 52, column 4
+-- Equation name is 'CLKZZ', location is LC046, type is output.
+CLKZZ    = TRI(CT1, !CNF_ON);
+CT1      = TFFE( CT0,  _EQ004,  VCC,  VCC,  VCC);
+  _EQ004 =  _X003 &  _X004;
+  _X003  = EXP( CT1 & !TG42_IN);
+  _X004  = EXP(!CT1 &  TG42_IN);
+
+-- Node name is 'CODE0' from file "sp037032.tdf" line 59, column 6
+-- Equation name is 'CODE0', location is LC012, type is buried.
+CODE0    = DFFE( _EQ005 $  GND,  10K_CLK, !_EQ006,  VCC,  VCC);
+  _EQ005 = !CNF_ON &  CODE2 & !10K_D0
+         # !CNF_ON & !CODE2 &  10K_D0
+         #  CNF_ON & !CODE0;
+  _EQ006 =  _X005 &  _X006;
+  _X005  = EXP( /CONFIG &  /RD);
+  _X006  = EXP( /CONFIG &  /IO);
+
+-- Node name is 'CODE1' from file "sp037032.tdf" line 59, column 6
+-- Equation name is 'CODE1', location is LC009, type is buried.
+CODE1    = DFFE( CODE0 $  GND,  10K_CLK, !_EQ007,  VCC,  VCC);
+  _EQ007 =  _X005 &  _X006;
+  _X005  = EXP( /CONFIG &  /RD);
+  _X006  = EXP( /CONFIG &  /IO);
+
+-- Node name is 'CODE2' from file "sp037032.tdf" line 59, column 6
+-- Equation name is 'CODE2', location is LC008, type is buried.
+CODE2    = DFFE( CODE1 $  GND,  10K_CLK, !_EQ008,  VCC,  VCC);
+  _EQ008 =  _X005 &  _X006;
+  _X005  = EXP( /CONFIG &  /RD);
+  _X006  = EXP( /CONFIG &  /IO);
+
+-- Node name is 'CODE3' from file "sp037032.tdf" line 59, column 6
+-- Equation name is 'CODE3', location is LC013, type is buried.
+CODE3    = DFFE( CODE2 $  GND,  10K_CLK, !_EQ009,  VCC,  VCC);
+  _EQ009 =  _X005 &  _X006;
+  _X005  = EXP( /CONFIG &  /RD);
+  _X006  = EXP( /CONFIG &  /IO);
+
+-- Node name is 'CODE4' from file "sp037032.tdf" line 59, column 6
+-- Equation name is 'CODE4', location is LC015, type is buried.
+CODE4    = DFFE( CODE3 $  GND,  10K_CLK, !_EQ010,  VCC,  VCC);
+  _EQ010 =  _X005 &  _X006;
+  _X005  = EXP( /CONFIG &  /RD);
+  _X006  = EXP( /CONFIG &  /IO);
+
+-- Node name is 'CT_WG' from file "sp037032.tdf" line 116, column 11
+-- Equation name is 'CT_WG', location is LC036, type is buried.
+CT_WG    = TFFE( VCC,  _EQ011,  VCC,  VCC,  VCC);
+  _EQ011 =  _X007 &  _X008 &  _X009;
+  _X007  = EXP(!CT_WG & !CT1);
+  _X008  = EXP( CT_WG &  CT1 &  _X010);
+  _X009  = EXP(!CT1 & !/DTRB & !STE &  _X011);
+  _X010  = EXP(!/DTRB & !STE &  _X011);
+  _X011  = EXP(!RSTB & !WSTB &  _X010);
+
+-- Node name is 'CT_WG1' from file "sp037032.tdf" line 118, column 12
+-- Equation name is 'CT_WG1', location is LC034, type is buried.
+CT_WG1   = TFFE( VCC,  _EQ012,  VCC,  VCC,  VCC);
+  _EQ012 =  _X012 &  _X013 &  _X014;
+  _X012  = EXP(!CT_WG1 & !CT1);
+  _X013  = EXP( CT_WG1 &  CT1 &  /DTRB);
+  _X014  = EXP(!CT1 & !/DTRB);
+
+-- Node name is 'CT0' from file "sp037032.tdf" line 52, column 4
+-- Equation name is 'CT0', location is LC035, type is buried.
+CT0      = TFFE( VCC,  _EQ013,  VCC,  VCC,  VCC);
+  _EQ013 =  _X003 &  _X004;
+  _X003  = EXP( CT1 & !TG42_IN);
+  _X004  = EXP(!CT1 &  TG42_IN);
+
+-- Node name is 'HD_CSS1' 
+-- Equation name is 'HD_CSS1', location is LC003, type is output.
+ HD_CSS1 = LCELL( _EQ014 $  VCC);
+  _EQ014 = !HDD_CS & !MA7;
+
+-- Node name is 'HD_CSS2' 
+-- Equation name is 'HD_CSS2', location is LC001, type is output.
+ HD_CSS2 = LCELL( _EQ015 $  VCC);
+  _EQ015 = !HDD_CS &  MA7;
+
+-- Node name is 'HD_CS1' 
+-- Equation name is 'HD_CS1', location is LC004, type is output.
+ HD_CS1  = LCELL( _EQ016 $  VCC);
+  _EQ016 = !HDD_CS & !/WR;
+
+-- Node name is 'HD_CS2' = ':107' from file "sp037032.tdf" line 206, column 12
+-- Equation name is 'HD_CS2', type is output 
+ HD_CS2  = LCELL( _EQ017 $  VCC);
+  _EQ017 = !HDD_CS & !/WRH;
+
+-- Node name is 'HD_OE1' 
+-- Equation name is 'HD_OE1', location is LC005, type is output.
+ HD_OE1  = LCELL( _EQ018 $  VCC);
+  _EQ018 = !HDD_CS & !/IO &  MA0 & !/WR &  /WRH &  _X015
+         # !HDD_CS & !/IO &  MA0 & !/RD &  _X015
+         #  CODE0 & !HDD_CS & !/MR & !/RD;
+  _X015  = EXP( _X016);
+  _X016  = EXP( _X017);
+  _X017  = EXP( _X018);
+  _X018  = EXP(!HDD_CS);
+
+-- Node name is 'HD_OE2' 
+-- Equation name is 'HD_OE2', location is LC014, type is output.
+ HD_OE2  = LCELL( _EQ019 $  VCC);
+  _EQ019 = !HDD_CS & !/IO & !MA0 & !/RD &  _X015
+         # !CODE0 & !HDD_CS & !/MR & !/RD;
+  _X015  = EXP( _X016);
+  _X016  = EXP( _X017);
+  _X017  = EXP( _X018);
+  _X018  = EXP(!HDD_CS);
+
+-- Node name is 'HD_WE1' 
+-- Equation name is 'HD_WE1', location is LC011, type is output.
+ HD_WE1  = LCELL( _EQ020 $  VCC);
+  _EQ020 = !HDD_CS & !/IO & !/WR
+         # !HDD_CS & !/IO & !/RD;
+
+-- Node name is 'HD_WE2' 
+-- Equation name is 'HD_WE2', location is LC016, type is output.
+ HD_WE2  = LCELL( _EQ021 $  VCC);
+  _EQ021 = !HDD_CS & !/IO &  MA0 & !/WR &  _X015;
+  _X015  = EXP( _X016);
+  _X016  = EXP( _X017);
+  _X017  = EXP( _X018);
+  _X018  = EXP(!HDD_CS);
+
+-- Node name is 'QDAT' 
+-- Equation name is 'QDAT', location is LC030, type is output.
+ QDAT    = LCELL( _EQ022 $  GND);
+  _EQ022 =  CNF_ON &  WGR4
+         # !CNF_ON &  10K_CLK;
+
+-- Node name is 'RDAT' 
+-- Equation name is 'RDAT', location is LC025, type is output.
+ RDAT    = LCELL( _EQ023 $  GND);
+  _EQ023 =  CNF_ON &  _LC023
+         # !CNF_ON &  10K_D0;
+
+-- Node name is 'STWG1' from file "sp037032.tdf" line 54, column 6
+-- Equation name is 'STWG1', location is LC052, type is buried.
+STWG1    = TFFE( CLK_PRC,  _EQ024,  VCC,  VCC,  VCC);
+  _EQ024 =  _X001 &  _X002;
+  _X001  = EXP(!CLK_WG & !CT_WG);
+  _X002  = EXP( CLK_WG &  CT_WG);
+
+-- Node name is 'TG42_OUT' 
+-- Equation name is 'TG42_OUT', location is LC064, type is output.
+ TG42_OUT = LCELL( _EQ025 $  GND);
+  _EQ025 =  _X019;
+  _X019  = EXP( TG42_IN);
+
+-- Node name is 'WGR0' from file "sp037032.tdf" line 55, column 5
+-- Equation name is 'WGR0', location is LC007, type is buried.
+WGR0     = TFFE( _EQ026,  CT_WG1,  VCC,  VCC,  VCC);
+  _EQ026 =  WGR0 &  WGR1 &  WGR2 & !WGR3
+         # !WGR0 & !WGR1 & !WGR2 &  WGR3
+         #  CNF_ON &  _LC023
+         # !CNF_ON &  10K_D0;
+
+-- Node name is 'WGR1' from file "sp037032.tdf" line 55, column 5
+-- Equation name is 'WGR1', location is LC019, type is buried.
+WGR1     = DFFE( _EQ027 $  _EQ028,  CT_WG1,  VCC,  VCC,  VCC);
+  _EQ027 =  CNF_ON & !_LC010 &  _LC023 & !WGR0 & !WGR1 &  WGR2 &  _X020 & 
+              _X021 &  _X022 &  _X023
+         # !CNF_ON & !_LC010 & !WGR0 & !WGR1 &  WGR2 &  _X020 &  _X021 & 
+              _X022 &  _X023 &  10K_D0
+         #  CNF_ON & !_LC010 &  _LC023 &  WGR0 &  WGR1 &  _X020 &  _X021 & 
+              _X022 &  _X023;
+  _X020  = EXP(!CNF_ON &  WGR0 &  WGR1 &  10K_D0);
+  _X021  = EXP(!CNF_ON & !WGR1 & !WGR2 & !10K_D0);
+  _X022  = EXP( WGR0 &  WGR1 & !WGR3);
+  _X023  = EXP(!WGR0 & !WGR1 &  WGR3);
+  _EQ028 = !_LC010 &  _X020 &  _X021 &  _X022 &  _X023;
+  _X020  = EXP(!CNF_ON &  WGR0 &  WGR1 &  10K_D0);
+  _X021  = EXP(!CNF_ON & !WGR1 & !WGR2 & !10K_D0);
+  _X022  = EXP( WGR0 &  WGR1 & !WGR3);
+  _X023  = EXP(!WGR0 & !WGR1 &  WGR3);
+
+-- Node name is 'WGR2' from file "sp037032.tdf" line 55, column 5
+-- Equation name is 'WGR2', location is LC022, type is buried.
+WGR2     = TFFE(!_EQ029,  CT_WG1,  VCC,  VCC,  VCC);
+  _EQ029 =  _X020 &  _X024 &  _X025 &  _X026 &  _X027 &  _X028 &  _X029 & 
+              _X030;
+  _X020  = EXP(!CNF_ON &  WGR0 &  WGR1 &  10K_D0);
+  _X024  = EXP(!CNF_ON &  WGR1 &  WGR2 & !WGR3 & !10K_D0);
+  _X025  = EXP( CNF_ON & !_LC023 &  WGR1 &  WGR2 & !WGR3);
+  _X026  = EXP( CNF_ON &  _LC023 &  WGR0 &  WGR1);
+  _X027  = EXP( WGR0 &  WGR1 &  WGR2 & !WGR3);
+  _X028  = EXP( CNF_ON & !_LC023 & !WGR2 & !WGR3);
+  _X029  = EXP(!_LC023 & !WGR2 & !WGR3 & !10K_D0);
+  _X030  = EXP(!CNF_ON & !WGR2 & !WGR3 & !10K_D0);
+
+-- Node name is 'WGR3' from file "sp037032.tdf" line 55, column 5
+-- Equation name is 'WGR3', location is LC006, type is buried.
+WGR3     = DFFE( _EQ030 $  _EQ031,  CT_WG1,  VCC,  VCC,  VCC);
+  _EQ030 =  CNF_ON &  _LC023 &  WGR0 &  WGR1 &  WGR2 &  WGR3 &  _X031 & 
+              _X032 &  _X033
+         # !CNF_ON &  WGR0 &  WGR1 &  WGR2 &  WGR3 &  _X031 &  _X032 &  _X033 & 
+              10K_D0
+         #  CNF_ON &  _LC023 & !WGR0 & !WGR3 &  _X031 &  _X032 &  _X033;
+  _X031  = EXP(!WGR1 & !WGR3);
+  _X032  = EXP(!CNF_ON & !WGR0 & !WGR3 &  10K_D0);
+  _X033  = EXP(!WGR2 & !WGR3);
+  _EQ031 =  _X031 &  _X032 &  _X033;
+  _X031  = EXP(!WGR1 & !WGR3);
+  _X032  = EXP(!CNF_ON & !WGR0 & !WGR3 &  10K_D0);
+  _X033  = EXP(!WGR2 & !WGR3);
+
+-- Node name is 'WGR4' from file "sp037032.tdf" line 55, column 5
+-- Equation name is 'WGR4', location is LC017, type is buried.
+WGR4     = TFFE( _EQ032,  CT_WG1,  VCC,  VCC,  VCC);
+  _EQ032 =  CNF_ON &  _LC023 &  WGR0 &  WGR1 &  WGR2 &  WGR3
+         # !CNF_ON &  WGR0 &  WGR1 &  WGR2 &  WGR3 &  10K_D0;
+
+-- Node name is '10K_CLK' from file "sp037032.tdf" line 77, column 13
+-- Equation name is '10K_CLK', location is LC002, type is buried.
+10K_CLK  = LCELL( _EQ033 $  VCC);
+  _EQ033 =  CNF_ON & !HDD_CS & !/MR & !/RD
+         # !CNF_ON & !/MR & !/WR;
+
+-- Node name is '10K_D0' from file "sp037032.tdf" line 89, column 12
+-- Equation name is '10K_D0', location is LC018, type is buried.
+10K_D0   = LCELL( CODE4 $  D0);
+
+-- Node name is '/CONFIG' = ':115' from file "sp037032.tdf" line 282, column 12
+-- Equation name is '/CONFIG', type is output 
+ /CONFIG = LCELL( _EQ034 $  EPM_RES);
+  _EQ034 =  EPM_RES & !HDD_CS & !MA7 & !/MR & !/WR;
+
+-- Node name is '/WRH' = ':114' from file "sp037032.tdf" line 233, column 9
+-- Equation name is '/WRH', type is output 
+ /WRH    = DFFE( _EQ035 $  VCC,  _EQ036, !_EQ037,  VCC,  VCC);
+  _EQ035 =  MA0 & !/WRH;
+  _EQ036 =  _X034;
+  _X034  = EXP(!HDD_CS & !/IO & !/WR);
+  _EQ037 = !/IO & !/RD;
+
+-- Node name is ':97' from file "sp037032.tdf" line 162, column 9
+-- Equation name is '_LC023', type is buried 
+_LC023   = DFFE( _EQ038 $  VCC,  CT_WG1,  VCC,  VCC,  VCC);
+  _EQ038 =  _LC024 &  _X035 &  _X036;
+  _X035  = EXP(!CT_WG1 &  RDATA);
+  _X036  = EXP( _X037 &  _X038);
+  _X037  = EXP(!CT_WG1 & !RDATA);
+  _X038  = EXP( _X035 &  _X036);
+
+-- Node name is ':98' from file "sp037032.tdf" line 162, column 25
+-- Equation name is '_LC024', type is buried 
+_LC024   = DFFE( _EQ039 $  GND,  CT_WG1,  VCC,  VCC,  VCC);
+  _EQ039 =  _X038;
+  _X038  = EXP( _X035 &  _X036);
+  _X035  = EXP(!CT_WG1 &  RDATA);
+  _X036  = EXP( _X037 &  _X038);
+  _X037  = EXP(!CT_WG1 & !RDATA);
+
+-- Node name is '~389~1' from file "sp037032.tdf" line 149, column 14
+-- Equation name is '~389~1', location is LC010, type is buried.
+-- synthesized logic cell 
+_LC010   = LCELL( _EQ040 $  GND);
+  _EQ040 =  CNF_ON & !_LC023 &  WGR1 & !WGR3
+         #  CNF_ON & !_LC023 & !WGR1 &  WGR3
+         # !CNF_ON &  WGR1 & !WGR3 & !10K_D0
+         #  CNF_ON & !_LC023 & !WGR1 & !WGR2
+         # !CNF_ON & !WGR1 &  WGR3 & !10K_D0;
+
+
+
+--     Shareable expanders that are duplicated in multiple LABs:
+--    _X001 occurs in LABs C, D
+--    _X002 occurs in LABs C, D
+
+
+
+
+Project Information               c:\prj\sprinter\firmware\97\max\sp037032.rpt
+
+** COMPILATION SETTINGS & TIMES **
+
+Processing Menu Commands
+------------------------
+
+Design Doctor                             = off
+
+Logic Synthesis:
+
+   Synthesis Type Used                    = Standard
+
+   Default Synthesis Style                = NORMAL
+
+      Logic option settings in 'NORMAL' style for 'MAX7000S' family
+
+      DECOMPOSE_GATES                     = on
+      DUPLICATE_LOGIC_EXTRACTION          = on
+      MINIMIZATION                        = full
+      MULTI_LEVEL_FACTORING               = on
+      NOT_GATE_PUSH_BACK                  = on
+      PARALLEL_EXPANDERS                  = off
+      REDUCE_LOGIC                        = on
+      REFACTORIZATION                     = on
+      REGISTER_OPTIMIZATION               = on
+      RESYNTHESIZE_NETWORK                = on
+      SLOW_SLEW_RATE                      = off
+      SOFT_BUFFER_INSERTION               = on
+      SUBFACTOR_EXTRACTION                = on
+      TURBO_BIT                           = on
+      XOR_SYNTHESIS                       = on
+      IGNORE_SOFT_BUFFERS                 = off
+      USE_LPM_FOR_AHDL_OPERATORS          = off
+
+   Other logic synthesis settings:
+
+      Automatic Global Clock              = off
+      Automatic Global Clear              = off
+      Automatic Global Preset             = off
+      Automatic Global Output Enable      = off
+      Automatic Fast I/O                  = off
+      Automatic Register Packing          = off
+      Automatic Open-Drain Pins           = on
+      Automatic Implement in EAB          = off
+      One-Hot State Machine Encoding      = off
+      Optimize                            = 0
+
+Default Timing Specifications: None
+
+Cut All Bidir Feedback Timing Paths       = on
+Cut All Clear & Preset Timing Paths       = on
+
+Ignore Timing Assignments                 = off
+
+Functional SNF Extractor                  = off
+
+Linked SNF Extractor                      = off
+Timing SNF Extractor                      = on
+Optimize Timing SNF                       = off
+Generate AHDL TDO File                    = off
+Fitter Settings                           = ADVANCED
+Smart Recompile                           = on
+Total Recompile                           = off
+
+Interfaces Menu Commands
+------------------------
+
+EDIF Netlist Writer                       = off
+Verilog Netlist Writer                    = off
+VHDL Netlist Writer                       = off
+
+Compilation Times
+-----------------
+
+   Compiler Netlist Extractor             00:00:00
+   Database Builder                       00:00:00
+   Logic Synthesizer                      00:00:00
+   Partitioner                            00:00:00
+   Fitter                                 00:00:00
+   Timing SNF Extractor                   00:00:00
+   Assembler                              00:00:01
+   --------------------------             --------
+   Total Time                             00:00:01
+
+
+Memory Allocated
+-----------------
+
+Peak memory allocated during compilation  = 3,985K

fw/src/max/sp047032.rpt

@@ -0,0 +1,811 @@
+Project Information               c:\prj\sprinter\firmware\97\max\sp047032.rpt
+
+MAX+plus II Compiler Report File
+Version 10.0 9/14/2000
+Compiled: 08/05/2024 18:38:05
+
+Copyright (C) 1988-2000 Altera Corporation
+Any megafunction design, and related net list (encrypted or decrypted),
+support information, device programming or simulation file, and any other
+associated documentation or information provided by Altera or a partner
+under Altera's Megafunction Partnership Program may be used only to
+program PLD devices (but not masked PLD devices) from Altera.  Any other
+use of such megafunction design, net list, support information, device
+programming or simulation file, or any other related documentation or
+information is prohibited for any other purpose, including, but not
+limited to modification, reverse engineering, de-compiling, or use with
+any other silicon devices, unless such use is explicitly licensed under
+a separate agreement with Altera or a megafunction partner.  Title to
+the intellectual property, including patents, copyrights, trademarks,
+trade secrets, or maskworks, embodied in any such megafunction design,
+net list, support information, device programming or simulation file, or
+any other related documentation or information provided by Altera or a
+megafunction partner, remains with Altera, the megafunction partner, or
+their respective licensors.  No other licenses, including any licenses
+needed under any third party's intellectual property, are provided herein.
+
+
+
+***** Project compilation was successful
+
+
+SINC_controller
+
+
+** DEVICE SUMMARY **
+
+Chip/                     Input   Output   Bidir         Shareable
+POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized
+
+sp047032  EPM7032LC44-12   17       18       0      32      27          100%
+
+User Pins:                 17       18       0  
+
+
+
+Project Information               c:\prj\sprinter\firmware\97\max\sp047032.rpt
+
+** PROJECT COMPILATION MESSAGES **
+
+Warning: Line 62, File c:\prj\sprinter\firmware\97\max\sp047032.tdf:
+   Symbolic name "MXX" was declared but never used
+Warning: Line 30, File c:\prj\sprinter\firmware\97\max\sp047032.tdf:
+   Symbolic name "/RTSB" was declared but never used
+Warning: Line 52, File c:\prj\sprinter\firmware\97\max\sp047032.tdf:
+   Symbolic name "CLKZZ1" was declared but never used
+Warning: Line 57, File c:\prj\sprinter\firmware\97\max\sp047032.tdf:
+   Symbolic name "TB_WG" was declared but never used
+Warning: Project has user pin or logic cell assignments, but has never been compiled before. For best fitting results, let the Compiler choose the first set of assignments instead.
+Info: Reserved unused input pin '/RTSB' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
+
+
+Project Information               c:\prj\sprinter\firmware\97\max\sp047032.rpt
+
+** AUTO GLOBAL SIGNALS **
+
+
+
+INFO: Signal 'CNF_ON' chosen for auto global Output Enable
+
+
+Project Information               c:\prj\sprinter\firmware\97\max\sp047032.rpt
+
+** PIN/LOCATION/CHIP ASSIGNMENTS **
+
+                  Actual                  
+    User       Assignments                
+Assignments   (if different)     Node Name
+
+sp047032@27                       CLK_PRC
+sp047032@13                       CLK_WG
+sp047032@31                       CLKZZ
+sp047032@44                       CNF_ON
+sp047032@40                       /CONFIG
+sp047032@34                       /DTRB
+sp047032@18                       D0
+sp047032@1                        EPM_RES
+sp047032@11                       HD_CSS1
+sp047032@12                       HD_CSS2
+sp047032@9                        HD_CS1
+sp047032@7                        HD_CS2
+sp047032@26                       HDD_CS
+sp047032@8                        HD_OE1
+sp047032@5                        HD_OE2
+sp047032@6                        HD_WE1
+sp047032@4                        HD_WE2
+sp047032@29                       /IO
+sp047032@39                       MA0
+sp047032@36                       MA7
+sp047032@28                       /MR
+sp047032@14                       QDAT
+sp047032@32                       /RD
+sp047032@16                       RDAT
+sp047032@17                       RDATA
+sp047032@21                       RSTB
+sp047032@33                       /RTSB
+sp047032@19                       STE
+sp047032@43                       TG42_IN
+sp047032@41                       TG42_OUT
+sp047032@25                       /WR
+sp047032@24                       /WRH
+sp047032@20                       WSTB
+sp047032@38                       10K_CLK
+sp047032@37                       10K_D0
+
+
+Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp047032.rpt
+sp047032
+
+***** Logic for device 'sp047032' compiled without errors.
+
+
+
+
+Device: EPM7032LC44-12
+
+Device Options:
+    Turbo Bit                                    = ON
+    Security Bit                                 = ON
+
+
+
+Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp047032.rpt
+sp047032
+
+** ERROR SUMMARY **
+
+Info: Chip 'sp047032' in device 'EPM7032LC44-12' has less than 10% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
+Info: Chip 'sp047032' in device 'EPM7032LC44-12' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
+                                         T     
+                             E     T     G  /  
+              H  H  H        P  C  G     4  C  
+              D  D  D        M  N  4     2  O  
+              _  _  _        _  F  2     _  N  
+              W  O  W  V  G  R  _  _  G  O  F  
+              E  E  E  C  N  E  O  I  N  U  I  
+              1  2  2  C  D  S  N  N  D  T  G  
+            -----------------------------------_ 
+          /   6  5  4  3  2  1 44 43 42 41 40   | 
+  HD_CS2 |  7                                39 | MA0 
+  HD_OE1 |  8                                38 | 10K_CLK 
+  HD_CS1 |  9                                37 | 10K_D0 
+     GND | 10                                36 | MA7 
+ HD_CSS1 | 11                                35 | VCC 
+ HD_CSS2 | 12         EPM7032LC44-12         34 | /DTRB 
+  CLK_WG | 13                                33 | /RTSB 
+    QDAT | 14                                32 | /RD 
+     VCC | 15                                31 | CLKZZ 
+    RDAT | 16                                30 | GND 
+   RDATA | 17                                29 | /IO 
+         |_  18 19 20 21 22 23 24 25 26 27 28  _| 
+           ------------------------------------ 
+              D  S  W  R  G  V  /  /  H  C  /  
+              0  T  S  S  N  C  W  W  D  L  M  
+                 E  T  T  D  C  R  R  D  K  R  
+                    B  B        H     _  _     
+                                      C  P     
+                                      S  R     
+                                         C     
+                                               
+
+
+N.C. = No Connect. This pin has no internal connection to the device.
+VCC = Dedicated power pin, which MUST be connected to VCC.
+GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
+RESERVED = Unused I/O pin, which MUST be left unconnected.
+
+
+
+Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp047032.rpt
+sp047032
+
+** RESOURCE USAGE **
+
+                                                Shareable     External
+Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect
+
+A:     LC1 - LC16    16/16(100%)  16/16(100%)  15/16( 93%)  26/36( 72%) 
+B:    LC17 - LC32    16/16(100%)  16/16(100%)  14/16( 87%)  31/36( 86%) 
+
+
+Total dedicated input pins used:                 3/4      ( 75%)
+Total I/O pins used:                            32/32     (100%)
+Total logic cells used:                         32/32     (100%)
+Total shareable expanders used:                 27/32     ( 84%)
+Total Turbo logic cells used:                   20/32     ( 62%)
+Total shareable expanders not available (n/a):   2/32     (  6%)
+Average fan-in:                                  4.50
+Total fan-in:                                   144
+
+Total input pins required:                      17
+Total output pins required:                     18
+Total bidirectional pins required:               0
+Total logic cells required:                     32
+Total flipflops required:                       21
+Total product terms required:                  104
+Total logic cells lending parallel expanders:    0
+Total shareable expanders in database:          25
+
+Synthesized logic cells:                         0/  32   (  0%)
+
+
+
+Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp047032.rpt
+sp047032
+
+** INPUTS **
+
+                                         Shareable
+                                         Expanders     Fan-In    Fan-Out
+ Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
+  44      -   -       INPUT  G            0      0   0    0    0    1    1  CNF_ON
+  34   (23)  (B)      INPUT               0      0   0    0    0    0    2  /DTRB
+  18   (13)  (A)      INPUT               0      0   0    0    0    1    0  D0
+   1      -   -       INPUT               0      0   0    0    0    1    0  EPM_RES
+  26   (30)  (B)      INPUT               0      0   0    0    0   11    5  HDD_CS
+  29   (27)  (B)      INPUT               0      0   0    0    0    4    5  /IO
+  39   (19)  (B)      INPUT               0      0   0    0    0    4    0  MA0
+  36   (22)  (B)      INPUT               0      0   0    0    0    3    0  MA7
+  28   (28)  (B)      INPUT               0      0   0    0    0    4    0  /MR
+  32   (25)  (B)      INPUT               0      0   0    0    0    5    5  /RD
+  17   (12)  (A)      INPUT               0      0   0    0    0    1    1  RDATA
+  21   (16)  (A)      INPUT               0      0   0    0    0    0    1  RSTB
+  33   (24)  (B)      INPUT               0      0   0    0    0    0    0  /RTSB
+  19   (14)  (A)      INPUT               0      0   0    0    0    0    1  STE
+  43      -   -       INPUT               0      0   0    0    0    2    1  TG42_IN
+  25   (31)  (B)      INPUT               0      0   0    0    0    7    0  /WR
+  20   (15)  (A)      INPUT               0      0   0    0    0    0    1  WSTB
+
+
+Code:
+
+s = Synthesized pin or logic cell
+t = Turbo logic cell
++ = Synchronous flipflop
+! = NOT gate push-back
+r = Fitter-inserted logic cell
+G = Global Source. Fan-out destinations counted here do not include destinations
+that are driven using global routing resources. Refer to the Auto Global Signals,
+Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
+Sections of this Report File for information on which signals' fan-outs are used as
+Clock, Clear, Preset, Output Enable, and synchronous Load signals.
+
+
+Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp047032.rpt
+sp047032
+
+** OUTPUTS **
+
+                                         Shareable
+                                         Expanders     Fan-In    Fan-Out
+ Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
+  27     29    B         FF      t        2      2   0    0    2    1    1  CLK_PRC
+  13      9    A         FF      t        2      2   0    0    4    2    1  CLK_WG
+  31     26    B     TRI/FF      t        2      2   0    1    2    1    3  CLKZZ
+  40     18    B     OUTPUT               0      0   0    5    0    0    5  /CONFIG
+  11      7    A     OUTPUT               0      0   0    2    0    0    0  HD_CSS1
+  12      8    A     OUTPUT               0      0   0    2    0    0    0  HD_CSS2
+   9      6    A     OUTPUT               0      0   0    2    0    0    0  HD_CS1
+   7      4    A     OUTPUT               0      0   0    1    1    0    0  HD_CS2
+   8      5    A     OUTPUT               4      4   0    6    2    0    0  HD_OE1
+   5      2    A     OUTPUT               4      4   0    5    1    0    0  HD_OE2
+   6      3    A         FF               0      0   0    3    0    0    0  HD_WE1
+   4      1    A     OUTPUT               4      4   0    4    0    0    0  HD_WE2
+  14     10    A         FF      t        0      0   0    0    6    0    0  QDAT
+  16     11    A         FF      t        4      4   0    1    2    1    4  RDAT
+  41     17    B     OUTPUT      t        1      0   0    1    0    0    0  TG42_OUT
+  24     32    B         FF               1      0   0    5    1    3    0  /WRH
+  38     20    B     OUTPUT               0      0   0    5    0    0    5  10K_CLK
+  37     21    B     OUTPUT               0      0   0    1    1    0    1  10K_D0
+
+
+Code:
+
+s = Synthesized pin or logic cell
+t = Turbo logic cell
++ = Synchronous flipflop
+! = NOT gate push-back
+r = Fitter-inserted logic cell
+
+
+Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp047032.rpt
+sp047032
+
+** BURIED LOGIC **
+
+                                         Shareable
+                                         Expanders     Fan-In    Fan-Out
+ Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
+ (26)    30    B       DFFE      t        4      3   1    4    5    2    2  CODE0
+ (34)    23    B       DFFE      t        3      3   0    3    3    0    1  CODE1
+ (36)    22    B       DFFE      t        3      3   0    3    3    0    2  CODE2
+ (25)    31    B       DFFE      t        3      3   0    3    3    0    1  CODE3
+ (29)    27    B       DFFE      t        3      3   0    3    3    1    0  CODE4
+ (18)    13    A       TFFE      t        5      0   0    4    2    2    2  CT_WG
+ (32)    25    B       TFFE      t        3      0   0    1    2    2    6  CT_WG1
+ (28)    28    B       TFFE      t        2      2   0    1    1    1    0  CT0
+ (19)    14    A       TFFE      t        2      2   0    0    3    1    0  STWG1
+ (33)    24    B       TFFE      t        0      0   0    0    6    1    4  WGR0
+ (39)    19    B       TFFE      t        1      0   1    0    6    1    4  WGR1
+ (17)    12    A       TFFE      t        0      0   0    0    6    1    4  WGR2
+ (20)    15    A       TFFE      t        0      0   0    0    6    1    4  WGR3
+ (21)    16    A       DFFE      t        4      4   0    1    1    1    0  :99
+
+
+Code:
+
+s = Synthesized pin or logic cell
+t = Turbo logic cell
++ = Synchronous flipflop
+! = NOT gate push-back
+r = Fitter-inserted logic cell
+
+
+Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp047032.rpt
+sp047032
+
+** LOGIC CELL INTERCONNECTIONS **
+
+Logic Array Block 'A':
+
+                                         Logic cells placed in LAB 'A'
+        +------------------------------- LC9 CLK_WG
+        | +----------------------------- LC13 CT_WG
+        | | +--------------------------- LC7 HD_CSS1
+        | | | +------------------------- LC8 HD_CSS2
+        | | | | +----------------------- LC6 HD_CS1
+        | | | | | +--------------------- LC4 HD_CS2
+        | | | | | | +------------------- LC5 HD_OE1
+        | | | | | | | +----------------- LC2 HD_OE2
+        | | | | | | | | +--------------- LC3 HD_WE1
+        | | | | | | | | | +------------- LC1 HD_WE2
+        | | | | | | | | | | +----------- LC10 QDAT
+        | | | | | | | | | | | +--------- LC11 RDAT
+        | | | | | | | | | | | | +------- LC14 STWG1
+        | | | | | | | | | | | | | +----- LC12 WGR2
+        | | | | | | | | | | | | | | +--- LC15 WGR3
+        | | | | | | | | | | | | | | | +- LC16 :99
+        | | | | | | | | | | | | | | | | 
+        | | | | | | | | | | | | | | | |   Other LABs fed by signals
+        | | | | | | | | | | | | | | | |   that feed LAB 'A'
+LC      | | | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'A':
+LC9  -> * - - - - - - - - - - - * - - - | * * | <-- CLK_WG
+LC13 -> * * - - - - - - - - - - * - - - | * * | <-- CT_WG
+LC11 -> - - - - - - - - - - * - - * * - | * * | <-- RDAT
+LC14 -> * - - - - - - - - - - - * - - - | * - | <-- STWG1
+LC12 -> - - - - - - - - - - * - - * * - | * * | <-- WGR2
+LC15 -> - - - - - - - - - - * - - * * - | * * | <-- WGR3
+LC16 -> - - - - - - - - - - - * - - - - | * - | <-- :99
+
+Pin
+44   -> - - - - - - - - - - - - - - - - | - * | <-- CNF_ON
+34   -> - * - - - - - - - - - - - - - - | * * | <-- /DTRB
+1    -> - - - - - - - - - - - - - - - - | - * | <-- EPM_RES
+26   -> - - * * * * * * * * - - - - - - | * * | <-- HDD_CS
+29   -> - - - - - - * * - * - - - - - - | * * | <-- /IO
+39   -> - - - - - - * * - * - - - - - - | * * | <-- MA0
+36   -> - - * * - - - - - - - - - - - - | * * | <-- MA7
+28   -> - - - - - - * * - - - - - - - - | * * | <-- /MR
+32   -> - - - - - - * * * - - - - - - - | * * | <-- /RD
+17   -> - - - - - - - - - - - * - - - * | * - | <-- RDATA
+21   -> - * - - - - - - - - - - - - - - | * - | <-- RSTB
+19   -> - * - - - - - - - - - - - - - - | * - | <-- STE
+43   -> - - - - - - - - - - - - - - - - | - * | <-- TG42_IN
+25   -> - - - - * - * - * * - - - - - - | * * | <-- /WR
+20   -> - * - - - - - - - - - - - - - - | * - | <-- WSTB
+LC29 -> * - - - - - - - - - - - * - - - | * - | <-- CLK_PRC
+LC26 -> - * - - - - - - - - - - - - - - | * * | <-- CLKZZ
+LC30 -> - - - - - - * * - - - - - - - - | * * | <-- CODE0
+LC25 -> - - - - - - - - - - * * - * * * | * * | <-- CT_WG1
+LC24 -> - - - - - - - - - - * - - * * - | * * | <-- WGR0
+LC19 -> - - - - - - - - - - * - - * * - | * * | <-- WGR1
+LC32 -> - - - - - * * - - - - - - - - - | * * | <-- /WRH
+
+
+* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
+- = The logic cell or pin is not an input to the logic cell (or LAB).
+
+
+Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp047032.rpt
+sp047032
+
+** LOGIC CELL INTERCONNECTIONS **
+
+Logic Array Block 'B':
+
+                                         Logic cells placed in LAB 'B'
+        +------------------------------- LC29 CLK_PRC
+        | +----------------------------- LC26 CLKZZ
+        | | +--------------------------- LC30 CODE0
+        | | | +------------------------- LC23 CODE1
+        | | | | +----------------------- LC22 CODE2
+        | | | | | +--------------------- LC31 CODE3
+        | | | | | | +------------------- LC27 CODE4
+        | | | | | | | +----------------- LC18 /CONFIG
+        | | | | | | | | +--------------- LC25 CT_WG1
+        | | | | | | | | | +------------- LC28 CT0
+        | | | | | | | | | | +----------- LC17 TG42_OUT
+        | | | | | | | | | | | +--------- LC24 WGR0
+        | | | | | | | | | | | | +------- LC19 WGR1
+        | | | | | | | | | | | | | +----- LC32 /WRH
+        | | | | | | | | | | | | | | +--- LC20 10K_CLK
+        | | | | | | | | | | | | | | | +- LC21 10K_D0
+        | | | | | | | | | | | | | | | | 
+        | | | | | | | | | | | | | | | |   Other LABs fed by signals
+        | | | | | | | | | | | | | | | |   that feed LAB 'B'
+LC      | | | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
+LC26 -> - * - - - - - - * * - - - - - - | * * | <-- CLKZZ
+LC30 -> - - * * - - - - - - - - - - - - | * * | <-- CODE0
+LC23 -> - - - - * - - - - - - - - - - - | - * | <-- CODE1
+LC22 -> - - * - - * - - - - - - - - - - | - * | <-- CODE2
+LC31 -> - - - - - - * - - - - - - - - - | - * | <-- CODE3
+LC27 -> - - - - - - - - - - - - - - - * | - * | <-- CODE4
+LC18 -> - - * * * * * - - - - - - - - - | - * | <-- /CONFIG
+LC25 -> - - - - - - - - * - - * * - - - | * * | <-- CT_WG1
+LC28 -> - * - - - - - - - * - - - - - - | - * | <-- CT0
+LC24 -> - - - - - - - - - - - * * - - - | * * | <-- WGR0
+LC19 -> - - - - - - - - - - - * * - - - | * * | <-- WGR1
+LC32 -> - - - - - - - - - - - - - * - - | * * | <-- /WRH
+LC20 -> - - * * * * * - - - - - - - - - | - * | <-- 10K_CLK
+LC21 -> - - * - - - - - - - - - - - - - | - * | <-- 10K_D0
+
+Pin
+44   -> - - * - - - - - - - - - - - * - | - * | <-- CNF_ON
+34   -> - - - - - - - - * - - - - - - - | * * | <-- /DTRB
+18   -> - - - - - - - - - - - - - - - * | - * | <-- D0
+1    -> - - - - - - - * - - - - - - - - | - * | <-- EPM_RES
+26   -> - - * * * * * * - - - - - * * - | * * | <-- HDD_CS
+29   -> - - * * * * * - - - - - - * - - | * * | <-- /IO
+39   -> - - - - - - - - - - - - - * - - | * * | <-- MA0
+36   -> - - - - - - - * - - - - - - - - | * * | <-- MA7
+28   -> - - - - - - - * - - - - - - * - | * * | <-- /MR
+32   -> - - * * * * * - - - - - - * * - | * * | <-- /RD
+43   -> - * - - - - - - - * * - - - - - | - * | <-- TG42_IN
+25   -> - - - - - - - * - - - - - * * - | * * | <-- /WR
+LC9  -> * - - - - - - - - - - - - - - - | * * | <-- CLK_WG
+LC13 -> * - - - - - - - - - - - - - - - | * * | <-- CT_WG
+LC11 -> - - - - - - - - - - - * * - - - | * * | <-- RDAT
+LC12 -> - - - - - - - - - - - * * - - - | * * | <-- WGR2
+LC15 -> - - - - - - - - - - - * * - - - | * * | <-- WGR3
+
+
+* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
+- = The logic cell or pin is not an input to the logic cell (or LAB).
+
+
+Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp047032.rpt
+sp047032
+
+** EQUATIONS **
+
+CNF_ON   : INPUT;
+D0       : INPUT;
+EPM_RES  : INPUT;
+HDD_CS   : INPUT;
+MA0      : INPUT;
+MA7      : INPUT;
+RDATA    : INPUT;
+RSTB     : INPUT;
+STE      : INPUT;
+TG42_IN  : INPUT;
+WSTB     : INPUT;
+/DTRB    : INPUT;
+/IO      : INPUT;
+/MR      : INPUT;
+/RD      : INPUT;
+/RTSB    : INPUT;
+/WR      : INPUT;
+
+-- Node name is 'CLK_PRC' = 'STWG0' from file "sp047032.tdf" line 53, column 6
+-- Equation name is 'CLK_PRC', location is LC029, type is output.
+ CLK_PRC = TFFE( VCC,  _EQ001,  VCC,  VCC,  VCC);
+  _EQ001 =  _X001 &  _X002;
+  _X001  = EXP(!CLK_WG & !CT_WG);
+  _X002  = EXP( CLK_WG &  CT_WG);
+
+-- Node name is 'CLK_WG' = 'STWG2' from file "sp047032.tdf" line 53, column 6
+-- Equation name is 'CLK_WG', location is LC009, type is output.
+ CLK_WG  = TFFE( _EQ002,  _EQ003,  VCC,  VCC,  VCC);
+  _EQ002 =  CLK_PRC &  STWG1;
+  _EQ003 =  _X001 &  _X002;
+  _X001  = EXP(!CLK_WG & !CT_WG);
+  _X002  = EXP( CLK_WG &  CT_WG);
+
+-- Node name is 'CLKZZ' = 'CT1' from file "sp047032.tdf" line 51, column 4
+-- Equation name is 'CLKZZ', location is LC026, type is output.
+CLKZZ    = TRI(CT1, GLOBAL(!CNF_ON));
+CT1      = TFFE( CT0,  _EQ004,  VCC,  VCC,  VCC);
+  _EQ004 =  _X003 &  _X004;
+  _X003  = EXP( CT1 & !TG42_IN);
+  _X004  = EXP(!CT1 &  TG42_IN);
+
+-- Node name is 'CODE0' from file "sp047032.tdf" line 58, column 6
+-- Equation name is 'CODE0', location is LC030, type is buried.
+CODE0    = DFFE( _EQ005 $  GND,  10K_CLK, !_EQ006,  VCC,  VCC);
+  _EQ005 = !CNF_ON &  CODE2 & !10K_D0
+         # !CNF_ON & !CODE2 &  10K_D0
+         #  CNF_ON & !CODE0;
+  _EQ006 =  _X005 &  _X006 &  _X007;
+  _X005  = EXP( /CONFIG &  /RD);
+  _X006  = EXP( /CONFIG &  /IO);
+  _X007  = EXP( /CONFIG &  HDD_CS);
+
+-- Node name is 'CODE1' from file "sp047032.tdf" line 58, column 6
+-- Equation name is 'CODE1', location is LC023, type is buried.
+CODE1    = DFFE( CODE0 $  GND,  10K_CLK, !_EQ007,  VCC,  VCC);
+  _EQ007 =  _X005 &  _X006 &  _X007;
+  _X005  = EXP( /CONFIG &  /RD);
+  _X006  = EXP( /CONFIG &  /IO);
+  _X007  = EXP( /CONFIG &  HDD_CS);
+
+-- Node name is 'CODE2' from file "sp047032.tdf" line 58, column 6
+-- Equation name is 'CODE2', location is LC022, type is buried.
+CODE2    = DFFE( CODE1 $  GND,  10K_CLK, !_EQ008,  VCC,  VCC);
+  _EQ008 =  _X005 &  _X006 &  _X007;
+  _X005  = EXP( /CONFIG &  /RD);
+  _X006  = EXP( /CONFIG &  /IO);
+  _X007  = EXP( /CONFIG &  HDD_CS);
+
+-- Node name is 'CODE3' from file "sp047032.tdf" line 58, column 6
+-- Equation name is 'CODE3', location is LC031, type is buried.
+CODE3    = DFFE( CODE2 $  GND,  10K_CLK, !_EQ009,  VCC,  VCC);
+  _EQ009 =  _X005 &  _X006 &  _X007;
+  _X005  = EXP( /CONFIG &  /RD);
+  _X006  = EXP( /CONFIG &  /IO);
+  _X007  = EXP( /CONFIG &  HDD_CS);
+
+-- Node name is 'CODE4' from file "sp047032.tdf" line 58, column 6
+-- Equation name is 'CODE4', location is LC027, type is buried.
+CODE4    = DFFE( CODE3 $  GND,  10K_CLK, !_EQ010,  VCC,  VCC);
+  _EQ010 =  _X005 &  _X006 &  _X007;
+  _X005  = EXP( /CONFIG &  /RD);
+  _X006  = EXP( /CONFIG &  /IO);
+  _X007  = EXP( /CONFIG &  HDD_CS);
+
+-- Node name is 'CT_WG' from file "sp047032.tdf" line 113, column 11
+-- Equation name is 'CT_WG', location is LC013, type is buried.
+CT_WG    = TFFE( VCC,  _EQ011,  VCC,  VCC,  VCC);
+  _EQ011 =  _X008 &  _X009 &  _X010;
+  _X008  = EXP(!CT_WG & !CT1);
+  _X009  = EXP( CT_WG &  CT1 &  _X011);
+  _X010  = EXP(!CT1 & !/DTRB & !STE &  _X012);
+  _X011  = EXP(!/DTRB & !STE &  _X012);
+  _X012  = EXP(!RSTB & !WSTB &  _X011);
+
+-- Node name is 'CT_WG1' from file "sp047032.tdf" line 115, column 12
+-- Equation name is 'CT_WG1', location is LC025, type is buried.
+CT_WG1   = TFFE( VCC,  _EQ012,  VCC,  VCC,  VCC);
+  _EQ012 =  _X013 &  _X014 &  _X015;
+  _X013  = EXP(!CT_WG1 & !CT1);
+  _X014  = EXP( CT_WG1 &  CT1 &  /DTRB);
+  _X015  = EXP(!CT1 & !/DTRB);
+
+-- Node name is 'CT0' from file "sp047032.tdf" line 51, column 4
+-- Equation name is 'CT0', location is LC028, type is buried.
+CT0      = TFFE( VCC,  _EQ013,  VCC,  VCC,  VCC);
+  _EQ013 =  _X003 &  _X004;
+  _X003  = EXP( CT1 & !TG42_IN);
+  _X004  = EXP(!CT1 &  TG42_IN);
+
+-- Node name is 'HD_CSS1' 
+-- Equation name is 'HD_CSS1', location is LC007, type is output.
+ HD_CSS1 = LCELL( _EQ014 $  VCC);
+  _EQ014 = !HDD_CS & !MA7;
+
+-- Node name is 'HD_CSS2' 
+-- Equation name is 'HD_CSS2', location is LC008, type is output.
+ HD_CSS2 = LCELL( _EQ015 $  VCC);
+  _EQ015 = !HDD_CS &  MA7;
+
+-- Node name is 'HD_CS1' 
+-- Equation name is 'HD_CS1', location is LC006, type is output.
+ HD_CS1  = LCELL( _EQ016 $  VCC);
+  _EQ016 = !HDD_CS & !/WR;
+
+-- Node name is 'HD_CS2' = ':108' from file "sp047032.tdf" line 196, column 12
+-- Equation name is 'HD_CS2', type is output 
+ HD_CS2  = LCELL( _EQ017 $  VCC);
+  _EQ017 = !HDD_CS & !/WRH;
+
+-- Node name is 'HD_OE1' 
+-- Equation name is 'HD_OE1', location is LC005, type is output.
+ HD_OE1  = LCELL( _EQ018 $  VCC);
+  _EQ018 = !HDD_CS & !/IO &  MA0 & !/WR &  /WRH &  _X016
+         # !HDD_CS & !/IO &  MA0 & !/RD &  _X016
+         #  CODE0 & !HDD_CS & !/MR & !/RD;
+  _X016  = EXP( _X017);
+  _X017  = EXP( _X018);
+  _X018  = EXP( _X019);
+  _X019  = EXP(!HDD_CS);
+
+-- Node name is 'HD_OE2' 
+-- Equation name is 'HD_OE2', location is LC002, type is output.
+ HD_OE2  = LCELL( _EQ019 $  VCC);
+  _EQ019 = !HDD_CS & !/IO & !MA0 & !/RD &  _X016
+         # !CODE0 & !HDD_CS & !/MR & !/RD;
+  _X016  = EXP( _X017);
+  _X017  = EXP( _X018);
+  _X018  = EXP( _X019);
+  _X019  = EXP(!HDD_CS);
+
+-- Node name is 'HD_WE1' = ':115' from file "sp047032.tdf" line 211, column 12
+-- Equation name is 'HD_WE1', type is output 
+ HD_WE1  = DFFE( GND $  GND, !HDD_CS,  VCC, !_EQ020,  VCC);
+  _EQ020 =  /RD &  /WR;
+
+-- Node name is 'HD_WE2' 
+-- Equation name is 'HD_WE2', location is LC001, type is output.
+ HD_WE2  = LCELL( _EQ021 $  VCC);
+  _EQ021 = !HDD_CS & !/IO &  MA0 & !/WR &  _X016;
+  _X016  = EXP( _X017);
+  _X017  = EXP( _X018);
+  _X018  = EXP( _X019);
+  _X019  = EXP(!HDD_CS);
+
+-- Node name is 'QDAT' = 'WGR4' from file "sp047032.tdf" line 54, column 5
+-- Equation name is 'QDAT', location is LC010, type is output.
+ QDAT    = TFFE( _EQ022,  CT_WG1,  VCC,  VCC,  VCC);
+  _EQ022 =  RDAT &  WGR0 &  WGR1 &  WGR2 &  WGR3;
+
+-- Node name is 'RDAT' = ':98' from file "sp047032.tdf" line 153, column 9
+-- Equation name is 'RDAT', type is output 
+ RDAT    = DFFE( _EQ023 $  VCC,  CT_WG1,  VCC,  VCC,  VCC);
+  _EQ023 =  _LC016 &  _X020 &  _X021;
+  _X020  = EXP(!CT_WG1 &  RDATA);
+  _X021  = EXP( _X022 &  _X023);
+  _X022  = EXP(!CT_WG1 & !RDATA);
+  _X023  = EXP( _X020 &  _X021);
+
+-- Node name is 'STWG1' from file "sp047032.tdf" line 53, column 6
+-- Equation name is 'STWG1', location is LC014, type is buried.
+STWG1    = TFFE( CLK_PRC,  _EQ024,  VCC,  VCC,  VCC);
+  _EQ024 =  _X001 &  _X002;
+  _X001  = EXP(!CLK_WG & !CT_WG);
+  _X002  = EXP( CLK_WG &  CT_WG);
+
+-- Node name is 'TG42_OUT' 
+-- Equation name is 'TG42_OUT', location is LC017, type is output.
+ TG42_OUT = LCELL( _EQ025 $  GND);
+  _EQ025 =  _X024;
+  _X024  = EXP( TG42_IN);
+
+-- Node name is 'WGR0' from file "sp047032.tdf" line 54, column 5
+-- Equation name is 'WGR0', location is LC024, type is buried.
+WGR0     = TFFE( _EQ026,  CT_WG1,  VCC,  VCC,  VCC);
+  _EQ026 =  WGR0 &  WGR1 &  WGR2 & !WGR3
+         # !WGR0 & !WGR1 & !WGR2 &  WGR3
+         #  RDAT;
+
+-- Node name is 'WGR1' from file "sp047032.tdf" line 54, column 5
+-- Equation name is 'WGR1', location is LC019, type is buried.
+WGR1     = TFFE( _EQ027,  CT_WG1,  VCC,  VCC,  VCC);
+  _EQ027 =  RDAT & !WGR0 & !WGR1 & !WGR2 & !WGR3
+         # !RDAT & !WGR1 &  WGR2 & !WGR3
+         # !RDAT &  WGR1 & !WGR3
+         #  RDAT &  WGR0;
+
+-- Node name is 'WGR2' from file "sp047032.tdf" line 54, column 5
+-- Equation name is 'WGR2', location is LC012, type is buried.
+WGR2     = TFFE( _EQ028,  CT_WG1,  VCC,  VCC,  VCC);
+  _EQ028 = !RDAT &  WGR1 &  WGR2 & !WGR3
+         #  RDAT &  WGR0 &  WGR1
+         # !RDAT & !WGR2 & !WGR3;
+
+-- Node name is 'WGR3' from file "sp047032.tdf" line 54, column 5
+-- Equation name is 'WGR3', location is LC015, type is buried.
+WGR3     = TFFE( _EQ029,  CT_WG1,  VCC,  VCC,  VCC);
+  _EQ029 =  RDAT &  WGR0 &  WGR1 &  WGR2 &  WGR3
+         #  WGR0 &  WGR1 &  WGR2 & !WGR3
+         # !RDAT &  WGR1 &  WGR2 & !WGR3;
+
+-- Node name is '10K_CLK' = ':87' from file "sp047032.tdf" line 75, column 13
+-- Equation name is '10K_CLK', type is output 
+ 10K_CLK = LCELL( _EQ030 $  VCC);
+  _EQ030 =  CNF_ON & !HDD_CS & !/MR & !/RD
+         # !CNF_ON & !/MR & !/WR;
+
+-- Node name is '10K_D0' = ':88' from file "sp047032.tdf" line 86, column 12
+-- Equation name is '10K_D0', type is output 
+ 10K_D0  = LCELL( CODE4 $  D0);
+
+-- Node name is '/CONFIG' = ':117' from file "sp047032.tdf" line 227, column 12
+-- Equation name is '/CONFIG', type is output 
+ /CONFIG = LCELL( _EQ031 $  EPM_RES);
+  _EQ031 =  EPM_RES & !HDD_CS & !MA7 & !/MR & !/WR;
+
+-- Node name is '/WRH' = ':116' from file "sp047032.tdf" line 223, column 9
+-- Equation name is '/WRH', type is output 
+ /WRH    = DFFE( _EQ032 $  VCC,  _EQ033, !_EQ034,  VCC,  VCC);
+  _EQ032 =  MA0 & !/WRH;
+  _EQ033 =  _X025;
+  _X025  = EXP(!HDD_CS & !/IO & !/WR);
+  _EQ034 = !HDD_CS & !/IO & !/RD;
+
+-- Node name is ':99' from file "sp047032.tdf" line 153, column 25
+-- Equation name is '_LC016', type is buried 
+_LC016   = DFFE( _EQ035 $  GND,  CT_WG1,  VCC,  VCC,  VCC);
+  _EQ035 =  _X023;
+  _X023  = EXP( _X020 &  _X021);
+  _X020  = EXP(!CT_WG1 &  RDATA);
+  _X021  = EXP( _X022 &  _X023);
+  _X022  = EXP(!CT_WG1 & !RDATA);
+
+
+
+--     Shareable expanders that are duplicated in multiple LABs:
+--    _X001 occurs in LABs A, B
+--    _X002 occurs in LABs A, B
+
+
+
+
+Project Information               c:\prj\sprinter\firmware\97\max\sp047032.rpt
+
+** COMPILATION SETTINGS & TIMES **
+
+Processing Menu Commands
+------------------------
+
+Design Doctor                             = off
+
+Logic Synthesis:
+
+   Synthesis Type Used                    = Standard
+
+   Default Synthesis Style                = NORMAL
+
+      Logic option settings in 'NORMAL' style for 'MAX7000' family
+
+      DECOMPOSE_GATES                     = on
+      DUPLICATE_LOGIC_EXTRACTION          = on
+      MINIMIZATION                        = full
+      MULTI_LEVEL_FACTORING               = on
+      NOT_GATE_PUSH_BACK                  = on
+      PARALLEL_EXPANDERS                  = off
+      REDUCE_LOGIC                        = on
+      REFACTORIZATION                     = on
+      REGISTER_OPTIMIZATION               = on
+      RESYNTHESIZE_NETWORK                = on
+      SLOW_SLEW_RATE                      = off
+      SOFT_BUFFER_INSERTION               = on
+      SUBFACTOR_EXTRACTION                = on
+      TURBO_BIT                           = on
+      XOR_SYNTHESIS                       = on
+      IGNORE_SOFT_BUFFERS                 = off
+      USE_LPM_FOR_AHDL_OPERATORS          = off
+
+   Other logic synthesis settings:
+
+      Automatic Global Clock              = off
+      Automatic Global Clear              = off
+      Automatic Global Preset             = off
+      Automatic Global Output Enable      = off
+      Automatic Fast I/O                  = off
+      Automatic Register Packing          = off
+      Automatic Open-Drain Pins           = on
+      Automatic Implement in EAB          = off
+      One-Hot State Machine Encoding      = off
+      Optimize                            = 0
+
+Default Timing Specifications: None
+
+Cut All Bidir Feedback Timing Paths       = on
+Cut All Clear & Preset Timing Paths       = on
+
+Ignore Timing Assignments                 = off
+
+Functional SNF Extractor                  = off
+
+Linked SNF Extractor                      = off
+Timing SNF Extractor                      = on
+Optimize Timing SNF                       = off
+Generate AHDL TDO File                    = off
+Fitter Settings                           = ADVANCED
+Smart Recompile                           = on
+Total Recompile                           = off
+
+Interfaces Menu Commands
+------------------------
+
+EDIF Netlist Writer                       = off
+Verilog Netlist Writer                    = off
+VHDL Netlist Writer                       = off
+
+Compilation Times
+-----------------
+
+   Compiler Netlist Extractor             00:00:00
+   Database Builder                       00:00:00
+   Logic Synthesizer                      00:00:00
+   Partitioner                            00:00:00
+   Fitter                                 00:00:00
+   Timing SNF Extractor                   00:00:00
+   Assembler                              00:00:00
+   --------------------------             --------
+   Total Time                             00:00:00
+
+
+Memory Allocated
+-----------------
+
+Peak memory allocated during compilation  = 3,646K

pcb/converted/readme.txt

@@ -0,0 +1,38 @@
+SPRINT05.BD1 - файл, полученный конвертацией из оригинального SPRINT05.PCB ghb при помощи пакета OrCAD 32bit version
+SPRINT05.max - результат импорта SPRINT05.BD1 в OrCAD 7.10
+SPRINT05.MIN - файл, полученный экспортом из OrCAD 7.10 для загрузки в DipTrace
+SPRINT05_PCAD.PCB - файл, полученный экспортом из DipTrace
+
+
+Общий порядок "конвертации" следующий:
+
+1. берем файл *.brd от orcad версии 2.xx, который в формате PCB2 (это тот который у нас)
+
+2. берем версию оркада 386+, уже 32-битную. это оркад 3.хх, который несовместим ни с чем (так же как и 2.хх ни с чем). 
+в нем есть утилита frompcb2.exe, которая преобразует наш 16-битный формат PCB2 в 32-битный PCB386+
+
+3. 32-битный формат потом нужно сконвертировать в "современный" оркадовский *.max (в таком формате файлы от 2003 платы). 
+это можно сделать утилитой tomax.exe из установленного оркада, в принципе любой версии. в оркаде 9 есть такая. 
+
+ну в целом через ассоциации расширений можно скормить файл в формате PCB386+ именно в orcad layout и будет то же самое.
+
+4. на выходе получим окадовский *.max с сопутствующими последующими квестами, которые я описал как "Открываем оригинальные файлы схемы и платы sp2003 (https://reverse.sprinter.ru/orcad920)".
+
+там, напомню, последовательность такая:
+orcad max -> текстовый MIN Interchange (который хавает только DipTrace)
+далее MIN Interchange -> DipTrace
+далее DipTrace -> текстовый pcad ascii
+
+
+
+по факту файл оброс:
+1. на КАЖДЫЙ компонент был создан СВОЙ паттерн (о чем я говорил не так давно). база данных ессно в труху, но зато визуально все компоненты в правильной ориентации ))
+2. неправильно транслировались линии в шелке. тут та же ошибка что совершил и я — замкнуты все точки, не учитывается флаг начала линии.
+3. все эти линии раскопированы на все assy слои и еще на какие то левые.
+4. создано куча левых слоев. так то не мешают, в них почти нет никакой инфы.
+5. поехавшие (немного) шрифты. ну это фигня, это всегда.
+
+
+
+
+Всегда Ваш, RomanRom2

pcb/parsed/readme.txt

@@ -0,0 +1,14 @@
+Файлы, полученные парсером оригинального файла OrCAD 2.00 и генератором в формат p-cad ASCII version 7.5
+
+SPRINT05.BRD - оригинальный файл OrCAD 2.00
+sprint05_pcad.pcb - результат работы парсера
+sprint05_pcad_fixed.pcb - исправлено немного ошибок в ориентации некоторых компонентов
+sprint05_pcad_fixed_bot.png
+sprint05_pcad_fixed_top.png
+
+sprint05_pcad_fixed.pcb - вариант, который проходит DRC. для этого тут минимальные косметические изменения, которые вы даже не заметите )
+
+1. сдвинуто несколько via и несколько линий дорожек на 5-10mil, что бы уложиться в параметры DRC
+2. подвинуты надписи с той же целью
+3. раздвинуты границы платы с той же целью
+4. там где не было проложено дорожек, но сеть имелась — дорожки допроложены. в двух местах.   

pcb/php-builder/builder.php

@@ -0,0 +1,113 @@
+<?php
+
+// builder
+// ================================================================================================
+
+// library   
+// - pad
+// - via
+// - text
+// - pattern
+// - component
+
+// netlist
+// - component
+// - net
+
+// pcb design
+// - pcbDesignHeader
+// - layerDef
+// - multiLayer
+//   - via
+//   - pattern
+
+// - layerContents 1 - top
+//   - line
+//   - text
+// - layerContents 2 - bottom
+//   - line
+//   - text
+// - layerContents 3 - board
+//   - line
+//   - polygon
+
+// - layersStackup
+
+
+
+// create header
+// ================================================================================================
+$out_file = "p/" . $proj[$PROJ_ID]['dir'] . "/sprint05_pcad.pcb";
+$ascii = "SPRINT05_PCAD.PCB";
+$ts = date("Y m d H i s");
+$cr = "Copyright © 2009-".date("Y")." Sprinter Reverse Team";
+
+$hdr = "ACCEL_ASCII \"$ascii\"\r\n";
+$hdr .= "\r\n";
+$hdr .= "(asciiHeader\r\n";
+$hdr .= "  (asciiVersion 3 0)\r\n";
+$hdr .= "  (timeStamp $ts)\r\n";
+$hdr .= "  (program \"Sprinter php parser\" \"01.00.1234\")\r\n";
+$hdr .= "  (copyright \"$cr\")\r\n";
+$hdr .= "  (fileAuthor \"RomanRom2\")\r\n";
+$hdr .= "  (headerString \"\")\r\n";
+$hdr .= "  (fileUnits Mil)\r\n";
+$hdr .= "  (guidString \"\")\r\n";
+$hdr .= ")\r\n";
+
+file_put_contents($out_file, $hdr, LOCK_EX);
+
+
+
+// create library
+// ================================================================================================
+
+// lib begin
+$pcad_lib  = "(library \"Library_1\"\r\n";
+file_put_contents($out_file, $pcad_lib, FILE_APPEND | LOCK_EX);
+
+include("p/" . $proj[$PROJ_ID]['dir'] . "/lib_via.php");
+include("p/" . $proj[$PROJ_ID]['dir'] . "/lib_text.php");
+include("p/" . $proj[$PROJ_ID]['dir'] . "/lib_pad.php");
+include("p/" . $proj[$PROJ_ID]['dir'] . "/lib_pattern.php");
+include("p/" . $proj[$PROJ_ID]['dir'] . "/lib_component.php");
+
+// lib end
+$pcad_lib = ")\r\n";
+file_put_contents($out_file, $pcad_lib, FILE_APPEND | LOCK_EX);
+
+
+
+// create netlist
+// ================================================================================================
+
+// netlist begin
+$pcad_net  = "(netlist \"Netlist_1\"\r\n";
+file_put_contents($out_file, $pcad_net, FILE_APPEND | LOCK_EX);
+
+include("p/" . $proj[$PROJ_ID]['dir'] . "/net.php");
+
+// netlist end
+$pcad_net = ")\r\n";
+file_put_contents($out_file, $pcad_net, FILE_APPEND | LOCK_EX);
+
+
+
+// create pcb design
+// ================================================================================================
+
+// pcb begin
+$pcad_pcb  = "(pcbDesign \"PcbDesign_1\"\r\n";
+file_put_contents($out_file, $pcad_pcb, FILE_APPEND | LOCK_EX);
+
+include("p/" . $proj[$PROJ_ID]['dir'] . "/pcb_header.php");
+include("p/" . $proj[$PROJ_ID]['dir'] . "/pcb_layerdef.php");
+include("p/" . $proj[$PROJ_ID]['dir'] . "/pcb_multilayer.php");
+include("p/" . $proj[$PROJ_ID]['dir'] . "/pcb_layers.php");
+include("p/" . $proj[$PROJ_ID]['dir'] . "/pcb_stackup.php");
+
+// pcb end
+$pcad_pcb = ")\r\n";
+file_put_contents($out_file, $pcad_pcb, FILE_APPEND | LOCK_EX);
+
+

pcb/php-builder/lib_component.php

@@ -0,0 +1,42 @@
+<?php
+
+// component
+// ================================================================================================
+echo"save components: ".$pcb->HDR['comp_count_real']['v']."<br>";
+$pcad_lib  = "";
+for($i=0; $i<sizeof($pcb->PATTERN_STYLE); $i++)
+{
+	$PTR = $pcb->PATTERN_STYLE[$i];
+
+	$pcad_lib .= "  (compDef \"".$PTR['name']."_1\"\r\n";
+	$pcad_lib .= "    (originalName \"".$PTR['name']."\")\r\n";
+	$pcad_lib .= "    (compHeader\r\n";
+	$pcad_lib .= "      (sourceLibrary \"\")\r\n";
+	$pcad_lib .= "      (numPins ".$PTR['pads_count'].")\r\n";
+	$pcad_lib .= "      (numParts 1)\r\n";
+	$pcad_lib .= "      (alts (ieeeAlt True) (deMorganAlt False))\r\n";
+	$pcad_lib .= "      (refDesPrefix \"U\")\r\n";
+	$pcad_lib .= "    )\r\n";
+
+	for ($j=1; $j<=$PTR['pads_count']; $j++)
+	{
+		$pad_des = $PTR['pad'.$j.'_des'];
+		$pcad_lib .= "    (compPin \"$pad_des\" (pinName \"$pad_des\") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) )\r\n";
+	}
+
+	$pcad_lib .= "    (attachedPattern (patternNum 1) (patternName \"".$PTR['name']."\")\r\n";
+	$pcad_lib .= "      (numPads ".$PTR['pads_count'].")\r\n";
+	$pcad_lib .= "      (padPinMap\r\n";
+
+	for ($j=1; $j<=$PTR['pads_count']; $j++)
+	{
+		$pad_des = $PTR['pad'.$j.'_des'];
+		$pcad_lib .= "        (padNum $j) (compPinRef \"$pad_des\")\r\n";
+	}
+
+	$pcad_lib .= "      )\r\n";
+	$pcad_lib .= "    )\r\n";
+	$pcad_lib .= "  )\r\n";
+
+}
+file_put_contents($out_file, $pcad_lib, FILE_APPEND | LOCK_EX);

pcb/php-builder/lib_pad.php

@@ -0,0 +1,96 @@
+<?php
+
+// pad
+// ================================================================================================
+function padGetStyle($pcb, $pad)
+{
+	for ($i=0; $i < sizeof($pcb->PAD_STYLE); $i++)
+	{
+		$style = $pcb->PAD_STYLE[$i];
+		if ( 
+			($style['shape'] == $pad['shape']) 
+			and ($style['width'] == $pad['width'])
+			and ($style['height'] == $pad['height'])
+			and ($style['hole_dia'] == $pad['hole_dia'])
+			and ($style['flags'] == $pad['flags'])
+		)
+			return $style['name'];
+	}
+
+	return false;
+}
+function padAddStyle($pcb, $pad)
+{
+	$st = padGetStyle($pcb, $pad);
+	if ($st)
+		return false;
+
+	$i = sizeof($pcb->PAD_STYLE);
+	$pcb->PAD_STYLE[$i]['shape'] = $pad['shape'];
+	$pcb->PAD_STYLE[$i]['width'] = $pad['width'];
+	$pcb->PAD_STYLE[$i]['height'] = $pad['height'];
+	$pcb->PAD_STYLE[$i]['hole_dia'] = $pad['hole_dia'];
+	$pcb->PAD_STYLE[$i]['flags'] = $pad['flags'];
+	$pcb->PAD_STYLE[$i]['name'] = "pad".$i;
+
+	return $pcb->PAD_STYLE[$i]['name'];
+}
+
+echo"<br>";
+echo"generate pad styles...<br>";
+for($i=0; $i<=$pcb->HDR['comp_count_real']['v']; $i++)
+{
+	$C = $pcb->COMP[$i];
+
+	for ($j=1; $j<=$C['pads_count']['v']; $j++)
+	{
+		$pad['shape'] = $C['pad'.$j.'_shape']['v'];
+		$pad['width'] = $C['pad'.$j.'_width']['v'];
+		$pad['height'] = $C['pad'.$j.'_height']['v'];
+		$pad['hole_dia'] = $C['pad'.$j.'_hole_dia']['v'];
+		$pad['flags'] = $C['pad'.$j.'_flags']['v'];
+
+		if ($pad_style = padAddStyle($pcb, $pad))
+		{
+			echo"comp [$i], pad [$j], added new pad {";
+			echo"shape=".$pad['shape']."";
+			echo", hole_dia=".$pad['hole_dia']."";
+			echo", size=".$pad['width']."x".$pad['height']."";
+			echo", flags=".$pad['flags']."";
+			echo"}, style=[$pad_style]<br>";
+		}
+
+		$pcb->COMP[$i]['pad'.$j.'_style']['v'] = padGetStyle($pcb, $pad);
+	}
+}
+echo"save pad styles: ".sizeof($pcb->PAD_STYLE)."<br>";
+$pcad_lib =  "";
+for ($i=0; $i<sizeof($pcb->PAD_STYLE); $i++)
+{
+	$pcad_lib .= "  (padStyleDef \"".$pcb->PAD_STYLE[$i]['name']."\"\r\n";
+	$pcad_lib .= "    (holeDiam ".$pcb->PAD_STYLE[$i]['hole_dia'].")\r\n";
+	$pcad_lib .= "    (StartRange 1)\r\n";
+	$pcad_lib .= "    (EndRange 2)\r\n";
+
+	$s1 = "Ellipse"; if ($pcb->PAD_STYLE[$i]['shape'] == 2) $s1 = "Rect";
+	$w1 = $pcb->PAD_STYLE[$i]['width'];
+	$h1 = $pcb->PAD_STYLE[$i]['height'];
+
+	$w2 = $w1;
+	$h2 = $w1;
+	$s2 = $s1;
+	if (!$pcb->PAD_STYLE[$i]['hole_dia'])
+	{
+		$w2 = "0";
+		$h2 = "0";
+		$s2 = "NoConnect";
+	}
+	$pcad_lib .= "    (padShape (layerNumRef 1) (padShapeType $s1) (shapeWidth $w1) (shapeHeight $h1) )\r\n";
+	$pcad_lib .= "    (padShape (layerNumRef 2) (padShapeType $s2) (shapeWidth $w2) (shapeHeight $h2) )\r\n";
+	$pcad_lib .= "    (padShape (layerType Signal) (padShapeType $s2) (shapeWidth $w2) (shapeHeight $h2) )\r\n";
+	$pcad_lib .= "    (padShape (layerType Plane) (padShapeType NoConnect) (shapeWidth 0) (shapeHeight 0) )\r\n";
+	$pcad_lib .= "    (padShape (layerType NonSignal) (padShapeType NoConnect) (shapeWidth 0) (shapeHeight 0) )\r\n";
+	$pcad_lib .= "  )\r\n";
+
+}
+file_put_contents($out_file, $pcad_lib, FILE_APPEND | LOCK_EX);

pcb/php-builder/lib_pattern.php

@@ -0,0 +1,162 @@
+<?php
+
+// pattern
+// ================================================================================================
+function patternGetStyle($pcb, $pattern, $ind)
+{
+	for ($i=0; $i < sizeof($pcb->PATTERN_STYLE); $i++)
+	{
+		$style = $pcb->PATTERN_STYLE[$i];
+
+		// 1. name
+		$pattern_name_bool = strtoupper($style['pattern']) == strtoupper($pattern['pattern']);
+
+		// 2. pads count
+		if ($pattern_name_bool)
+		{
+			$pads_count_bool = $style['pads_count'] == $pattern['pads_count'];
+			if (!$pads_count_bool) 
+				return false;
+
+			// 3. pad styles
+			for ($j=1; $j<=$pattern['pads_count']; $j++)
+			{
+				$pad_style_bool = $style['pad'.$j.'_style'] == $pattern['pad'.$j.'_style'];
+				if (!$pad_style_bool) 
+					break;
+			}
+
+			if (!$pad_style_bool) 
+				continue;
+
+			return $style;
+		}
+	}
+
+	return false;
+}
+function patternCheckName($pcb, $name)
+{
+	for ($i=0; $i < sizeof($pcb->PATTERN_STYLE); $i++)
+	{
+		$style = $pcb->PATTERN_STYLE[$i];
+		if ($style['name'] == $name)
+			return $name."_".$i;
+	}
+	return $name;
+}
+function patternAddStyle($pcb, $pattern, $ind)
+{
+	$st = patternGetStyle($pcb, $pattern, $ind);
+	if ($st['name'])
+		return false;
+
+	$i = sizeof($pcb->PATTERN_STYLE);
+	$pcb->PATTERN_STYLE[$i] = $pattern;                               
+	$pcb->PATTERN_STYLE[$i]['name'] = patternCheckName($pcb, strtoupper($pattern['pattern']));
+//	$pcb->PATTERN_STYLE[$i]['rotate'] = strtoupper($pattern['rotate']);
+
+	return $pcb->PATTERN_STYLE[$i]['name'];
+}
+
+echo"<br>";
+echo"generate patterns...<br>";
+for($i=1; $i<=$pcb->HDR['comp_count_real']['v']; $i++)
+{
+	$C = $pcb->COMP[$i];
+
+	$pattern = array();
+	$pattern['pattern'] = $C['pattern']['v'];
+	$pattern['rotate'] = $C['rotate']['v'];
+	$pattern['pads_count'] = $C['pads_count']['v'];
+
+	for ($j=1; $j<=$pattern['pads_count']; $j++)
+	{
+		$pattern['pad'.$j.'_num'] = $j;
+		$pattern['pad'.$j.'_style'] = $C['pad'.$j.'_style']['v'];
+		$pattern['pad'.$j.'_rotate'] = $C['pad'.$j.'_rotate']['v'];
+		$pattern['pad'.$j.'_pos_x'] = $C['pos_x']['v'] - $C['pad'.$j.'_pos_x']['v'];
+		$pattern['pad'.$j.'_pos_y'] = $C['pos_y']['v'] - $C['pad'.$j.'_pos_y']['v'];
+		$pattern['pad'.$j.'_des'] = $C['pad'.$j.'_des']['v'];
+	}
+
+	$pattern['lines_count'] = $C['lines_count']['v'];
+	for ($j=1; $j<=$pattern['lines_count']; $j++)
+	{
+		$pattern['line'.$j.'_pos_x'] = $C['pos_x']['v'] - $C['line'.$j.'_pos_x']['v'];
+		$pattern['line'.$j.'_pos_y'] = $C['pos_y']['v'] - $C['line'.$j.'_pos_y']['v'];
+		$pattern['line'.$j.'_size'] = "8.0";               
+		$pattern['line'.$j.'_flags'] = $C['line'.$j.'_flags']['v'];
+	}
+
+	if ($pattern_style = patternAddStyle($pcb, $pattern, $i))
+	{
+		echo"comp [$i], added NEW pattern {";
+		echo"name=".$pattern['pattern']."";
+		echo", pads=".$pattern['pads_count']."";
+		echo", lines=".$pattern['lines_count']."";
+		echo", style_rotate=".$pattern['rotate']."";
+		echo"}, style=[$pattern_style]<br>";
+	}
+
+	// save pattern style to component
+	$st = patternGetStyle($pcb, $pattern, $i);
+	$pcb->COMP[$i]['style']['v'] = $st['name'];
+	$pcb->COMP[$i]['style_rotate']['v'] = $st['rotate'];
+}
+
+echo"save patterns: ".sizeof($pcb->PATTERN_STYLE)."<br>";
+$pcad_lib  = "";
+for($i=0; $i<sizeof($pcb->PATTERN_STYLE); $i++)
+{
+	$PTR = $pcb->PATTERN_STYLE[$i];
+
+	// begin library pattern
+	$pcad_lib .= "  (patternDefExtended \"".$PTR['name']."_1\"\r\n";
+	$pcad_lib .= "  (originalName \"".$PTR['name']."\")\r\n";
+	$pcad_lib .= "    (patternGraphicsNameRef \"Primary\")\r\n";
+	$pcad_lib .= "    (patternGraphicsDef \r\n";
+	$pcad_lib .= "      (patternGraphicsNameDef \"Primary\")\r\n";
+
+	// multilayer, pads
+	$pcad_lib .= "      (multiLayer \r\n";
+	for ($j=1; $j<=$PTR['pads_count']; $j++)
+	{
+		$rot = ($PTR['pad'.$j.'_rotate'] * 90);
+		$x = $PTR['pad'.$j.'_pos_x'];
+		$y = $PTR['pad'.$j.'_pos_y'];
+
+		$pcad_lib .= "        (pad (padNum $j) (padStyleRef \"".$PTR['pad'.$j.'_style']."\") (pt $y $x) (rotation $rot) (defaultPinDes \"".$PTR['pad'.$j.'_des']."\") )\r\n";
+	}
+	$pcad_lib .= "      )\r\n";
+
+	// layer 6 - top silk
+	$pcad_lib .= "      (layerContents  (layerNumRef  6)\r\n";
+	for ($j=1; $j<$PTR['lines_count']; $j++)
+	{
+		$flags2 = $PTR['line'.($j+1).'_flags'];
+		if (!$flags2) continue; // next point flags = 0, begin other line
+
+		$x1 = $PTR['line'.$j.'_pos_x'];
+		$y1 = $PTR['line'.$j.'_pos_y'];
+
+		$x2 = $PTR['line'.($j+1).'_pos_x'];
+		$y2 = $PTR['line'.($j+1).'_pos_y'];
+
+		$w = $PTR['line'.$j.'_size'];
+
+if ( ($x1 == $x2) and ($y1 == $y2) ) {} else // HACK !!!
+		$pcad_lib .= "        (line (pt $y2 $x2) (pt $y1 $x1) (width $w) )\r\n";
+	}
+//	$rot = ($PTR['pad'.$j.'_rotate'] * 90);     //(rotation $rot) 
+	$pcad_lib .= "        (attr \"RefDes\" \"\" (isVisible False) (justify Center) (textStyleRef \"(DefaultTTF)\") )\r\n";
+	$pcad_lib .= "        (attr \"Type\" \"\" (isVisible False) (justify Center) (textStyleRef \"(DefaultTTF)\") )\r\n";
+	$pcad_lib .= "        (attr \"Value\" \"\" (isVisible False) (justify Center) (textStyleRef \"(DefaultTTF)\") )\r\n";
+	$pcad_lib .= "      )\r\n";
+
+	// end
+	$pcad_lib .= "    )\r\n"; // patternGraphicsDef
+	$pcad_lib .= "  )\r\n"; // patternDefExtended
+
+}
+file_put_contents($out_file, $pcad_lib, FILE_APPEND | LOCK_EX);

pcb/php-builder/lib_text.php

@@ -0,0 +1,102 @@
+<?php
+
+// text
+// ================================================================================================
+function txtGetStyle($pcb, $txt)
+{
+	for ($i=0; $i < sizeof($pcb->TXT_STYLE); $i++)
+	{
+		$style = $pcb->TXT_STYLE[$i];
+		if ( ($style['size_v'] == $txt['size_v']) )
+			return $style['name'];
+	}
+
+	return false;
+}
+function txtAddStyle($pcb, $txt)
+{
+	for ($i=0; $i < sizeof($pcb->TXT_STYLE); $i++)
+	{
+		$style = $pcb->TXT_STYLE[$i];
+		if ( ($style['size_v'] == $txt['size_v']) )
+			return false;
+	}
+
+	$pcb->TXT_STYLE[$i]['size_v'] = $txt['size_v'];
+	$pcb->TXT_STYLE[$i]['name'] = "txt".$i;
+
+	return $pcb->TXT_STYLE[$i]['name'];
+}
+
+echo"<br>";
+echo"generate text styles...<br>";
+for($i=1; $i<=$pcb->HDR['texts_count']['v']; $i++)
+{
+	$T = $pcb->TXT[$i];
+
+	$txt['size_v'] = round(1.5*$T['size_v']['v']);
+
+	if ($txt_style = txtAddStyle($pcb, $txt))
+	{
+			echo"text [$i], added new text {";
+			echo"size_v=".$txt['size_v']."";
+			echo"}, style=[$txt_style]<br>";
+	}
+
+	// save style to text
+	$pcb->TXT[$i]['style']['v'] = txtGetStyle($pcb, $txt);
+}
+echo"save text styles: ".sizeof($pcb->TXT_STYLE)."<br>";
+
+	$pcad_font_stroke  = "    (font\r\n";
+	$pcad_font_stroke .= "      (fontType Stroke)\r\n";
+	$pcad_font_stroke .= "      (fontFamily SanSerif)\r\n";
+	$pcad_font_stroke .= "      (fontFace \"Quality\")\r\n";
+	$pcad_font_stroke .= "      (fontHeight 100)\r\n";
+	$pcad_font_stroke .= "      (strokeWidth 8)\r\n";
+	$pcad_font_stroke .= "    )\r\n";
+
+	$pcad_font_truetype  = "    (font\r\n";
+	$pcad_font_truetype .= "      (fontType TrueType)\r\n";
+	$pcad_font_truetype .= "      (fontFamily Modern)\r\n";
+	$pcad_font_truetype .= "      (fontFace \"Arial\")\r\n";
+	$pcad_font_truetype .= "      (fontHeight 100)\r\n";
+	$pcad_font_truetype .= "      (strokeWidth 10)\r\n";
+	$pcad_font_truetype .= "      (fontWeight 400)\r\n";
+	$pcad_font_truetype .= "      (fontCharSet 0)\r\n";
+	$pcad_font_truetype .= "      (fontOutPrecision 7)\r\n";
+	$pcad_font_truetype .= "      (fontClipPrecision 32)\r\n";
+	$pcad_font_truetype .= "      (fontQuality 1)\r\n";
+	$pcad_font_truetype .= "      (fontPitchAndFamily 6)\r\n";
+	$pcad_font_truetype .= "    )\r\n";
+
+
+	$pcad_lib =  "  (textStyleDef \"(Default)\"\r\n";
+	$pcad_lib .= $pcad_font_stroke;
+	$pcad_lib .= "  )\r\n";
+
+	$pcad_lib .= "  (textStyleDef \"(DefaultTTF)\"\r\n";
+	$pcad_lib .= $pcad_font_stroke;
+	$pcad_lib .= $pcad_font_truetype;
+	$pcad_lib .= "    (textStyleAllowTType True)\r\n";
+	$pcad_lib .= "    (textStyleDisplayTType True)\r\n";
+	$pcad_lib .= "  )\r\n";
+file_put_contents($out_file, $pcad_lib, FILE_APPEND | LOCK_EX);
+
+$pcad_lib =  "";
+for ($i=0; $i<sizeof($pcb->TXT_STYLE); $i++)
+{
+	$pcad_lib .= "  (textStyleDef \"".$pcb->TXT_STYLE[$i]['name']."\"\r\n";
+	$pcad_lib .= "    (font\r\n";
+	$pcad_lib .= "      (fontType Stroke)\r\n";
+	$pcad_lib .= "      (fontFamily SanSerif)\r\n";
+	$pcad_lib .= "      (fontFace \"Quality\")\r\n";
+	$pcad_lib .= "      (fontHeight ".$pcb->TXT_STYLE[$i]['size_v'].")\r\n";
+	$pcad_lib .= "      (strokeWidth 8)\r\n";
+	$pcad_lib .= "    )\r\n";
+	$pcad_lib .= "    (textStyleAllowTType False)\r\n";
+	$pcad_lib .= "    (textStyleDisplayTType False)\r\n";
+	$pcad_lib .= "  )\r\n";
+
+}
+file_put_contents($out_file, $pcad_lib, FILE_APPEND | LOCK_EX);

pcb/php-builder/lib_via.php

@@ -0,0 +1,86 @@
+<?php
+
+// via
+// ================================================================================================
+function viaGetStyle($pcb, $via)
+{
+	for ($i=0; $i < sizeof($pcb->VIA_STYLE); $i++)
+	{
+		$style = $pcb->VIA_STYLE[$i];
+		if ( ($style['shape'] == $via['shape']) and ($style['dia'] == $via['dia']) )
+			return $style['name'];
+	}
+
+	return false;
+}
+function viaAddStyle($pcb, $via)
+{
+	for ($i=0; $i < sizeof($pcb->VIA_STYLE); $i++)
+	{
+		$style = $pcb->VIA_STYLE[$i];
+		if ( ($style['shape'] == $via['shape']) and ($style['dia'] == $via['dia']) )
+			return false;
+	}
+
+	$pcb->VIA_STYLE[$i]['shape'] = $via['shape'];
+	$pcb->VIA_STYLE[$i]['dia'] = $via['dia'];
+	$pcb->VIA_STYLE[$i]['name'] = "via".$i;
+
+	return $pcb->VIA_STYLE[$i]['name'];
+}
+
+echo"generate via styles...<br>";
+for($i=0; $i<=$pcb->HDR['net_points_count']['v']; $i++)
+{
+	$flags = hex($pcb->NETPOI[$i]['flags']['v']);
+	$flags_hdr = substr($flags, 1, 1);
+
+	if ( ($flags_hdr == "6") or ($flags_hdr == "7") ) {} else continue;
+
+	$via['shape'] = $pcb->NETPOI[$i]['size']['v'];
+	$via['dia'] = $via['shape'] / 2;
+
+	if ($via_style = viaAddStyle($pcb, $via))
+	{
+		echo"net point [$i], added new via {shape=".$via['shape'].", dia=".$via['dia']."}, style=[$via_style]<br>";
+	}
+
+	$pcb->NETPOI[$i]['style']['v'] = viaGetStyle($pcb, $via);
+}
+echo"save via styles: ".sizeof($pcb->VIA_STYLE)."<br>";
+	$pcad_lib =  "  (viaStyleDef \"(Default)\"\r\n";
+	$pcad_lib .= "    (holeDiam 18)\r\n";
+	$pcad_lib .= "    (StartRange 1)\r\n";
+	$pcad_lib .= "    (EndRange 2)\r\n";
+	$s = "Ellipse";
+	$w = "40";
+	$h = "40";
+	$pcad_lib .= "    (viaShape (layerNumRef 1) (viaShapeType $s) (shapeWidth $w) (shapeHeight $h) )\r\n";
+	$pcad_lib .= "    (viaShape (layerNumRef 2) (viaShapeType $s) (shapeWidth $w) (shapeHeight $h) )\r\n";
+	$pcad_lib .= "    (viaShape (layerType Signal) (viaShapeType $s) (shapeWidth $w) (shapeHeight $h) )\r\n";
+	$pcad_lib .= "    (viaShape (layerType Plane) (viaShapeType NoConnect) (shapeWidth 0) (shapeHeight 0) )\r\n";
+	$pcad_lib .= "    (viaShape (layerType NonSignal) (viaShapeType NoConnect) (shapeWidth 0) (shapeHeight 0) )\r\n";
+	$pcad_lib .= "  )\r\n";
+file_put_contents($out_file, $pcad_lib, FILE_APPEND | LOCK_EX);
+
+$pcad_lib =  "";
+for ($i=0; $i<sizeof($pcb->VIA_STYLE); $i++)
+{
+	$pcad_lib .= "  (viaStyleDef \"".$pcb->VIA_STYLE[$i]['name']."\"\r\n";
+	$pcad_lib .= "    (holeDiam ".$pcb->VIA_STYLE[$i]['dia'].")\r\n";
+	$pcad_lib .= "    (StartRange 1)\r\n";
+	$pcad_lib .= "    (EndRange 2)\r\n";
+
+	$s = "Ellipse";
+	$w = $pcb->VIA_STYLE[$i]['shape'];
+	$h = $pcb->VIA_STYLE[$i]['shape'];
+
+	$pcad_lib .= "    (viaShape (layerNumRef 1) (viaShapeType $s) (shapeWidth $w) (shapeHeight $h) )\r\n";
+	$pcad_lib .= "    (viaShape (layerNumRef 2) (viaShapeType $s) (shapeWidth $w) (shapeHeight $h) )\r\n";
+	$pcad_lib .= "    (viaShape (layerType Signal) (viaShapeType $s) (shapeWidth $w) (shapeHeight $h) )\r\n";
+	$pcad_lib .= "    (viaShape (layerType Plane) (viaShapeType NoConnect) (shapeWidth 0) (shapeHeight 0) )\r\n";
+	$pcad_lib .= "    (viaShape (layerType NonSignal) (viaShapeType NoConnect) (shapeWidth 0) (shapeHeight 0) )\r\n";
+	$pcad_lib .= "  )\r\n";
+
+}
+file_put_contents($out_file, $pcad_lib, FILE_APPEND | LOCK_EX);

pcb/php-builder/net.php

@@ -0,0 +1,81 @@
+<?php
+
+$pcad_net  = "";
+
+// install components
+for($i=1; $i<=$pcb->HDR['comp_count_real']['v']; $i++)
+{
+	$C = $pcb->COMP[$i];
+
+	$name1 = ValidateRef($C['name1_str']['v']);
+	$name2 = ValidateRef($C['name2_str']['v']);
+	$pattern = $C['style']['v'];
+	$pcad_net .= "  (compInst \"$name1\"\r\n";
+	$pcad_net .= "    (compRef \"".$pattern."_1\")\r\n";
+	$pcad_net .= "    (originalName \"$pattern\")\r\n";
+	$pcad_net .= "    (compValue \"$name2\")\r\n";
+	$pcad_net .= "  )\r\n";
+}
+file_put_contents($out_file, $pcad_net, FILE_APPEND | LOCK_EX);
+
+
+
+echo"generate net list...<br>";
+$net_lists = array();
+for($i=1; $i<=$pcb->HDR['comp_count_real']['v']; $i++)
+{
+	$C = $pcb->COMP[$i];
+	for ($j=1; $j<=$C['pads_count']['v']; $j++)
+	{
+		$net = $C['pad'.$j.'_net']['v'];
+if (!trim($net)) continue;
+
+		if (!in_array($net, $net_list))
+		{
+			$net_list[] = $net; 
+		}
+	}
+}
+echo"nets from components: ".sizeof($net_list)."<br>";
+//for($n=0; $n<sizeof($net_list); $n++) echo"(".$net_list[$n].")"; echo"<br>";
+
+$pcad_net  = "";
+for($n=0; $n<sizeof($net_list); $n++)
+{
+	$net = $net_list[$n];
+	$pcad_net .= "  (net \"".$net."\"\r\n";
+
+	for($i=1; $i<=$pcb->HDR['comp_count_real']['v']; $i++)
+	{
+		$C = $pcb->COMP[$i];
+		for ($j=1; $j<=$C['pads_count']['v']; $j++)
+		{
+			$pad_net = $C['pad'.$j.'_net']['v'];
+			$pad_des = $C['pad'.$j.'_des']['v'];
+			if ($net == $pad_net)
+			{
+				$pcad_net .= "    (node \"".ValidateRef($C['name1_str']['v'])."\" \"$pad_des\")\r\n";
+			}
+		}
+	}
+//*/
+	$pcad_net .= "  )\r\n";
+
+}
+file_put_contents($out_file, $pcad_net, FILE_APPEND | LOCK_EX);
+
+
+echo"generate netclass...<br>";
+$pcad_net  = "  (netClass \"DefaultNetClass\"\r\n";
+for($n=0; $n<sizeof($net_list); $n++)
+{
+	$pcad_net .= "    (netNameRef \"".$net_list[$n]."\")\r\n";
+}
+$pcad_net .= "    (attr \"Width\" \"10\" (textStyleRef \"(Default)\"))\r\n";
+$pcad_net .= "    (attr \"Clearance\" \"10\" (textStyleRef \"(Default)\"))\r\n";
+$pcad_net .= "    (attr \"MaxWidth\" \"1000\" (textStyleRef \"(Default)\"))\r\n";
+$pcad_net .= "    (attr \"MinWidth\" \"1\" (textStyleRef \"(Default)\"))\r\n";
+$pcad_net .= "    (attr \"USE_LAYERS\" \"TOP, BOTTOM\" (textStyleRef \"(Default)\"))\r\n";
+$pcad_net .= "  )\r\n";
+//file_put_contents($out_file, $pcad_net, FILE_APPEND | LOCK_EX);
+

pcb/php-builder/pcb_header.php

@@ -0,0 +1,51 @@
+<?php
+
+$dt = date("d.m.Y");
+$tm = date("H:i:s");
+$work_width = 2 * $pcb->MaxPosX; // "30000";
+$work_height = 2 * $pcb->MaxPosY; // "20000";
+
+$pcad_pcb  = "  (pcbDesignHeader \r\n";
+$pcad_pcb .= "    (workspaceSize $work_width $work_height) ;; MaxX=".$pcb->MaxPosX.", MaxY=".$pcb->MaxPosY."\r\n";
+$pcad_pcb .= "    (gridDfns \r\n";
+//$pcad_pcb .= "      (grid \"0.05mm\")\r\n";
+//$pcad_pcb .= "      (grid \"0.1mm\")\r\n";
+$pcad_pcb .= "      (grid \"5.0mil\")\r\n";
+$pcad_pcb .= "      (grid \"10.0mil\")\r\n";
+$pcad_pcb .= "      (grid \"100.0mil\")\r\n";
+$pcad_pcb .= "    )\r\n";
+$pcad_pcb .= "    (designInfo \r\n";
+$pcad_pcb .= "      (fieldSet \"(Default)\"\r\n";
+$pcad_pcb .= "        (fieldDef \"Date\" \"$dt\")\r\n";
+$pcad_pcb .= "        (fieldDef \"Time\" \"$tm\")\r\n";
+$pcad_pcb .= "        (fieldDef \"Author\" \"\")\r\n";
+$pcad_pcb .= "        (fieldDef \"Revision\" \"\")\r\n";
+$pcad_pcb .= "        (fieldDef \"Title\" \"\")\r\n";
+$pcad_pcb .= "        (fieldDef \"Approved By\" \"\")\r\n";
+$pcad_pcb .= "        (fieldDef \"Checked By\" \"\")\r\n";
+$pcad_pcb .= "        (fieldDef \"Company Name\" \"\")\r\n";
+$pcad_pcb .= "        (fieldDef \"Drawing Number\" \"\")\r\n";
+$pcad_pcb .= "        (fieldDef \"Drawn By\" \"\")\r\n";
+$pcad_pcb .= "        (fieldDef \"Engineer\" \"\")\r\n";
+$pcad_pcb .= "        (fieldDef \"Variant Name\" \"\")\r\n";
+$pcad_pcb .= "        (fieldDef \"Variant Description\" \"\")\r\n";
+$pcad_pcb .= "      )\r\n";
+$pcad_pcb .= "    )\r\n";
+$pcad_pcb .= "    (solderSwell 4.0)\r\n";
+$pcad_pcb .= "    (pasteSwell 0.0)\r\n";
+$pcad_pcb .= "    (planeSwell 20.0)\r\n";
+$pcad_pcb .= "    (refPointSize 100.0)\r\n";
+$pcad_pcb .= "    (infoPointSize 100.0)\r\n";
+$pcad_pcb .= "    (gluePointSize 100.0)\r\n";
+$pcad_pcb .= "    (pickPointSize 100.0)\r\n";
+$pcad_pcb .= "    (testPointSize 100.0)\r\n";
+$pcad_pcb .= "    (refPointSizePrint 100.0)\r\n";
+$pcad_pcb .= "    (infoPointSizePrint 100.0)\r\n";
+$pcad_pcb .= "    (gluePointSizePrint 100.0)\r\n";
+$pcad_pcb .= "    (pickPointSizePrint 100.0)\r\n";
+$pcad_pcb .= "    (testPointSizePrint 100.0)\r\n";
+$pcad_pcb .= "    (solderFlowDirection solderFlowTopToBottom)\r\n";
+$pcad_pcb .= "    (globalCopperPourCutoutBackoffFlag False)\r\n";
+$pcad_pcb .= "  )\r\n";
+
+file_put_contents($out_file, $pcad_pcb, FILE_APPEND | LOCK_EX);

pcb/php-builder/pcb_layerdef.php

@@ -0,0 +1,79 @@
+<?php
+
+$pcad_pcb  = "";
+
+// top
+$pcad_pcb .= "  (layerDef \"Top\"\r\n";
+$pcad_pcb .= "    (layerNum 1)\r\n";
+$pcad_pcb .= "    (layerType Signal)\r\n";
+$pcad_pcb .= "    (attr \"PadToPadClearance\" \"8mil\" (textStyleRef \"(Default)\") (constraintUnits mil) )\r\n";
+$pcad_pcb .= "    (attr \"PadToLineClearance\" \"8mil\" (textStyleRef \"(Default)\") (constraintUnits mil) )\r\n";
+$pcad_pcb .= "    (attr \"LineToLineClearance\" \"8mil\" (textStyleRef \"(Default)\") (constraintUnits mil) )\r\n";
+$pcad_pcb .= "    (attr \"ViaToPadClearance\" \"8mil\" (textStyleRef \"(Default)\") (constraintUnits mil) )\r\n";
+$pcad_pcb .= "    (attr \"ViaToLineClearance\" \"8mil\" (textStyleRef \"(Default)\") (constraintUnits mil) )\r\n";
+$pcad_pcb .= "    (attr \"ViaToViaClearance\" \"8mil\" (textStyleRef \"(Default)\") (constraintUnits mil) )\r\n";
+$pcad_pcb .= "    (fieldSetRef \"(Default)\")\r\n";
+$pcad_pcb .= "  )\r\n";
+$pcad_pcb .= "  (layerDef \"Top Assy\"\r\n";
+$pcad_pcb .= "    (layerNum 10)\r\n";
+$pcad_pcb .= "    (layerType NonSignal)\r\n";
+$pcad_pcb .= "    (fieldSetRef \"(Default)\")\r\n";
+$pcad_pcb .= "  )\r\n";
+$pcad_pcb .= "  (layerDef \"Top Silk\"\r\n";
+$pcad_pcb .= "    (layerNum 6)\r\n";
+$pcad_pcb .= "    (layerType NonSignal)\r\n";
+$pcad_pcb .= "    (fieldSetRef \"(Default)\")\r\n";
+$pcad_pcb .= "  )\r\n";
+$pcad_pcb .= "  (layerDef \"Top Mask\"\r\n";
+$pcad_pcb .= "    (layerNum 4)\r\n";
+$pcad_pcb .= "    (layerType NonSignal)\r\n";
+$pcad_pcb .= "    (fieldSetRef \"(Default)\")\r\n";
+$pcad_pcb .= "  )\r\n";
+$pcad_pcb .= "  (layerDef \"Top Paste\"\r\n";
+$pcad_pcb .= "    (layerNum 8)\r\n";
+$pcad_pcb .= "    (layerType NonSignal)\r\n";
+$pcad_pcb .= "    (fieldSetRef \"(Default)\")\r\n";
+$pcad_pcb .= "  )\r\n";
+
+// bottom
+$pcad_pcb .= "  (layerDef \"Bottom\"\r\n";
+$pcad_pcb .= "    (layerNum 2)\r\n";
+$pcad_pcb .= "    (layerType Signal)\r\n";
+$pcad_pcb .= "    (attr \"PadToPadClearance\" \"8mil\" (textStyleRef \"(Default)\") (constraintUnits mil) )\r\n";
+$pcad_pcb .= "    (attr \"PadToLineClearance\" \"8mil\" (textStyleRef \"(Default)\") (constraintUnits mil) )\r\n";
+$pcad_pcb .= "    (attr \"LineToLineClearance\" \"8mil\" (textStyleRef \"(Default)\") (constraintUnits mil) )\r\n";
+$pcad_pcb .= "    (attr \"ViaToPadClearance\" \"8mil\" (textStyleRef \"(Default)\") (constraintUnits mil) )\r\n";
+$pcad_pcb .= "    (attr \"ViaToLineClearance\" \"8mil\" (textStyleRef \"(Default)\") (constraintUnits mil) )\r\n";
+$pcad_pcb .= "    (attr \"ViaToViaClearance\" \"8mil\" (textStyleRef \"(Default)\") (constraintUnits mil) )\r\n";
+$pcad_pcb .= "    (fieldSetRef \"(Default)\")\r\n";
+$pcad_pcb .= "  )\r\n";
+$pcad_pcb .= "  (layerDef \"Bot Assy\"\r\n";
+$pcad_pcb .= "    (layerNum 11)\r\n";
+$pcad_pcb .= "    (layerType NonSignal)\r\n";
+$pcad_pcb .= "    (fieldSetRef \"(Default)\")\r\n";
+$pcad_pcb .= "  )\r\n";
+$pcad_pcb .= "  (layerDef \"Bot Silk\"\r\n";
+$pcad_pcb .= "    (layerNum 7)\r\n";
+$pcad_pcb .= "    (layerType NonSignal)\r\n";
+$pcad_pcb .= "    (fieldSetRef \"(Default)\")\r\n";
+$pcad_pcb .= "  )\r\n";
+$pcad_pcb .= "  (layerDef \"Bot Mask\"\r\n";
+$pcad_pcb .= "    (layerNum 5)\r\n";
+$pcad_pcb .= "    (layerType NonSignal)\r\n";
+$pcad_pcb .= "    (fieldSetRef \"(Default)\")\r\n";
+$pcad_pcb .= "  )\r\n";
+$pcad_pcb .= "  (layerDef \"Bot Paste\"\r\n";
+$pcad_pcb .= "    (layerNum 9)\r\n";
+$pcad_pcb .= "    (layerType NonSignal)\r\n";
+$pcad_pcb .= "    (fieldSetRef \"(Default)\")\r\n";
+$pcad_pcb .= "  )\r\n";
+
+// board
+$pcad_pcb .= "  (layerDef \"Board\"\r\n";
+$pcad_pcb .= "    (layerNum 3)\r\n";
+$pcad_pcb .= "    (layerType NonSignal)\r\n";
+$pcad_pcb .= "    (fieldSetRef \"(Default)\")\r\n";
+$pcad_pcb .= "  )\r\n";
+
+file_put_contents($out_file, $pcad_pcb, FILE_APPEND | LOCK_EX);
+

pcb/php-builder/pcb_layers.php

@@ -0,0 +1,161 @@
+<?php
+
+// generate lines
+// ================================================================================================
+for ($i=0; $i<20; $i++)
+  $LAYER[$i] = array();
+
+for($i=1; $i<$pcb->HDR['net_points_count']['v']; $i++)
+{
+	$flags1 = hex($pcb->NETPOI[$i]['flags']['v']);
+	$flags1_layer = substr($flags1, 0, 1); // 0-bot, 1-top
+	$flags1_head = substr($flags1, 1, 1); // 0-start line, 1-continue, 6,7 via
+	$net1 = $pcb->NETPOI[$i]['net_id']['v'];
+	$x1 = $pcb->NETPOI[$i]['pos_x']['v'];
+	$y1 = $pcb->NETPOI[$i]['pos_y']['v'];
+	$size = $pcb->NETPOI[$i]['size']['v'];
+
+
+	$flags2 = hex($pcb->NETPOI[($i+1)]['flags']['v']);
+	$flags2_layer = substr($flags2, 0, 1); // 0-bot, 1-top
+	$flags2_head = substr($flags2, 1, 1); // 0-start line, 1-continue, 6,7 via
+	$net2 = $pcb->NETPOI[($i+1)]['net_id']['v'];
+	$x2 = $pcb->NETPOI[($i+1)]['pos_x']['v'];
+	$y2 = $pcb->NETPOI[($i+1)]['pos_y']['v'];
+
+	if ($net1 != $net2) continue; // next point is from other net
+	if ($flags2_head == 0) continue; // next point is start
+	if ($flags2_head == 8) continue; // next point is start
+	if ($flags2_layer != $flags1_layer) continue; // next point at another layer, via is here
+	if (($flags1_layer == $flags2_layer) and ($flags2_head == 6)) continue;
+
+
+
+//if ($net1 != 16521) continue; // ISA RES
+//if ($net1 != 78) continue; // GND
+//if ($net1 != 90) continue; // VCC
+//if ($net1 != 66) continue; // VCC
+
+
+
+	$line['id1'] = $i;
+	$line['x1'] = $x1;
+	$line['y1'] = $y1;
+	$line['id2'] = $i+1;
+	$line['x2'] = $x2;
+	$line['y2'] = $y2;
+	$line['net'] = getNetByPadOfs($pcb, $net1);
+	$line['size'] = $size;
+
+	$LAYER[$flags1_layer][] = $line;
+}
+
+for($i=1; $i<$pcb->HDR['brd_points_count']['v']; $i++)
+{
+	$flags1 = hex($pcb->BRDPOI[$i]['flags']['v']);
+	$flags1_head = substr($flags1, 1, 1); // 0-start line, 1-continue, 6,7 via
+	$x1 = $pcb->BRDPOI[$i]['pos_x']['v'];
+	$y1 = $pcb->BRDPOI[$i]['pos_y']['v'];
+
+	$flags2 = hex($pcb->BRDPOI[($i+1)]['flags']['v']);
+	$flags2_head = substr($flags2, 1, 1); // 0-start line, 1-continue, 6,7 via
+	$x2 = $pcb->BRDPOI[($i+1)]['pos_x']['v'];
+	$y2 = $pcb->BRDPOI[($i+1)]['pos_y']['v'];
+
+	if ($flags2_head == 0) continue; // next point is start
+
+	$line['x1'] = $x1;
+	$line['y1'] = $y1;
+	$line['x2'] = $x2;
+	$line['y2'] = $y2;
+	$line['size'] = "8";
+
+	$LAYER[3][] = $line;
+}
+
+function createLayerContent($pcb, $LAYER, $orcad_layer)
+{
+	$pcad_pcb = "";
+	for($i=1; $i<sizeof($LAYER[$orcad_layer]); $i++) // 1 - orcad top
+	{      
+		$line = $LAYER[$orcad_layer][$i];
+		$x1 = $line['x1'];
+		$y1 = $line['y1'];
+		$x2 = $line['x2'];
+		$y2 = $line['y2'];
+		$size = $line['size'];
+
+		$net = $line['net'];
+		$netref = "";
+		if ($net) 
+			$netref="(netNameRef \"$net\") ";
+
+		$pcad_pcb .= "    (line (pt $y1 $x1) (pt $y2 $x2) (width $size) $netref)";  
+//		$pcad_pcb .= " ;; [".$line['id1']."]-[".$line['id2']."]";
+		$pcad_pcb .= "\r\n";
+	}
+
+	for($i=1; $i<=$pcb->HDR['texts_count']['v']; $i++)
+	{
+		$T = $pcb->TXT[$i];
+		if ($T['layer']['v'] != $orcad_layer) continue; // 0-bot, 1-top
+
+		$style = "(DefaultTTF)";
+		$style = $T['style']['v'];
+		$x = $T['pos_x']['v'];
+		$y = $T['pos_y']['v'];
+		$s = $T['str']['v'];
+		$r = ($T['rotate']['v']);
+//		$r = $r - 1; // rotate -90
+		if ($r<0) $r = 4 + $r;
+		if ($orcad_layer == 1) // HACK FOR TOP LAYER ONLY !!!
+		{
+			if ($r==3) $r = 1; 
+		}
+		$r = $r * 90;
+
+		$flip = "";
+		$flags = hex($T['flags']['v']);
+		$mirrored = substr($flags, 0, 1); // 1 - not mirrored, 0 - mirrored (why ???)
+		$visible = substr($flags, 1, 1); // 1 - visible, 0 - not visible
+		if ($mirrored == "0") $flip = "(isFlipped True) ";
+		$pcad_pcb .= "    (text (pt $y $x) \"$s\" (textStyleRef \"$style\") (rotation $r) $flip(justify Center) $ext)\r\n";
+	}
+
+	return $pcad_pcb;
+}
+
+
+// layer1, pcad top
+// ================================================================================================
+$pcad_pcb  = "  (layerContents (layerNumRef 1)\r\n";
+$pcad_pcb .= createLayerContent($pcb, $LAYER, 1);
+$pcad_pcb .= "  )\r\n";
+file_put_contents($out_file, $pcad_pcb, FILE_APPEND | LOCK_EX);
+
+// layer2, pcad bottom
+// ================================================================================================
+$pcad_pcb  = "  (layerContents (layerNumRef 2)\r\n";
+$pcad_pcb .= createLayerContent($pcb, $LAYER, 0);
+$pcad_pcb .= "  )\r\n";
+file_put_contents($out_file, $pcad_pcb, FILE_APPEND | LOCK_EX);
+
+// board
+// ================================================================================================
+$pcad_pcb  = "  (layerContents (layerNumRef 3)\r\n";
+// - lines
+for($i=1; $i<sizeof($LAYER[3]); $i++)
+{
+	$line = $LAYER[3][$i];
+	$x1 = $line['x1'];
+	$y1 = $line['y1'];
+	$x2 = $line['x2'];
+	$y2 = $line['y2'];
+	$net = $line['net'];
+	$size = $line['size'];
+
+	$pcad_pcb .= "    (line (pt $y1 $x1) (pt $y2 $x2) (width $size) )\r\n";
+}
+$pcad_pcb .= "  )\r\n";
+file_put_contents($out_file, $pcad_pcb, FILE_APPEND | LOCK_EX);
+

pcb/php-builder/pcb_multilayer.php

@@ -0,0 +1,64 @@
+<?php
+
+// multilayer begin
+$pcad_pcb  = "  (multiLayer\r\n";
+
+// - via
+for($i=0; $i<=$pcb->HDR['net_points_count']['v']; $i++)
+{
+	$net1 = $pcb->NETPOI[$i]['net_id']['v'];
+	$net = getNetByPadOfs($pcb, $net1);
+	$netref = "";
+	if ($net) $netref = "(netNameRef \"$net\") ";
+
+	$flags = hex($pcb->NETPOI[$i]['flags']['v']);
+	$flags_hdr = substr($flags, 1, 1);
+
+	if ( ($flags_hdr == "6") or ($flags_hdr == "7") ) {} else continue;
+
+	$st = $pcb->NETPOI[$i]['style']['v'];
+	$x = $pcb->NETPOI[$i]['pos_x']['v'];
+	$y = $pcb->NETPOI[$i]['pos_y']['v'];
+
+	$pcad_pcb .= "    (via (viaStyleRef \"$st\") (pt $y $x) $netref)\r\n";
+}
+//file_put_contents($out_file, $pcad_pcb, FILE_APPEND | LOCK_EX);
+
+// - components
+for($i=1; $i<=$pcb->HDR['comp_count_real']['v']; $i++)
+{
+	$C = $pcb->COMP[$i];
+
+	$name1 = ValidateRef($C['name1_str']['v']);
+	$name2 = ValidateRef($C['name2_str']['v']);
+	$pattern = $C['style']['v'] . "_1";
+	$x = $C['pos_x']['v'];
+	$y = $C['pos_y']['v'];
+
+	$delta = $C['rotate']['v'] - $C['style_rotate']['v'];
+	$r = (2 - $delta);
+
+	$comment = "";
+//	$comment = ";; styleR=[".$C['style_rotate']['v']."], compR=".$C['rotate']['v'].", calcR=$r";
+
+	$pcad_pcb .= "    (pattern (patternRef \"$pattern\") (refDesRef \"$name1\") (pt $y $x) (rotation ".($r*90).") (patternGraphicsNameRef \"Primary\")\r\n";
+	$pcad_pcb .= "      (patternGraphicsRef $comment\r\n";
+	$pcad_pcb .= "        (patternGraphicsNameRef \"Primary\")\r\n";
+
+	$tr = ($C['rotate']['v'] +3) %4;
+	if (($tr == 1) or ($tr == 3)) $tr = ($tr +2) %4;
+
+// can be experimenting
+if ($C['pads_count']['v'] > 12)
+	$pcad_pcb .= "        (attr \"RefDes\" \"$name1\" (rotation ".($tr*90).") (isVisible True) (justify Center) (textStyleRef \"(DefaultTTF)\") )\r\n";
+
+	$pcad_pcb .= "      )\r\n";
+	$pcad_pcb .= "    )\r\n";
+
+//file_put_contents($out_file, $pcad_pcb, FILE_APPEND | LOCK_EX);
+}
+
+// multilayer end.
+$pcad_pcb .= "  )\r\n";
+file_put_contents($out_file, $pcad_pcb, FILE_APPEND | LOCK_EX);
+

pcb/php-builder/pcb_stackup.php

@@ -0,0 +1,35 @@
+<?php
+
+$pcad_pcb  = "";
+
+// sets
+$pcad_pcb .= "  (layerSets \r\n";
+$pcad_pcb .= "    (layerSet \"All Layers\" \"1\" \"1\" \"2\" \"3\" \"4\" \"5\" \"6\" \"7\" \"8\" \"9\" \"10\" \"11\")\r\n";
+$pcad_pcb .= "    (layerSet \"Signal Layers\" \"1\" \"1\" \"2\")\r\n";
+$pcad_pcb .= "    (layerSet \"Plane Layers\" \"-1\")\r\n";
+$pcad_pcb .= "    (layerSet \"Nonsignal Layers\" \"6\" \"6\" \"3\" \"4\" \"5\" \"7\" \"8\" \"9\" \"10\" \"11\")\r\n";
+$pcad_pcb .= "    (layerSet \"TOP\" \"1\" \"1\" \"6\" \"3\")\r\n";
+$pcad_pcb .= "    (layerSet \"BOT\" \"2\" \"2\" \"3\" \"7\")\r\n";
+$pcad_pcb .= "  )\r\n";
+
+// stackup
+$pcad_pcb .= "  (layersStackup \r\n";
+$pcad_pcb .= "    (layerStackupData \r\n";
+$pcad_pcb .= "      (layerStackupName \"Top\")\r\n";
+$pcad_pcb .= "      (layerStackupMaterial \"\")\r\n";
+$pcad_pcb .= "      (layerStackupThickness \"\")\r\n";
+$pcad_pcb .= "      (layerStackupDielectricConstant \"\")\r\n";
+$pcad_pcb .= "      (layerStackupDisplay True)\r\n";
+$pcad_pcb .= "    )\r\n";
+$pcad_pcb .= "    (layerStackupData \r\n";
+$pcad_pcb .= "      (layerStackupName \"Bottom\")\r\n";
+$pcad_pcb .= "      (layerStackupMaterial \"\")\r\n";
+$pcad_pcb .= "      (layerStackupThickness \"\")\r\n";
+$pcad_pcb .= "      (layerStackupDielectricConstant \"\")\r\n";
+$pcad_pcb .= "      (layerStackupDisplay True)\r\n";
+$pcad_pcb .= "    )\r\n";
+$pcad_pcb .= "  )\r\n";
+
+file_put_contents($out_file, $pcad_pcb, FILE_APPEND | LOCK_EX);
+
+

pcb/php-parser/Class_OrCad21.php

@@ -0,0 +1,486 @@
+<?
+class orcad21
+{
+	const HDR_SIZE = 48;
+
+	public $Error;
+	public $LastErrorStr;
+
+	public $ParseIndex;
+
+	public $FileName;
+	public $FileSize;
+	public $BUF = array();
+	public $HDR = array();
+	public $COMP = array();
+	public $TXT = array();
+	public $BRDPOI = array();
+	public $NETPOI = array();
+
+	public $VIA_STYLE = array();
+	public $PAD_STYLE = array();
+	public $TXT_STYLE = array();
+
+	public $PATTERN_STYLE = array();
+
+
+	public $MinPosX;                                   
+	public $MinPosY;                                   
+	public $MaxPosX;                                   
+	public $MaxPosY;                                   
+
+	// constructor
+	function __construct($fn = "")
+	{
+		$this->FileName = $fn;
+		$this->Load($this->FileName);
+
+		$this->MinPosX = 1000000;
+		$this->MinPosY = 1000000;
+		$this->MaxPosX = 0;
+		$this->MaxPosY = 0;
+	}
+
+	// private
+	private function hex($int) 
+	{
+		$h = dechex($int);
+		if (strlen($h)%2 != 0) 
+		{
+			$h = str_pad($h, strlen($h) + 1, '0', STR_PAD_LEFT);
+		}
+		return strtoupper($h)."h";
+	}
+
+	private function GetStr($strl, $descr = "")
+	{
+		$result['ofs'] = $this->ParseIndex;
+		for ($i=0; $i<$strl; $i++)
+		{
+			if ($i > 0) $result['buf'] .= " ";
+			$result['buf'] .= $this->hex(ord($this->BUF[$this->ParseIndex + $i]));
+			if ((ord($this->BUF[$this->ParseIndex + $i]) > 31) and (ord($this->BUF[$this->ParseIndex + $i]) < 128)) 
+			{
+				$result['v'] .= $this->BUF[$this->ParseIndex + $i];
+			}
+		}
+		$result['descr'] = $descr;
+		$this->ParseIndex += $strl;
+		return $result;
+	}
+
+	private function GetByte($descr = "")
+	{
+		$result['ofs'] = $this->ParseIndex;
+		$result['buf'] = $this->hex(ord($this->BUF[$this->ParseIndex]));
+		$result['v'] = ord($this->BUF[$this->ParseIndex]);
+		$result['descr'] = $descr;
+		$this->ParseIndex++;
+		return $result;
+	}
+
+	private function GetWord($descr = "")
+	{
+		$result['ofs'] = $this->ParseIndex;
+		$result['buf'] = $this->hex(ord($this->BUF[$this->ParseIndex])) . " " . $this->hex(ord($this->BUF[$this->ParseIndex + 1]));
+		$result['v'] = ord($this->BUF[$this->ParseIndex]) + 256 * ord($this->BUF[$this->ParseIndex + 1]);
+		$result['descr'] = $descr;
+		$this->ParseIndex += 2;
+		return $result;
+	}
+
+	private function ParseHeader()
+	{
+		$this->Error = 0;
+		$this->LastErrorStr = "";
+
+		$this->ParseIndex = 0;
+		$this->HDR['file_name'] = $this->GetStr(8);
+		$this->HDR['file_name']['v'] = trim($this->HDR['file_name']['v']);
+		$this->HDR['unk1'] = $this->GetWord();
+		$this->HDR['comp_count'] = $this->GetWord();
+		$this->HDR['unk3'] = $this->GetWord();
+		$this->HDR['unk4'] = $this->GetWord();
+		$this->HDR['unk5'] = $this->GetWord();
+		$this->HDR['unk6'] = $this->GetWord();
+		$this->HDR['unk7'] = $this->GetWord();
+		$this->HDR['unk8'] = $this->GetWord();
+		$this->HDR['unk9'] = $this->GetWord();
+		$this->HDR['unk10'] = $this->GetWord();
+		$this->HDR['unk11'] = $this->GetWord();
+		$this->HDR['texts_ofs'] = $this->GetWord();
+		$this->HDR['texts_ofs_real']['v'] = $this->HDR['texts_ofs']['v'] * 2 + self::HDR_SIZE;
+		$this->HDR['texts_size'] = $this->GetWord();
+		$this->HDR['brd_points_count'] = $this->GetWord();
+		$this->HDR['net_points_count'] = $this->GetWord();
+		$this->HDR['unk16'] = $this->GetWord();
+		$this->HDR['unk17'] = $this->GetWord();
+		$this->HDR['unk18'] = $this->GetWord();
+		$this->HDR['file_ext'] = $this->GetStr(4);
+		$this->HDR['file_ext']['v'] = trim($this->HDR['file_ext']['v']);
+
+		// check range
+		if ($this->ParseIndex > $this->FileSize)
+		{
+			$this->Error = 1;
+			$this->LastErrorStr = "ParseIndex is out of FileSize during ParseHeader()";
+			return false;
+		}
+
+		return true;
+	}
+
+	private function ParseComponent($i)
+	{
+		$this->COMP[$i]['ofs'] = $this->ParseIndex;
+
+		$this->COMP[$i]['timestamp'] = $this->GetStr(8);
+		$this->COMP[$i]['unk1'] = $this->GetByte();
+		$this->COMP[$i]['rotate'] = $this->GetByte("0-0, 1-90, 2-180, 3-270");
+		$this->COMP[$i]['layer'] = $this->GetByte("0-bot, 1-top");
+		$this->COMP[$i]['unk3'] = $this->GetByte();
+		$this->COMP[$i]['unk4'] = $this->GetWord();
+		$this->COMP[$i]['unk5'] = $this->GetWord();
+		$this->COMP[$i]['unk6'] = $this->GetWord();
+		$this->COMP[$i]['unk7'] = $this->GetWord();
+		$this->COMP[$i]['pos_y'] = $this->GetWord();
+		$this->COMP[$i]['pos_x'] = $this->GetWord();
+		$this->COMP[$i]['unk10'] = $this->GetWord();
+		$this->COMP[$i]['unk11'] = $this->GetWord();
+		$this->COMP[$i]['lines_ofs'] = $this->GetWord();
+		$this->COMP[$i]['names_ofs'] = $this->GetWord();
+		$this->COMP[$i]['pads_ofs'] = $this->GetWord();
+		$this->COMP[$i]['next_ofs1'] = $this->GetWord();
+		$this->COMP[$i]['next_ofs2'] = $this->GetWord();
+		$this->COMP[$i]['pattern'] = $this->GetStr(8);
+		$this->COMP[$i]['pattern']['v'] = trim($this->COMP[$i]['pattern']['v']);
+		$this->COMP[$i]['next_ofs3'] = $this->GetWord();
+
+		$this->COMP[$i]['lines_count']['v'] = ($this->COMP[$i]['names_ofs']['v'] - $this->COMP[$i]['lines_ofs']['v']) / 6;
+		$this->COMP[$i]['names_count']['v'] = ($this->COMP[$i]['pads_ofs']['v'] - $this->COMP[$i]['names_ofs']['v']) / 24;
+		$this->COMP[$i]['pads_count']['v'] = ($this->COMP[$i]['next_ofs1']['v'] - $this->COMP[$i]['pads_ofs']['v']) / 24;
+
+		// lines
+		for($j=1; $j<=$this->COMP[$i]['lines_count']['v']; $j++)
+		{
+			$this->COMP[$i]['line'.$j.'_flags'] = $this->GetWord();
+			$this->COMP[$i]['line'.$j.'_pos_y'] = $this->GetWord();
+			$this->COMP[$i]['line'.$j.'_pos_x'] = $this->GetWord();
+		}
+
+		// names
+		for($j=1; $j<=$this->COMP[$i]['names_count']['v']; $j++)
+		{
+			$this->COMP[$i]['name'.$j.'_unk1'] = $this->GetWord();
+			$this->COMP[$i]['name'.$j.'_unk2'] = $this->GetWord();
+			$this->COMP[$i]['name'.$j.'_str'] = $this->GetStr(8);
+			$this->COMP[$i]['name'.$j.'_str']['v'] = trim($this->COMP[$i]['name'.$j.'_str']['v']);
+			$this->COMP[$i]['name'.$j.'_unk4'] = $this->GetWord();
+			$this->COMP[$i]['name'.$j.'_unk5'] = $this->GetWord();
+			$this->COMP[$i]['name'.$j.'_unk6'] = $this->GetWord();
+			$this->COMP[$i]['name'.$j.'_unk7'] = $this->GetWord();
+			$this->COMP[$i]['name'.$j.'_pos_y'] = $this->GetWord();
+			$this->COMP[$i]['name'.$j.'_pos_x'] = $this->GetWord();
+		}
+
+		// pads
+		for($j=1; $j<=$this->COMP[$i]['pads_count']['v']; $j++)
+		{
+			$this->COMP[$i]['pad'.$j.'_ofs_real']['v'] = $this->ParseIndex;
+			$this->COMP[$i]['pad'.$j.'_ofs']['v'] = round($this->ParseIndex / 2) - 24;
+			$this->COMP[$i]['pad'.$j.'_des'] = $this->GetStr(4);
+			$this->COMP[$i]['pad'.$j.'_des']['v'] = trim($this->COMP[$i]['pad'.$j.'_des']['v']);
+			$this->COMP[$i]['pad'.$j.'_net'] = $this->GetStr(8);
+			$this->COMP[$i]['pad'.$j.'_net']['v'] = trim($this->COMP[$i]['pad'.$j.'_net']['v']);
+			$this->COMP[$i]['pad'.$j.'_shape'] = $this->GetByte("1-circ, 2-rect");
+			$this->COMP[$i]['pad'.$j.'_width'] = $this->GetWord();
+			$this->COMP[$i]['pad'.$j.'_height'] = $this->GetWord();
+			$this->COMP[$i]['pad'.$j.'_rotate'] = $this->GetByte("0-0, 1-90, 2-180, 3-270");
+			$this->COMP[$i]['pad'.$j.'_flags'] = $this->GetByte("1-smd, 3-plated");
+			$this->COMP[$i]['pad'.$j.'_hole_dia'] = $this->GetByte();
+			$this->COMP[$i]['pad'.$j.'_pos_y'] = $this->GetWord();
+			$this->COMP[$i]['pad'.$j.'_pos_x'] = $this->GetWord();
+		}
+	}
+
+	private function ParseComponents()
+	{
+		$this->Error = 0;
+		$this->LastErrorStr = "";
+
+		// 'comp_count' = 'comp_count_real' + 1, 
+		// so needs check 'ParseIndex' does not over 'texts_ofs_real'
+		for($i=1; $i<=$this->HDR['comp_count']['v']; $i++)
+		{
+			$this->ParseComponent($i);
+
+			// check components size
+			if($this->ParseIndex >= $this->HDR['texts_ofs_real']['v'])
+			{
+				$this->HDR['comp_count_real']['v'] = $i;
+				return true;
+			}
+
+			// check range
+			if ($this->ParseIndex > $this->FileSize)
+			{
+				$this->Error = 1;
+				$this->LastErrorStr = "ParseIndex is out of FileSize during ParseComponents(), i=" . $i;
+				return false;
+			}
+		}
+
+		return false;
+	}
+
+	private function ParseTexts()
+	{
+		$this->Error = 0;
+		$this->LastErrorStr = "";
+
+		$i = 1;
+		while (1)
+		{                                                                                    
+			$this->TXT[$i]['ofs'] = $this->ParseIndex;
+
+			$this->TXT[$i]['unk1'] = $this->GetWord();
+			$this->TXT[$i]['unk2'] = $this->GetWord();
+			$this->TXT[$i]['unk3'] = $this->GetWord();
+			$this->TXT[$i]['unk4'] = $this->GetWord();
+			$this->TXT[$i]['unk5'] = $this->GetWord();
+			$this->TXT[$i]['unk6'] = $this->GetWord();
+			$this->TXT[$i]['len'] = $this->GetByte();
+			$this->TXT[$i]['size_h'] = $this->GetWord();
+			$this->TXT[$i]['size_v'] = $this->GetWord();
+			$this->TXT[$i]['rotate'] = $this->GetByte("0-0, 1-90, 2-180, 3-270");
+			$this->TXT[$i]['layer'] = $this->GetByte("0-bot, 1-top");
+			$this->TXT[$i]['flags'] = $this->GetByte("(HL), H-mirrored(0-yes)");
+			$this->TXT[$i]['pos_y'] = $this->GetWord();
+			$this->TXT[$i]['pos_x'] = $this->GetWord();
+			$this->TXT[$i]['str'] = $this->GetStr($this->TXT[$i]['len']['v']);
+
+			// check texts size
+			if ($this->ParseIndex >= ($this->HDR['texts_ofs_real']['v'] + $this->HDR['texts_size']['v']))
+				break;
+
+			// check range
+			if ($this->ParseIndex > $this->FileSize)
+			{
+				$this->Error = 1;
+				$this->LastErrorStr = "ParseIndex is out of FileSize during ParseTexts(), i=" . $i;
+				return false;
+			}
+
+			$i++;
+		}
+
+		$this->HDR['texts_count']['v'] = $i;
+		return true;
+	}
+
+	private function ParseBoardPoints()
+	{
+		$this->Error = 0;
+		$this->LastErrorStr = "";
+
+		for($i=1; $i<=$this->HDR['brd_points_count']['v']; $i++)
+		{
+
+			$this->BRDPOI[$i]['ofs'] = $this->ParseIndex;
+
+			$this->BRDPOI[$i]['flags'] = $this->GetByte();
+			$this->BRDPOI[$i]['unk2'] = $this->GetByte();
+			$this->BRDPOI[$i]['pos_y'] = $this->GetWord();
+			$this->BRDPOI[$i]['pos_x'] = $this->GetWord();
+			$this->BRDPOI[$i]['unk5'] = $this->GetByte();
+			$this->BRDPOI[$i]['unk6'] = $this->GetByte();
+
+			if ($this->BRDPOI[$i]['pos_x']['v'] < $this->MinPosX) $this->MinPosX = $this->BRDPOI[$i]['pos_x']['v'];
+			if ($this->BRDPOI[$i]['pos_y']['v'] < $this->MinPosY) $this->MinPosY = $this->BRDPOI[$i]['pos_y']['v'];
+
+			if ($this->BRDPOI[$i]['pos_x']['v'] > $this->MaxPosX) $this->MaxPosX = $this->BRDPOI[$i]['pos_x']['v'];
+			if ($this->BRDPOI[$i]['pos_y']['v'] > $this->MaxPosY) $this->MaxPosY = $this->BRDPOI[$i]['pos_y']['v'];
+
+			// check range
+			if ($this->ParseIndex > $this->FileSize)
+			{
+				$this->Error = 1;
+				$this->LastErrorStr = "ParseIndex is out of FileSize during ParseBoardPoints(), i=" . $i;
+				return false;
+			}
+		}
+
+		return true;
+	}
+
+	private function ParseNetPoints()
+	{
+		$this->Error = 0;
+		$this->LastErrorStr = "";
+
+		for($i=1; $i<=$this->HDR['net_points_count']['v']; $i++)
+		{
+
+			$this->NETPOI[$i]['ofs'] = $this->ParseIndex;
+
+			$this->NETPOI[$i]['flags'] = $this->GetByte("(1x)h-layer, (x1)h-head");
+			$this->NETPOI[$i]['size'] = $this->GetByte();
+			$this->NETPOI[$i]['pos_y'] = $this->GetWord();
+			$this->NETPOI[$i]['pos_x'] = $this->GetWord();
+			$this->NETPOI[$i]['net_id'] = $this->GetWord();
+
+			// check range
+			if ($this->ParseIndex > $this->FileSize)
+			{
+				$this->Error = 1;
+				$this->LastErrorStr = "ParseIndex is out of FileSize during ParseNetPoints(), i=" . $i;
+				return false;
+			}
+		}
+
+		return true;
+	}
+
+	// public
+	public function Load()
+	{
+		$this->ParseIndex = 0;
+		$this->BUF = file_get_contents($this->FileName);
+		$this->FileSize = filesize($this->FileName);
+		if (!$this->FileSize)
+		{
+			$this->FileSize = 0;
+		}
+	}
+
+	public function Parse()
+	{
+		$this->ParseHeader();
+		$this->ParseComponents();
+		$this->ParseTexts();
+		$this->ParseBoardPoints();
+		$this->ParseNetPoints();
+
+		if ($this->FileSize == $this->ParseIndex)
+			return true;
+
+		return false;
+	}
+
+	public function ChangePos($dx, $dy, $reverse_x, $reverse_y, $swap = 0)
+	{
+		// component
+		for($i=1; $i<=sizeof($this->COMP); $i++)
+		{
+			if (!$this->COMP[$i]['ofs']) continue;
+
+			$this->COMP[$i]['pos_x']['v'] += $dx;
+			$this->COMP[$i]['pos_y']['v'] += $dy;
+			if ($reverse_x) $this->COMP[$i]['pos_x']['v'] = $reverse_x - $this->COMP[$i]['pos_x']['v'];
+			if ($reverse_y) $this->COMP[$i]['pos_y']['v'] = $reverse_y - $this->COMP[$i]['pos_y']['v'];
+			if ($swap)
+			{
+				$tmp = $this->COMP[$i]['pos_x']['v'];
+				$this->COMP[$i]['pos_x']['v'] = $this->COMP[$i]['pos_y']['v'];
+				$this->COMP[$i]['pos_y']['v'] = $tmp;
+			}
+
+			// lines
+			for($j=1; $j<=$this->COMP[$i]['lines_count']['v']; $j++)
+			{
+				$this->COMP[$i]['line'.$j.'_pos_y']['v'] += $dy;
+				$this->COMP[$i]['line'.$j.'_pos_x']['v'] += $dx;
+				if ($reverse_x) $this->COMP[$i]['line'.$j.'_pos_x']['v'] = $reverse_x - $this->COMP[$i]['line'.$j.'_pos_x']['v'];
+				if ($reverse_y) $this->COMP[$i]['line'.$j.'_pos_y']['v'] = $reverse_y - $this->COMP[$i]['line'.$j.'_pos_y']['v'];
+				if ($swap)
+				{
+					$tmp = $this->COMP[$i]['line'.$j.'_pos_x']['v'];
+					$this->COMP[$i]['line'.$j.'_pos_x']['v'] = $this->COMP[$i]['line'.$j.'_pos_y']['v'];
+					$this->COMP[$i]['line'.$j.'_pos_y']['v'] = $tmp;
+				}
+			}
+
+			// names
+			for($j=1; $j<=$this->COMP[$i]['names_count']['v']; $j++)
+			{
+				$this->COMP[$i]['name'.$j.'_pos_y']['v'] += $dy;
+				$this->COMP[$i]['name'.$j.'_pos_x']['v'] += $dx;
+				if ($reverse_x) $this->COMP[$i]['name'.$j.'_pos_x']['v'] = $reverse_x - $this->COMP[$i]['name'.$j.'_pos_x']['v'];
+				if ($reverse_y) $this->COMP[$i]['name'.$j.'_pos_y']['v'] = $reverse_y - $this->COMP[$i]['name'.$j.'_pos_y']['v'];
+				if ($swap)
+				{
+					$tmp = $this->COMP[$i]['name'.$j.'_pos_x']['v'];
+					$this->COMP[$i]['name'.$j.'_pos_x']['v'] = $this->COMP[$i]['name'.$j.'_pos_y']['v'];
+					$this->COMP[$i]['name'.$j.'_pos_y']['v'] = $tmp;
+				}
+			}
+
+			// pads
+			for($j=1; $j<=$this->COMP[$i]['pads_count']['v']; $j++)
+			{
+				$this->COMP[$i]['pad'.$j.'_pos_y']['v'] += $dy;
+				$this->COMP[$i]['pad'.$j.'_pos_x']['v'] += $dx;
+				if ($reverse_x) $this->COMP[$i]['pad'.$j.'_pos_x']['v'] = $reverse_x - $this->COMP[$i]['pad'.$j.'_pos_x']['v'];
+				if ($reverse_y) $this->COMP[$i]['pad'.$j.'_pos_y']['v'] = $reverse_y - $this->COMP[$i]['pad'.$j.'_pos_y']['v'];
+				if ($swap)
+				{
+					$tmp = $this->COMP[$i]['pad'.$j.'_pos_x']['v'];
+					$this->COMP[$i]['pad'.$j.'_pos_x']['v'] = $this->COMP[$i]['pad'.$j.'_pos_y']['v'];
+					$this->COMP[$i]['pad'.$j.'_pos_y']['v'] = $tmp;
+
+					$tmp = $this->COMP[$i]['pad'.$j.'_width']['v'];
+					$this->COMP[$i]['pad'.$j.'_width']['v'] = $this->COMP[$i]['pad'.$j.'_height']['v'];
+					$this->COMP[$i]['pad'.$j.'_height']['v'] = $tmp;
+				}
+			}
+		}
+
+		// text
+		for($i=1; $i<=sizeof($this->TXT); $i++)
+		{
+			$this->TXT[$i]['pos_y']['v'] += $dy;
+			$this->TXT[$i]['pos_x']['v'] += $dx;
+			if ($reverse_x) $this->TXT[$i]['pos_x']['v'] = $reverse_x - $this->TXT[$i]['pos_x']['v'];
+			if ($reverse_y) $this->TXT[$i]['pos_y']['v'] = $reverse_y - $this->TXT[$i]['pos_y']['v'];
+			if ($swap)
+			{
+				$tmp = $this->TXT[$i]['pos_x']['v'];
+				$this->TXT[$i]['pos_x']['v'] = $this->TXT[$i]['pos_y']['v'];
+				$this->TXT[$i]['pos_y']['v'] = $tmp;
+			}
+		}
+
+		// board points
+		for($i=1; $i<=$this->HDR['brd_points_count']['v']; $i++)
+		{
+			$this->BRDPOI[$i]['pos_y']['v'] += $dy;
+			$this->BRDPOI[$i]['pos_x']['v'] += $dx;
+			if ($reverse_x) $this->BRDPOI[$i]['pos_x']['v'] = $reverse_x - $this->BRDPOI[$i]['pos_x']['v'];
+			if ($reverse_y) $this->BRDPOI[$i]['pos_y']['v'] = $reverse_y - $this->BRDPOI[$i]['pos_y']['v'];
+			if ($swap)
+			{
+				$tmp = $this->BRDPOI[$i]['pos_y']['v'];
+				$this->BRDPOI[$i]['pos_y']['v'] = $this->BRDPOI[$i]['pos_x']['v'];
+				$this->BRDPOI[$i]['pos_x']['v'] = $tmp;
+			}
+		}
+
+		// net pointes
+		for($i=1; $i<=$this->HDR['net_points_count']['v']; $i++)
+		{
+			$this->NETPOI[$i]['pos_y']['v'] += $dy;
+			$this->NETPOI[$i]['pos_x']['v'] += $dx;
+			if ($reverse_x) $this->NETPOI[$i]['pos_x']['v'] = $reverse_x - $this->NETPOI[$i]['pos_x']['v'];
+			if ($reverse_y) $this->NETPOI[$i]['pos_y']['v'] = $reverse_y - $this->NETPOI[$i]['pos_y']['v'];
+			if ($swap)
+			{
+				$tmp = $this->NETPOI[$i]['pos_x']['v'];
+				$this->NETPOI[$i]['pos_x']['v'] = $this->NETPOI[$i]['pos_y']['v'];
+				$this->NETPOI[$i]['pos_y']['v'] = $tmp;
+			}
+		}
+
+	}
+
+
+}

pcb/php-parser/parser.php

@@ -0,0 +1,123 @@
+<?php
+
+// helpers
+function hex($int) 
+{
+	$h = dechex($int);
+	if (strlen($h)%2 != 0) 
+	{
+		$h = str_pad($h, strlen($h) + 1, '0', STR_PAD_LEFT);
+	}
+	return strtoupper($h)."h";
+}
+function ValidateRef($ref)
+{
+	$ref = str_replace("-", "_", $ref);
+	$ref = str_replace("*", "", $ref);
+	$ref = str_replace("?", "", $ref);
+	$ref = str_replace(".", "", $ref);
+	$ref = str_replace("+", "", $ref);
+	if (!trim($ref)) $ref = "UNK";
+	return $ref;
+}
+function getNetByPadOfs($pcb, $ofs)
+{
+	for($i=1; $i<=$pcb->HDR['comp_count_real']['v']; $i++)
+	{
+		for ($j=1; $j<=$pcb->COMP[$i]['pads_count']['v']; $j++)
+		{
+			$pad_ofs = $pcb->COMP[$i]['pad'.$j.'_ofs']['v'];
+			if ($pad_ofs == $ofs)
+			{                    
+				return $pcb->COMP[$i]['pad'.$j.'_net']['v'];
+			}
+		}
+	}
+}
+
+// include class
+include("p/" . $proj[$PROJ_ID]['dir'] . "/Class_OrCad21.php");
+
+// parse
+// ------------------------------------------------------------------------------------------------
+$pcb = new orcad21("p/" . $proj[$PROJ_ID]['dir'] . "/sprint05.pcb");
+echo"file size = [".$pcb->FileSize."]<br>";
+
+if (!$pcb->Parse())
+{
+	echo"parser error<br>";
+	return;
+}
+
+// print results
+// ------------------------------------------------------------------------------------------------
+echo"min_x = ".$pcb->MinPosX.", min_y = ".$pcb->MinPosY."<br>";
+echo"max_x = ".$pcb->MaxPosX.", max_y = ".$pcb->MaxPosY."<br>";
+
+// transform all coordinates from "orcad-top-left" to "pcad-bottom-left"
+$pcb->ChangePos(0,0, 0,($pcb->MaxPosY + $pcb->MinPosY), 1);
+
+// check ref duplicated
+$REF = array();
+echo"validate ref...<br>";
+for($i=1; $i<=$pcb->HDR['comp_count_real']['v']; $i++)
+{
+	$ref1 = $pcb->COMP[$i]['name1_str']['v'];
+	$ref2 = ValidateRef($pcb->COMP[$i]['name1_str']['v']);
+	if ($ref1 != $ref2)
+	{
+		echo"name [$ref1] change to [$ref2]<br>";
+		$pcb->COMP[$i]['name1_str']['v'] = $ref2;
+	}
+
+}
+
+echo"check duplicates...<br>";
+$found = 0;
+for($i=1; $i<=$pcb->HDR['comp_count_real']['v']; $i++)
+{
+	$ref = $pcb->COMP[$i]['name1_str']['v'];
+	$REF[$ref] = $REF[$ref] + 1;
+	if ($REF[$ref] > 1)
+		$found = 1;
+}
+if ($found)
+{
+	echo"duplicate found!<br>";
+	foreach ($REF as $ref => $m)
+	{
+		if ($REF[$ref] > 1)
+		{
+			echo"[$ref] = ".$REF[$ref]."<br>";
+			$id = 1;
+			for($i=0; $i<=$pcb->HDR['comp_count_real']['v']; $i++)
+			{
+				$comp_ref = $pcb->COMP[$i]['name1_str']['v'];
+				if ($comp_ref == $ref)
+				{
+					$pcb->COMP[$i]['name1_str']['v'] = $comp_ref . "_DUP".$id;
+					$id++;
+				}
+			}
+		}
+	}
+}
+
+$REF = array();
+echo"check duplicates...<br>";
+$found = 0;
+for($i=1; $i<=$pcb->HDR['comp_count_real']['v']; $i++)
+{
+	$ref = $pcb->COMP[$i]['name1_str']['v'];
+	$REF[$ref] = $REF[$ref] + 1;
+	if ($REF[$ref] > 1)
+		$found = 1;
+}
+if ($found)
+	echo"duplicate found!<br>";
+else
+	echo"no duplicates now<br>";
+
+echo"<br>";
+
+// build ...