mirror of
https://github.com/holub/mame
synced 2025-06-30 16:00:01 +03:00
powervr2: Explode the core/ta registers [O. Galibert]
This commit is contained in:
Olivier Galibert
parent
cdda6a9f58
commit
0073de5340
@ -1535,7 +1535,7 @@ static ADDRESS_MAP_START( naomi_map, AS_PROGRAM, 64, naomi_state )
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AM_RANGE(0x005f7400, 0x005f74ff) AM_MIRROR(0x02000000) AM_DEVICE32( "rom_board", naomi_g1_device, amap, U64(0xffffffffffffffff) )
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AM_RANGE(0x005f7800, 0x005f78ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
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AM_RANGE(0x005f7c00, 0x005f7cff) AM_MIRROR(0x02000000) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w, U64(0xffffffffffffffff))
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AM_RANGE(0x005f8000, 0x005f9fff) AM_MIRROR(0x02000000) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ta_r, pvr_ta_w, U64(0xffffffffffffffff))
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AM_RANGE(0x005f8000, 0x005f9fff) AM_MIRROR(0x02000000) AM_DEVICE32("powervr2", powervr2_device, ta_map, U64(0xffffffffffffffff))
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AM_RANGE(0x00600000, 0x006007ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_modem_r, dc_modem_w )
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AM_RANGE(0x00700000, 0x00707fff) AM_MIRROR(0x02000000) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
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AM_RANGE(0x00710000, 0x0071000f) AM_MIRROR(0x02000000) AM_READWRITE(dc_rtc_r, dc_rtc_w )
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@ -1587,7 +1587,7 @@ static ADDRESS_MAP_START( naomi2_map, AS_PROGRAM, 64, naomi_state )
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AM_RANGE(0x005f7400, 0x005f74ff) AM_MIRROR(0x02000000) AM_DEVICE32( "rom_board", naomi_g1_device, amap, U64(0xffffffffffffffff) )
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AM_RANGE(0x005f7800, 0x005f78ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
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AM_RANGE(0x005f7c00, 0x005f7cff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w, U64(0xffffffffffffffff))
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AM_RANGE(0x005f8000, 0x005f9fff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ta_r, pvr_ta_w, U64(0xffffffffffffffff))
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AM_RANGE(0x005f8000, 0x005f9fff) AM_MIRROR(0x02000000) AM_DEVICE32("powervr2", powervr2_device, ta_map, U64(0xffffffffffffffff))
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AM_RANGE(0x00600000, 0x006007ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_modem_r, dc_modem_w )
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AM_RANGE(0x00700000, 0x00707fff) AM_MIRROR(0x02000000) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
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AM_RANGE(0x00710000, 0x0071000f) AM_MIRROR(0x02000000) AM_READWRITE(dc_rtc_r, dc_rtc_w )
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@ -1599,7 +1599,7 @@ static ADDRESS_MAP_START( naomi2_map, AS_PROGRAM, 64, naomi_state )
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// AM_RANGE(0x025f6800, 0x025f69ff) AM_READWRITE_LEGACY(dc_sysctrl_r, dc_sysctrl_w ) // second PVR DMA!
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// AM_RANGE(0x025f7c00, 0x025f7cff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w, U64(0xffffffffffffffff))
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AM_RANGE(0x025f8000, 0x025f9fff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr2_ta_r, pvr2_ta_w, U64(0xffffffffffffffff))
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AM_RANGE(0x005f8000, 0x005f9fff) AM_MIRROR(0x02000000) AM_DEVICE32("powervr2", powervr2_device, ta_map, U64(0xffffffffffffffff))
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/* Area 1 */
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AM_RANGE(0x04000000, 0x04ffffff) AM_RAM AM_SHARE("dc_texture_ram") // texture memory 64 bit access
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@ -1609,7 +1609,7 @@ static ADDRESS_MAP_START( naomi2_map, AS_PROGRAM, 64, naomi_state )
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/* Area 2*/
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AM_RANGE(0x085f6800, 0x085f69ff) AM_WRITE(dc_sysctrl_w ) // writes to BOTH PVRs
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AM_RANGE(0x085f8000, 0x085f9fff) AM_DEVWRITE32("powervr2", powervr2_device, pvrs_ta_w, U64(0xffffffffffffffff) ) // writes to BOTH PVRs
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AM_RANGE(0x085f8000, 0x805f9fff) AM_DEVICE32("powervr2", powervr2_device, ta_map, U64(0xffffffffffffffff))
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AM_RANGE(0x08800000, 0x088000ff) AM_DEVREADWRITE32("powervr2", powervr2_device, elan_regs_r, elan_regs_w, U64(0xffffffffffffffff)) // T&L chip registers
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// AM_RANGE(0x09000000, 0x09??????) T&L command processing
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AM_RANGE(0x0a000000, 0x0bffffff) AM_RAM AM_SHARE("elan_ram") // T&L chip RAM
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@ -1740,7 +1740,7 @@ static ADDRESS_MAP_START( aw_map, AS_PROGRAM, 64, naomi_state )
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AM_RANGE(0x005f7400, 0x005f74ff) AM_MIRROR(0x02000000) AM_DEVICE32( "rom_board", naomi_g1_device, amap, U64(0xffffffffffffffff) )
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AM_RANGE(0x005f7800, 0x005f78ff) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
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AM_RANGE(0x005f7c00, 0x005f7cff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w, U64(0xffffffffffffffff))
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AM_RANGE(0x005f8000, 0x005f9fff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ta_r, pvr_ta_w, U64(0xffffffffffffffff))
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AM_RANGE(0x005f8000, 0x005f9fff) AM_MIRROR(0x02000000) AM_DEVICE32("powervr2", powervr2_device, ta_map, U64(0xffffffffffffffff))
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AM_RANGE(0x00600000, 0x006007ff) AM_READWRITE(aw_modem_r, aw_modem_w )
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AM_RANGE(0x00700000, 0x00707fff) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
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AM_RANGE(0x00710000, 0x0071000f) AM_READWRITE(dc_rtc_r, dc_rtc_w )
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@ -246,81 +246,6 @@ class dc_state : public driver_device
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#define RTC3 ((0x00710008-0x00710000)/4)
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/*--------------- CORE registers --------------*/
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#define PVRID ((0x005f8000-0x005f8000)/4)
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#define REVISION ((0x005f8004-0x005f8000)/4)
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#define SOFTRESET ((0x005f8008-0x005f8000)/4)
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#define STARTRENDER ((0x005f8014-0x005f8000)/4)
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#define TEST_SELECT ((0x005f8018-0x005f8000)/4)
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#define PARAM_BASE ((0x005f8020-0x005f8000)/4)
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#define REGION_BASE ((0x005f802c-0x005f8000)/4)
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#define SPAN_SORT_CFG ((0x005f8030-0x005f8000)/4)
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#define VO_BORDER_COL ((0x005f8040-0x005f8000)/4)
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#define FB_R_CTRL ((0x005f8044-0x005f8000)/4)
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#define FB_W_CTRL ((0x005f8048-0x005f8000)/4)
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#define FB_W_LINESTRIDE ((0x005f804c-0x005f8000)/4)
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#define FB_R_SOF1 ((0x005f8050-0x005f8000)/4)
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#define FB_R_SOF2 ((0x005f8054-0x005f8000)/4)
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#define FB_R_SIZE ((0x005f805c-0x005f8000)/4)
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#define FB_W_SOF1 ((0x005f8060-0x005f8000)/4)
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#define FB_W_SOF2 ((0x005f8064-0x005f8000)/4)
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#define FB_X_CLIP ((0x005f8068-0x005f8000)/4)
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#define FB_Y_CLIP ((0x005f806c-0x005f8000)/4)
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#define FPU_SHAD_SCALE ((0x005f8074-0x005f8000)/4)
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#define FPU_CULL_VAL ((0x005f8078-0x005f8000)/4)
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#define FPU_PARAM_CFG ((0x005f807c-0x005f8000)/4)
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#define HALF_OFFSET ((0x005f8080-0x005f8000)/4)
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#define FPU_PERP_VAL ((0x005f8084-0x005f8000)/4)
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#define ISP_BACKGND_D ((0x005f8088-0x005f8000)/4)
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#define ISP_BACKGND_T ((0x005f808c-0x005f8000)/4)
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#define ISP_FEED_CFG ((0x005f8098-0x005f8000)/4)
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#define SDRAM_REFRESH ((0x005f80a0-0x005f8000)/4)
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#define SDRAM_ARB_CFG ((0x005f80a4-0x005f8000)/4)
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#define SDRAM_CFG ((0x005f80a8-0x005f8000)/4)
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#define FOG_COL_RAM ((0x005f80b0-0x005f8000)/4)
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#define FOG_COL_VERT ((0x005f80b4-0x005f8000)/4)
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#define FOG_DENSITY ((0x005f80b8-0x005f8000)/4)
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#define FOG_CLAMP_MAX ((0x005f80bc-0x005f8000)/4)
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#define FOG_CLAMP_MIN ((0x005f80c0-0x005f8000)/4)
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#define SPG_TRIGGER_POS ((0x005f80c4-0x005f8000)/4)
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#define SPG_HBLANK_INT ((0x005f80c8-0x005f8000)/4)
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#define SPG_VBLANK_INT ((0x005f80cc-0x005f8000)/4)
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#define SPG_CONTROL ((0x005f80d0-0x005f8000)/4)
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#define SPG_HBLANK ((0x005f80d4-0x005f8000)/4)
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#define SPG_LOAD ((0x005f80d8-0x005f8000)/4)
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#define SPG_VBLANK ((0x005f80dc-0x005f8000)/4)
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#define SPG_WIDTH ((0x005f80e0-0x005f8000)/4)
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#define TEXT_CONTROL ((0x005f80e4-0x005f8000)/4)
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#define VO_CONTROL ((0x005f80e8-0x005f8000)/4)
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#define VO_STARTX ((0x005f80ec-0x005f8000)/4)
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#define VO_STARTY ((0x005f80f0-0x005f8000)/4)
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#define SCALER_CTL ((0x005f80f4-0x005f8000)/4)
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#define PAL_RAM_CTRL ((0x005f8108-0x005f8000)/4)
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#define ISP_BACKGND_T ((0x005f808c-0x005f8000)/4)
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#define SPG_STATUS ((0x005f810c-0x005f8000)/4)
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#define FB_BURSTCTRL ((0x005f8110-0x005f8000)/4)
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#define Y_COEFF ((0x005f8118-0x005f8000)/4)
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#define PT_ALPHA_REF ((0x005f811c-0x005f8000)/4)
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/* 0x005f8200 - 0x005f83ff fog_table */
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/* 0x005f9000 - 0x005f9fff palette_ram */
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/*--------- Tile Accelerator registers ---------*/
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#define TA_OL_BASE ((0x005f8124-0x005f8000)/4)
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#define TA_ISP_BASE ((0x005f8128-0x005f8000)/4)
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#define TA_OL_LIMIT ((0x005f812c-0x005f8000)/4)
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#define TA_ISP_LIMIT ((0x005f8130-0x005f8000)/4)
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#define TA_NEXT_OPB ((0x005f8134-0x005f8000)/4)
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#define TA_ITP_CURRENT ((0x005f8138-0x005f8000)/4)
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#define TA_GLOB_TILE_CLIP ((0x005f813c-0x005f8000)/4)
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#define TA_ALLOC_CTRL ((0x005f8140-0x005f8000)/4)
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#define TA_LIST_INIT ((0x005f8144-0x005f8000)/4)
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#define TA_YUV_TEX_BASE ((0x005f8148-0x005f8000)/4)
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#define TA_YUV_TEX_CTRL ((0x005f814c-0x005f8000)/4)
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#define TA_YUV_TEX_CNT ((0x005f8150-0x005f8000)/4)
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#define TA_LIST_CONT ((0x005f8160-0x005f8000)/4)
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#define TA_NEXT_OPB_INIT ((0x005f8164-0x005f8000)/4)
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/* 0x005f8600 - 0x005f8f5c TA_OL_POINTERS (read only) */
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/* ------------- normal interrupts ------------- */
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#define IST_EOR_VIDEO 0x00000001
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#define IST_EOR_ISP 0x00000002
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File diff suppressed because it is too large
Load Diff
@ -25,6 +25,8 @@ public:
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DMA_PVR_IRQ
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};
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DECLARE_ADDRESS_MAP(ta_map, 32);
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struct {
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UINT32 pvr_addr;
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UINT32 sys_addr;
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@ -112,7 +114,7 @@ public:
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UINT64 *pvr2_framebuffer_ram;
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UINT64 *elan_ram;
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UINT32 pvrta_regs[0x2000/4];
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UINT32 pvrctrl_regs[0x100/4];
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UINT32 debug_dip_status;
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emu_timer *vbout_timer;
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@ -128,15 +130,106 @@ public:
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powervr2_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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template<class _cb> void set_irq_cb(_cb cb) { irq_cb.set_callback(cb); }
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DECLARE_READ32_MEMBER( pvr_ctrl_r );
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DECLARE_READ32_MEMBER( id_r );
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DECLARE_READ32_MEMBER( revision_r );
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DECLARE_READ32_MEMBER( softreset_r );
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DECLARE_WRITE32_MEMBER( softreset_w );
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DECLARE_WRITE32_MEMBER( startrender_w );
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DECLARE_READ32_MEMBER( param_base_r );
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DECLARE_WRITE32_MEMBER( param_base_w );
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DECLARE_READ32_MEMBER( region_base_r );
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DECLARE_WRITE32_MEMBER( region_base_w );
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DECLARE_READ32_MEMBER( vo_border_col_r );
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DECLARE_WRITE32_MEMBER( vo_border_col_w );
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DECLARE_READ32_MEMBER( fb_r_ctrl_r );
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DECLARE_WRITE32_MEMBER( fb_r_ctrl_w );
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DECLARE_READ32_MEMBER( fb_w_ctrl_r );
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DECLARE_WRITE32_MEMBER( fb_w_ctrl_w );
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DECLARE_READ32_MEMBER( fb_w_linestride_r );
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DECLARE_WRITE32_MEMBER( fb_w_linestride_w );
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DECLARE_READ32_MEMBER( fb_r_sof1_r );
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DECLARE_WRITE32_MEMBER( fb_r_sof1_w );
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DECLARE_READ32_MEMBER( fb_r_sof2_r );
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DECLARE_WRITE32_MEMBER( fb_r_sof2_w );
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DECLARE_READ32_MEMBER( fb_r_size_r );
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DECLARE_WRITE32_MEMBER( fb_r_size_w );
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DECLARE_READ32_MEMBER( fb_w_sof1_r );
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DECLARE_WRITE32_MEMBER( fb_w_sof1_w );
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DECLARE_READ32_MEMBER( fb_w_sof2_r );
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DECLARE_WRITE32_MEMBER( fb_w_sof2_w );
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DECLARE_READ32_MEMBER( fb_x_clip_r );
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DECLARE_WRITE32_MEMBER( fb_x_clip_w );
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DECLARE_READ32_MEMBER( fb_y_clip_r );
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DECLARE_WRITE32_MEMBER( fb_y_clip_w );
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DECLARE_READ32_MEMBER( fpu_param_cfg_r );
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DECLARE_WRITE32_MEMBER( fpu_param_cfg_w );
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DECLARE_READ32_MEMBER( isp_backgnd_t_r );
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DECLARE_WRITE32_MEMBER( isp_backgnd_t_w );
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DECLARE_READ32_MEMBER( spg_hblank_int_r );
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DECLARE_WRITE32_MEMBER( spg_hblank_int_w );
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DECLARE_READ32_MEMBER( spg_vblank_int_r );
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DECLARE_WRITE32_MEMBER( spg_vblank_int_w );
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DECLARE_READ32_MEMBER( spg_hblank_r );
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DECLARE_WRITE32_MEMBER( spg_hblank_w );
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DECLARE_READ32_MEMBER( spg_load_r );
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DECLARE_WRITE32_MEMBER( spg_load_w );
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DECLARE_READ32_MEMBER( spg_vblank_r );
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DECLARE_WRITE32_MEMBER( spg_vblank_w );
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DECLARE_READ32_MEMBER( spg_width_r );
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DECLARE_WRITE32_MEMBER( spg_width_w );
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DECLARE_READ32_MEMBER( text_control_r );
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DECLARE_WRITE32_MEMBER( text_control_w );
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DECLARE_READ32_MEMBER( vo_control_r );
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DECLARE_WRITE32_MEMBER( vo_control_w );
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DECLARE_READ32_MEMBER( vo_startx_r );
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DECLARE_WRITE32_MEMBER( vo_startx_w );
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DECLARE_READ32_MEMBER( vo_starty_r );
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DECLARE_WRITE32_MEMBER( vo_starty_w );
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DECLARE_READ32_MEMBER( pal_ram_ctrl_r );
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DECLARE_WRITE32_MEMBER( pal_ram_ctrl_w );
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DECLARE_READ32_MEMBER( spg_status_r );
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DECLARE_READ32_MEMBER( ta_ol_base_r );
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DECLARE_WRITE32_MEMBER( ta_ol_base_w );
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DECLARE_READ32_MEMBER( ta_isp_base_r );
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DECLARE_WRITE32_MEMBER( ta_isp_base_w );
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DECLARE_READ32_MEMBER( ta_ol_limit_r );
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DECLARE_WRITE32_MEMBER( ta_ol_limit_w );
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DECLARE_READ32_MEMBER( ta_isp_limit_r );
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DECLARE_WRITE32_MEMBER( ta_isp_limit_w );
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DECLARE_READ32_MEMBER( ta_next_opb_r );
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DECLARE_READ32_MEMBER( ta_itp_current_r );
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DECLARE_READ32_MEMBER( ta_alloc_ctrl_r );
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DECLARE_WRITE32_MEMBER( ta_alloc_ctrl_w );
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DECLARE_READ32_MEMBER( ta_list_init_r );
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DECLARE_WRITE32_MEMBER( ta_list_init_w );
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DECLARE_READ32_MEMBER( ta_yuv_tex_base_r );
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DECLARE_WRITE32_MEMBER( ta_yuv_tex_base_w );
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DECLARE_READ32_MEMBER( ta_yuv_tex_ctrl_r );
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DECLARE_WRITE32_MEMBER( ta_yuv_tex_ctrl_w );
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DECLARE_READ32_MEMBER( ta_yuv_tex_cnt_r );
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DECLARE_WRITE32_MEMBER( ta_yuv_tex_cnt_w );
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DECLARE_READ32_MEMBER( ta_list_cont_r );
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DECLARE_WRITE32_MEMBER( ta_list_cont_w );
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DECLARE_READ32_MEMBER( ta_next_opb_init_r );
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DECLARE_WRITE32_MEMBER( ta_next_opb_init_w );
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DECLARE_READ32_MEMBER( fog_table_r );
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DECLARE_WRITE32_MEMBER( fog_table_w );
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DECLARE_READ32_MEMBER( palette_r );
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DECLARE_WRITE32_MEMBER( palette_w );
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DECLARE_READ32_MEMBER( pvr_ctrl_r );
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DECLARE_WRITE32_MEMBER( pvr_ctrl_w );
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DECLARE_READ32_MEMBER( pvr_ta_r );
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DECLARE_READ32_MEMBER( pvr_ta_r );
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DECLARE_WRITE32_MEMBER( pvr_ta_w );
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DECLARE_READ32_MEMBER( pvr2_ta_r );
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DECLARE_READ32_MEMBER( pvr2_ta_r );
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DECLARE_WRITE32_MEMBER( pvr2_ta_w );
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DECLARE_READ32_MEMBER( pvrs_ta_r );
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DECLARE_READ32_MEMBER( pvrs_ta_r );
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DECLARE_WRITE32_MEMBER( pvrs_ta_w );
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DECLARE_READ32_MEMBER( elan_regs_r );
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DECLARE_READ32_MEMBER( elan_regs_r );
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DECLARE_WRITE32_MEMBER( elan_regs_w );
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DECLARE_WRITE64_MEMBER( ta_fifo_poly_w );
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DECLARE_WRITE64_MEMBER( ta_fifo_yuv_w );
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@ -166,6 +259,27 @@ protected:
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private:
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devcb2_write8 irq_cb;
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// Core registers
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UINT32 softreset;
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UINT32 param_base, region_base;
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UINT32 vo_border_col;
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UINT32 fb_r_ctrl, fb_w_ctrl, fb_w_linestride, fb_r_sof1, fb_r_sof2, fb_r_size, fb_w_sof1, fb_w_sof2, fb_x_clip, fb_y_clip;
|
||||
UINT32 fpu_param_cfg;
|
||||
UINT32 isp_backgnd_t;
|
||||
UINT32 spg_hblank_int, spg_vblank_int, spg_hblank, spg_load, spg_vblank, spg_width;
|
||||
UINT32 vo_control, vo_startx, vo_starty;
|
||||
UINT32 text_control;
|
||||
UINT32 pal_ram_ctrl;
|
||||
|
||||
// TA registers
|
||||
UINT32 ta_ol_base, ta_ol_limit, ta_isp_base, ta_isp_limit;
|
||||
UINT32 ta_next_opb, ta_itp_current, ta_alloc_ctrl, ta_next_opb_init;
|
||||
UINT32 ta_yuv_tex_base, ta_yuv_tex_ctrl, ta_yuv_tex_cnt;
|
||||
|
||||
// Other registers
|
||||
UINT32 fog_table[0x80];
|
||||
UINT32 palette[0x400];
|
||||
|
||||
static UINT32 (*const blend_functions[64])(UINT32 s, UINT32 d);
|
||||
|
||||
static inline INT32 clamp(INT32 in, INT32 min, INT32 max);
|
||||
@ -298,6 +412,7 @@ private:
|
||||
void pvr_build_parameterconfig();
|
||||
void process_ta_fifo();
|
||||
void debug_paletteram();
|
||||
void update_screen_format();
|
||||
};
|
||||
|
||||
extern const device_type POWERVR2;
|
||||
|
||||
@ -119,7 +119,7 @@ static ADDRESS_MAP_START( dc_map, AS_PROGRAM, 64, dc_cons_state )
|
||||
AM_RANGE(0x005f7400, 0x005f74ff) AM_READWRITE(dc_mess_g1_ctrl_r, dc_mess_g1_ctrl_w )
|
||||
AM_RANGE(0x005f7800, 0x005f78ff) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
|
||||
AM_RANGE(0x005f7c00, 0x005f7cff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w, U64(0xffffffffffffffff))
|
||||
AM_RANGE(0x005f8000, 0x005f9fff) AM_DEVREADWRITE32("powervr2", powervr2_device, pvr_ta_r, pvr_ta_w, U64(0xffffffffffffffff))
|
||||
AM_RANGE(0x005f8000, 0x005f9fff) AM_DEVICE32("powervr2", powervr2_device, ta_map, U64(0xffffffffffffffff))
|
||||
AM_RANGE(0x00600000, 0x006007ff) AM_READWRITE(dc_modem_r, dc_modem_w )
|
||||
AM_RANGE(0x00700000, 0x00707fff) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
|
||||
AM_RANGE(0x00710000, 0x0071000f) AM_READWRITE(dc_rtc_r, dc_rtc_w )
|
||||
|
||||
Loading…
Reference in New Issue
Block a user