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https://github.com/holub/mame
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i386.cpp: athlon xp updates to memory access (nw)
Now athlon xp supports WrMem and RdMem bits in fixed range MTRRs Accesses to the first megabyte can be directed to system memory (ram) or memory-mapped-io (mmio) (the pci bus) Above 1mb accesses below the top_mem MSR address ram the others mmio At reset everyting is directed to mmio Addresss spaces work in the following way AS_PROGRAM is used for ram AS_DATA is used for mmio AS_OPCODES is used by the debugger disassembler and in memory views to look at the memory contents from the point of view of the microprocessor, including the cache Also some class members have been added to the save state
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702b45b1bc
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03e88d6696
@ -347,6 +347,7 @@ uint64_t athlonxp_device::opcode_rdmsr(bool &valid_msr)
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// 20 MtrrVarDramEn - Enable top of memory address and I/O range registers
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// 19 MtrrFixDramModEn - Enable modification of RdDram and WrDram bits in fixed MTRRs
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// 18 MtrrFixDramEn - Enable RdDram and WrDram attributes in fixed MTRRs
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ret = m_msr_sys_cfg;
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break;
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case 0xC0010015: // HWCR
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break;
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@ -363,6 +364,7 @@ uint64_t athlonxp_device::opcode_rdmsr(bool &valid_msr)
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break;
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case 0xC001001A: // TOP_MEM
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// 39-23 TOM16-0 - Top of Memory, accesses from this address onward are directed to mmio
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ret = (uint64_t)m_msr_top_mem;
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break;
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case 0xC001001D: // TOP_MEM2
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break;
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@ -434,6 +436,7 @@ void athlonxp_device::opcode_wrmsr(uint64_t data, bool &valid_msr)
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case 0x40c: // MC3_CTL
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break;
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case 0xC0010010: // SYS_CFG
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m_msr_sys_cfg = data;
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break;
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case 0xC0010015: // HWCR
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break;
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@ -443,6 +446,7 @@ void athlonxp_device::opcode_wrmsr(uint64_t data, bool &valid_msr)
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case 0xC0010019:
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break;
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case 0xC001001A: // TOP_MEM
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m_msr_top_mem = (offs_t)data;
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break;
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case 0xC0010113: // SMM_MASK
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break;
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@ -133,6 +133,8 @@ pentium3_device::pentium3_device(const machine_config &mconfig, const char *tag,
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athlonxp_device::athlonxp_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: pentium_device(mconfig, ATHLONXP, tag, owner, clock)
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, m_data_config("mmio", ENDIANNESS_LITTLE, 32, 32, 0, 32, 12)
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, m_opcodes_config("debugger", ENDIANNESS_LITTLE, 32, 32, 0, 32, 12)
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{
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// TODO: put correct value
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set_vtlb_dynamic_entries(256);
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@ -4692,11 +4694,22 @@ void athlonxp_device::device_start()
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{
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i386_common_init();
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register_state_i386_x87_xmm();
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m_data = &space(AS_DATA);
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m_opcodes = &space(AS_OPCODES);
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mmacache32 = m_data->cache<2, 0, ENDIANNESS_LITTLE>();
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m_opcodes->install_read_handler(0, 0xffffffff, read32_delegate(FUNC(athlonxp_device::debug_read_memory), this));
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build_x87_opcode_table();
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build_opcode_table(OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_PPRO | OP_MMX | OP_SSE);
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m_cycle_table_rm = cycle_table_rm[CPU_CYCLES_PENTIUM].get(); // TODO: generate own cycle tables
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m_cycle_table_pm = cycle_table_pm[CPU_CYCLES_PENTIUM].get(); // TODO: generate own cycle tables
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// put savestate calls here
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save_item(NAME(m_processor_name_string));
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save_item(NAME(m_msr_top_mem));
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save_item(NAME(m_msr_sys_cfg));
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save_item(NAME(m_msr_mtrrfix));
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save_item(NAME(m_memory_ranges_1m));
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}
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void athlonxp_device::device_reset()
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@ -4745,7 +4758,9 @@ void athlonxp_device::device_reset()
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for (int n = 0; n < 11; n++)
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m_msr_mtrrfix[n] = 0;
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for (int n = 0; n < (1024 / 4); n++)
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m_memory_ranges_1m[n] = 0; // change the 0 to 6 to test the cache just after reset
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m_memory_ranges_1m[n] = 0;
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m_msr_top_mem = 1024 * 1024;
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m_msr_sys_cfg = 0;
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m_cpuid_max_input_value_eax = 0x01;
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m_cpu_version = REG32(EDX);
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@ -4756,6 +4771,16 @@ void athlonxp_device::device_reset()
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CHANGE_PC(m_eip);
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}
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device_memory_interface::space_config_vector athlonxp_device::memory_space_config() const
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{
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return space_config_vector{
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std::make_pair(AS_PROGRAM, &m_program_config),
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std::make_pair(AS_IO, &m_io_config),
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std::make_pair(AS_DATA, &m_data_config),
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std::make_pair(AS_OPCODES, &m_opcodes_config)
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};
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}
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void athlonxp_device::parse_mtrrfix(u64 mtrr, offs_t base, int kblock)
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{
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int nb = kblock / 4;
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@ -4788,11 +4813,48 @@ int athlonxp_device::check_cacheable(offs_t address)
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return m_memory_ranges_1m[block] | disabled;
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}
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template <int wr>
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int athlonxp_device::address_mode(offs_t address)
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{
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if (address >= m_msr_top_mem)
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return 1;
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if (address >= 1 * 1024 * 1024)
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return 0;
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if ((m_memory_ranges_1m[address >> 12] & (1 << (3 + wr))) != 0)
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return 0;
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return 1;
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}
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READ32_MEMBER(athlonxp_device::debug_read_memory)
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{
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offs_t address = offset << 2;
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int mode = check_cacheable(address);
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bool nocache = false;
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address_space *m = m_program;
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u8 *data;
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if ((mode & 7) == 0)
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nocache = true;
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if (mode & 1)
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nocache = true;
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if (nocache == false)
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{
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int offset = (address & 63);
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data = cache.search<CacheRead>(address);
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if (data)
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return *(u32 *)(data + offset);
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}
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if (address_mode<1>(address))
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m = m_data;
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return m->read_dword(address);
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}
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template <class dt, offs_t xorle>
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dt athlonxp_device::opcode_read_cache(offs_t address)
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{
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int mode = check_cacheable(address);
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bool nocache = false;
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memory_access_cache<2, 0, ENDIANNESS_LITTLE> *m = macache32;
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u8 *data;
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if ((mode & 7) == 0)
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@ -4814,31 +4876,21 @@ dt athlonxp_device::opcode_read_cache(offs_t address)
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offs_t old_address = cache.old();
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for (int w = 0; w < 64; w += 4)
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macache32->write_dword(old_address + w, *(u32 *)(data + w));
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m->write_dword(old_address + w, *(u32 *)(data + w));
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}
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for (int r = 0; r < 64; r += 4)
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*(u32 *)(data + r) = macache32->read_dword(address + r);
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*(u32 *)(data + r) = m->read_dword(address + r);
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return *(dt *)(data + offset);
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}
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else
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{
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if (sizeof(dt) == 1)
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return macache32->read_byte(address);
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else if (sizeof(dt) == 2)
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return macache32->read_word(address);
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else
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return macache32->read_dword(address);
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}
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}
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if (address_mode<1>(address))
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m = mmacache32;
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if (sizeof(dt) == 1)
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return m->read_byte(address);
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else if (sizeof(dt) == 2)
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return m->read_word(address);
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else
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{
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if (sizeof(dt) == 1)
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return macache32->read_byte(address);
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else if (sizeof(dt) == 2)
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return macache32->read_word(address);
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else
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return macache32->read_dword(address);
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}
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return m->read_dword(address);
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}
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template <class dt, offs_t xorle>
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@ -4846,6 +4898,7 @@ dt athlonxp_device::program_read_cache(offs_t address)
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{
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int mode = check_cacheable(address);
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bool nocache = false;
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address_space *m = m_program;
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u8 *data;
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if ((mode & 7) == 0)
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@ -4867,31 +4920,21 @@ dt athlonxp_device::program_read_cache(offs_t address)
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offs_t old_address = cache.old();
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for (int w = 0; w < 64; w += 4)
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m_program->write_dword(old_address + w, *(u32 *)(data + w));
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m->write_dword(old_address + w, *(u32 *)(data + w));
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}
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for (int r = 0; r < 64; r += 4)
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*(u32 *)(data + r) = m_program->read_dword(address + r);
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*(u32 *)(data + r) = m->read_dword(address + r);
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return *(dt *)(data + offset);
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}
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else
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{
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if (sizeof(dt) == 1)
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return m_program->read_byte(address);
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else if (sizeof(dt) == 2)
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return m_program->read_word(address);
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else
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return m_program->read_dword(address);
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}
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}
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if (address_mode<1>(address))
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m = m_data;
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if (sizeof(dt) == 1)
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return m->read_byte(address);
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else if (sizeof(dt) == 2)
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return m->read_word(address);
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else
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{
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if (sizeof(dt) == 1)
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return m_program->read_byte(address);
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else if (sizeof(dt) == 2)
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return m_program->read_word(address);
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else
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return m_program->read_dword(address);
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}
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return m->read_dword(address);
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}
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template <class dt, offs_t xorle>
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@ -4899,6 +4942,7 @@ void athlonxp_device::program_write_cache(offs_t address, dt data)
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{
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int mode = check_cacheable(address);
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bool nocache = false;
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address_space *m = m_program;
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u8 *dataw;
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if ((mode & 7) == 0)
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@ -4923,36 +4967,28 @@ void athlonxp_device::program_write_cache(offs_t address, dt data)
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offs_t old_address = cache.old();
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for (int w = 0; w < 64; w += 4)
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m_program->write_dword(old_address + w, *(u32 *)(dataw + w));
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m->write_dword(old_address + w, *(u32 *)(dataw + w));
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}
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for (int r = 0; r < 64; r += 4)
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*(u32 *)(dataw + r) = m_program->read_dword(address + r);
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*(u32 *)(dataw + r) = m->read_dword(address + r);
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*(dt *)(dataw + offset) = data;
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}
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else
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{
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if (sizeof(dt) == 1)
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m_program->write_byte(address, data);
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else if (sizeof(dt) == 2)
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m_program->write_word(address, data);
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else
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m_program->write_dword(address, data);
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return;
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}
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}
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if (address_mode<0>(address))
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m = m_data;
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if (sizeof(dt) == 1)
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m->write_byte(address, data);
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else if (sizeof(dt) == 2)
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m->write_word(address, data);
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else
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{
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if (sizeof(dt) == 1)
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m_program->write_byte(address, data);
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else if (sizeof(dt) == 2)
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m_program->write_word(address, data);
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else
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m_program->write_dword(address, data);
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}
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m->write_dword(address, data);
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}
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void athlonxp_device::cache_writeback()
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{
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// dirty cachelines are written back to memory
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address_space *m = m_program;
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u32 base;
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u8 *data;
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@ -4960,7 +4996,7 @@ void athlonxp_device::cache_writeback()
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while (data != nullptr)
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{
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for (int w = 0; w < 64; w += 4)
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m_program->write_dword(base + w, *(u32 *)(data + w));
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m->write_dword(base + w, *(u32 *)(data + w));
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data = cache.next_dirty(base, false);
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}
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}
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@ -1655,15 +1655,28 @@ protected:
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virtual void mem_pwd16(offs_t address, u16 data) override { program_write_cache<u16, NATIVE_ENDIAN_VALUE_LE_BE(0, 2)>(address, data); }
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virtual void mem_pwd32(offs_t address, u32 data) override { program_write_cache<u32, 0>(address, data); }
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// device_memory_interface override
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virtual space_config_vector memory_space_config() const override;
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private:
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void parse_mtrrfix(u64 mtrr, offs_t base, int kblock);
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int check_cacheable(offs_t address);
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inline int check_cacheable(offs_t address);
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template <int wr> int address_mode(offs_t address);
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template <class dt, offs_t xorle> dt opcode_read_cache(offs_t address);
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template <class dt, offs_t xorle> dt program_read_cache(offs_t address);
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template <class dt, offs_t xorle> void program_write_cache(offs_t address, dt data);
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DECLARE_READ32_MEMBER(debug_read_memory);
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address_space_config m_data_config;
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address_space *m_data;
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address_space_config m_opcodes_config;
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address_space *m_opcodes;
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memory_access_cache<2, 0, ENDIANNESS_LITTLE> *mmacache32;
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uint8_t m_processor_name_string[48];
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offs_t m_msr_top_mem;
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uint64_t m_msr_sys_cfg;
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uint64_t m_msr_mtrrfix[11];
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uint8_t m_memory_ranges_1m[1024 / 4];
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cpucache<17, 9, Cache2Way, CacheLineBytes64> cache; // 512 sets, 2 ways (cachelines per set), 64 bytes per cacheline
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