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Reworked truthtables a bit.

Browse Source 
- Moved 9312 and 74279 to ttl macro library.
- Renamed TTL_9312_* to DM9312. This is more appropriate.
- Fixed a number of warnings from latest ubuntu clang-5.0.
This commit is contained in:
couriersud 2017-02-17 01:33:20 +01:00
parent 776d89919b
commit 0716d96514
23 changed files with 418 additions and 631 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
scripts/src/netlist.lua
View File

@ -159,8 +159,6 @@ project "netlist"
MAME_DIR .. "src/lib/netlist/devices/nld_74193.h",
MAME_DIR .. "src/lib/netlist/devices/nld_74194.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_74194.h",
MAME_DIR .. "src/lib/netlist/devices/nld_74279.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_74279.h",
MAME_DIR .. "src/lib/netlist/devices/nld_74365.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_74365.h",
MAME_DIR .. "src/lib/netlist/devices/nld_74ls629.cpp",
@ -175,8 +173,6 @@ project "netlist"
MAME_DIR .. "src/lib/netlist/devices/nld_82S126.h",
MAME_DIR .. "src/lib/netlist/devices/nld_9310.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_9310.h",
MAME_DIR .. "src/lib/netlist/devices/nld_9312.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_9312.h",
MAME_DIR .. "src/lib/netlist/devices/nld_9316.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_9316.h",
MAME_DIR .. "src/lib/netlist/devices/nld_9322.cpp",

3
src/lib/netlist/analog/nlid_fourterm.h
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@ -136,7 +136,6 @@ namespace netlist {
{
public:
NETLIB_CONSTRUCTOR_DERIVED(CCCS, VCCS)
, m_gfac(1.0)
{
m_gfac = NL_FCONST(1.0) / m_RI();
}
@ -145,8 +144,6 @@ namespace netlist {
NETLIB_UPDATEI();
NETLIB_RESETI();
NETLIB_UPDATE_PARAMI();
nl_double m_gfac;
};

2
src/lib/netlist/build/makefile
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@ -100,7 +100,6 @@ NLOBJS := \
$(NLOBJ)/devices/nld_74192.o \
$(NLOBJ)/devices/nld_74193.o \
$(NLOBJ)/devices/nld_74194.o \
$(NLOBJ)/devices/nld_74279.o \
$(NLOBJ)/devices/nld_74365.o \
$(NLOBJ)/devices/nld_74ls629.o \
$(NLOBJ)/devices/nld_82S16.o \
@ -108,7 +107,6 @@ NLOBJS := \
$(NLOBJ)/devices/nld_82S123.o \
$(NLOBJ)/devices/nld_82S126.o \
$(NLOBJ)/devices/nld_9310.o \
$(NLOBJ)/devices/nld_9312.o \
$(NLOBJ)/devices/nld_9316.o \
$(NLOBJ)/devices/nld_9322.o \
$(NLOBJ)/devices/nld_am2847.o \

3
src/lib/netlist/devices/net_lib.cpp
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@ -93,7 +93,6 @@ namespace netlist
ENTRYX(82S123, PROM_82S123, "+CEQ,+A0,+A1,+A2,+A3,+A4")
ENTRYX(82S126, PROM_82S126, "+CE1Q,+CE2Q,+A0,+A1,+A2,+A3,+A4,+A5,+A6,+A7")
ENTRYX(9310, TTL_9310, "")
ENTRYX(9312, TTL_9312, "+A,+B,+C,+D0,+D1,+D2,+D3,+D4,+D5,+D6,+D7,+G")
ENTRYX(9316, TTL_9316, "+CLK,+ENP,+ENT,+CLRQ,+LOADQ,+A,+B,+C,+D")
ENTRYX(9322, TTL_9322, "+SELECT,+A1,+B1,+A2,+B2,+A3,+B3,+A4,+B4,+STROBE")
ENTRYX(9334, TTL_9334, "+CQ,+EQ,+D,+A0,+A1,+A2")
@ -133,7 +132,6 @@ namespace netlist
ENTRYX(74192_dip, TTL_74192_DIP, "")
ENTRYX(74193_dip, TTL_74193_DIP, "")
ENTRYX(74194_dip, TTL_74194_DIP, "")
ENTRYX(74279_dip, TTL_74279_DIP, "")
ENTRYX(74365_dip, TTL_74365_DIP, "")
ENTRYX(82S16_dip, TTL_82S16_DIP, "")
ENTRYX(82S115_dip, PROM_82S115_DIP, "")
@ -141,7 +139,6 @@ namespace netlist
ENTRYX(82S126_dip, PROM_82S126_DIP, "")
ENTRYX(9602_dip, TTL_9602_DIP, "")
ENTRYX(9310_dip, TTL_9310_DIP, "")
ENTRYX(9312_dip, TTL_9312_DIP, "")
ENTRYX(9316_dip, TTL_9316_DIP, "")
ENTRYX(9322_dip, TTL_9322_DIP, "")
ENTRYX(9334_dip, TTL_9334_DIP, "")

2
src/lib/netlist/devices/net_lib.h
View File

@ -59,7 +59,6 @@
#include "nld_74192.h"
#include "nld_74193.h"
#include "nld_74194.h"
#include "nld_74279.h"
#include "nld_74365.h"
#include "nld_74ls629.h"
#include "nld_82S16.h"
@ -67,7 +66,6 @@
#include "nld_82S123.h"
#include "nld_82S126.h"
#include "nld_9310.h"
#include "nld_9312.h"
#include "nld_9316.h"
#include "nld_9322.h"

84
src/lib/netlist/devices/nld_74279.cpp
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@ -1,84 +0,0 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_74279.c
*
*/
#include "nlid_truthtable.h"
#include "nld_74279.h"
#include "../nl_base.h"
namespace netlist
{
namespace devices
{
NETLIB_TRUTHTABLE(74279A, 3, 1);
NETLIB_TRUTHTABLE(74279B, 4, 1);
NETLIB_OBJECT(74279_dip)
{
NETLIB_CONSTRUCTOR(74279_dip)
, m_1(*this, "1")
, m_2(*this, "2")
, m_3(*this, "3")
, m_4(*this, "4")
{
register_subalias("1", m_1.m_I[2]); //R
register_subalias("2", m_1.m_I[0]);
register_subalias("3", m_1.m_I[1]);
register_subalias("4", m_1.m_Q[0]);
register_subalias("5", m_2.m_I[1]); //R
register_subalias("6", m_2.m_I[0]);
register_subalias("7", m_2.m_Q[0]);
register_subalias("9", m_3.m_Q[0]);
register_subalias("10", m_3.m_I[2]); //R
register_subalias("11", m_3.m_I[0]);
register_subalias("12", m_3.m_I[1]);
register_subalias("13", m_4.m_Q[0]);
register_subalias("14", m_4.m_I[1]); //R
register_subalias("15", m_4.m_I[0]);
}
//NETLIB_RESETI();
//NETLIB_UPDATEI();
protected:
NETLIB_SUB(74279B) m_1;
NETLIB_SUB(74279A) m_2;
NETLIB_SUB(74279B) m_3;
NETLIB_SUB(74279A) m_4;
};
nld_74279A::truthtable_t nld_74279A::m_ttbl;
nld_74279B::truthtable_t nld_74279B::m_ttbl;
const pstring nld_74279A::m_desc[] = {
"S,R,_Q|Q",
"0,X,X|1|22",
"1,0,X|0|27",
"1,1,0|0|27", //15
"1,1,1|1|22",
""
};
const pstring nld_74279B::m_desc[] = {
"S1,S2,R,_Q|Q",
"0,X,X,X|1|22",
"X,0,X,X|1|22",
"1,1,0,X|0|27",
"1,1,1,0|0|27", // 15
"1,1,1,1|1|22",
""
};
NETLIB_DEVICE_IMPL(74279_dip)
} //namespace devices
} // namespace netlist

42
src/lib/netlist/devices/nld_74279.h
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@ -1,42 +0,0 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_74279.h
*
* DM74279: Quad S-R Latch
*
* +--------------+
* 1R |1 ++ 16| VCC
* 1S1 |2 15| 4S
* 1S2 |3 14| 4R
* 1Q |4 74279 13| 4Q
* 2R |5 12| 3S2
* 2S |6 11| 3S1
* 2Q |7 10| 3R
* GND |8 9| 3Q
* +--------------+
* ___
*
* +---+---+---++---+
* |S1 |S2 | R || Q |
* +===+===+===++===+
* | 0 | 0 | 0 || 1 |
* | 0 | 1 | 1 || 1 |
* | 1 | 0 | 1 || 1 |
* | 1 | 1 | 0 || 0 |
* | 1 | 1 | 1 ||QP |
* +---+---+---++---+
*
* QP: Previous Q
*
* Naming conventions follow Fairchild Semiconductor datasheet
*
*/
#ifndef NLD_74279_H_
#define NLD_74279_H_
#define TTL_74279_DIP(name) \
NET_REGISTER_DEV(TTL_74279_DIP, name)
#endif /* NLD_74279_H_ */

2
src/lib/netlist/devices/nld_7493.cpp
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@ -69,7 +69,7 @@ namespace netlist
logic_output_t m_QC;
logic_output_t m_QD;
state_var_u8 m_reset;
state_var<netlist_sig_t> m_reset;
state_var_u8 m_a;
state_var_u8 m_bcd;
};

202
src/lib/netlist/devices/nld_9312.cpp
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@ -1,202 +0,0 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_9312.c
*
*/
/*
* +---+---+---+---++---+---+
* | C | B | A | G || Y | YQ|
* +===+===+===+===++===+===+
* | X | X | X | 1 || 0| 1 |
* | 0 | 0 | 0 | 0 || D0|D0Q|
* | 0 | 0 | 1 | 0 || D1|D1Q|
* | 0 | 1 | 0 | 0 || D2|D2Q|
* | 0 | 1 | 1 | 0 || D3|D3Q|
* | 1 | 0 | 0 | 0 || D4|D4Q|
* | 1 | 0 | 1 | 0 || D5|D5Q|
* | 1 | 1 | 0 | 0 || D6|D6Q|
* | 1 | 1 | 1 | 0 || D7|D7Q|
* +---+---+---+---++---+---+
*/
#include "nlid_truthtable.h"
#include "nld_9312.h"
namespace netlist
{
namespace devices
{
#if (USE_TRUTHTABLE)
/* FIXME: The truthtable implementation is a lot faster than
* the carefully crafted code :-(
* Convert this into a macro module.
*/
NETLIB_TRUTHTABLE(9312, 12, 2);
#else
NETLIB_OBJECT(9312)
{
NETLIB_CONSTRUCTOR(9312)
, m_A(*this, "A")
, m_B(*this, "B")
, m_C(*this, "C")
, m_G(*this, "G")
, m_D(*this, {{"D0","D1","D2","D3","D4","D5","D6","D7"}})
, m_Y(*this, "Y")
, m_YQ(*this, "YQ")
, m_last_chan(*this, "m_last_chan", 0)
, m_last_G(*this, "m_last_G", 0)
{
}
NETLIB_UPDATEI();
NETLIB_RESETI();
public:
logic_input_t m_A;
logic_input_t m_B;
logic_input_t m_C;
logic_input_t m_G;
object_array_t<logic_input_t, 8> m_D;
logic_output_t m_Y;
logic_output_t m_YQ;
state_var_u8 m_last_chan;
state_var_u8 m_last_G;
};
#endif
NETLIB_OBJECT(9312_dip)
{
NETLIB_CONSTRUCTOR(9312_dip)
, m_sub(*this, "1")
{
#if (1 && USE_TRUTHTABLE)
register_subalias("13", m_sub.m_I[0]);
register_subalias("12", m_sub.m_I[1]);
register_subalias("11", m_sub.m_I[2]);
register_subalias("10", m_sub.m_I[3]);
register_subalias("1", m_sub.m_I[4]);
register_subalias("2", m_sub.m_I[5]);
register_subalias("3", m_sub.m_I[6]);
register_subalias("4", m_sub.m_I[7]);
register_subalias("5", m_sub.m_I[8]);
register_subalias("6", m_sub.m_I[9]);
register_subalias("7", m_sub.m_I[10]);
register_subalias("9", m_sub.m_I[11]);
register_subalias("15", m_sub.m_Q[0]); // Y
register_subalias("14", m_sub.m_Q[1]); // YQ
#else
register_subalias("13", m_sub.m_C);
register_subalias("12", m_sub.m_B);
register_subalias("11", m_sub.m_A);
register_subalias("10", m_sub.m_G);
register_subalias("1", m_sub.m_D[0]);
register_subalias("2", m_sub.m_D[1]);
register_subalias("3", m_sub.m_D[2]);
register_subalias("4", m_sub.m_D[3]);
register_subalias("5", m_sub.m_D[4]);
register_subalias("6", m_sub.m_D[5]);
register_subalias("7", m_sub.m_D[6]);
register_subalias("9", m_sub.m_D[7]);
register_subalias("15", m_sub.m_Y); // Y
register_subalias("14", m_sub.m_YQ); // YQ
#endif
}
//NETLIB_RESETI();
//NETLIB_UPDATEI();
protected:
NETLIB_SUB(9312) m_sub;
};
#if (USE_TRUTHTABLE)
nld_9312::truthtable_t nld_9312::m_ttbl;
/* FIXME: Data changes are propagating faster than changing selects A,B,C
* Please refer to data sheet.
* This would require a state machine, thus we do not
* do this right now.
*/
const pstring nld_9312::m_desc[] = {
" C, B, A, G,D0,D1,D2,D3,D4,D5,D6,D7| Y,YQ",
" X, X, X, 1, X, X, X, X, X, X, X, X| 0, 1|33,19",
" 0, 0, 0, 0, 0, X, X, X, X, X, X, X| 0, 1|33,28",
" 0, 0, 0, 0, 1, X, X, X, X, X, X, X| 1, 0|33,28",
" 0, 0, 1, 0, X, 0, X, X, X, X, X, X| 0, 1|33,28",
" 0, 0, 1, 0, X, 1, X, X, X, X, X, X| 1, 0|33,28",
" 0, 1, 0, 0, X, X, 0, X, X, X, X, X| 0, 1|33,28",
" 0, 1, 0, 0, X, X, 1, X, X, X, X, X| 1, 0|33,28",
" 0, 1, 1, 0, X, X, X, 0, X, X, X, X| 0, 1|33,28",
" 0, 1, 1, 0, X, X, X, 1, X, X, X, X| 1, 0|33,28",
" 1, 0, 0, 0, X, X, X, X, 0, X, X, X| 0, 1|33,28",
" 1, 0, 0, 0, X, X, X, X, 1, X, X, X| 1, 0|33,28",
" 1, 0, 1, 0, X, X, X, X, X, 0, X, X| 0, 1|33,28",
" 1, 0, 1, 0, X, X, X, X, X, 1, X, X| 1, 0|33,28",
" 1, 1, 0, 0, X, X, X, X, X, X, 0, X| 0, 1|33,28",
" 1, 1, 0, 0, X, X, X, X, X, X, 1, X| 1, 0|33,28",
" 1, 1, 1, 0, X, X, X, X, X, X, X, 0| 0, 1|33,28",
" 1, 1, 1, 0, X, X, X, X, X, X, X, 1| 1, 0|33,28",
""
};
#else
NETLIB_UPDATE(9312)
{
const NLUINT8 G = INPLOGIC(m_G);
if (G)
{
const netlist_time delay[2] = { NLTIME_FROM_NS(33), NLTIME_FROM_NS(19) };
OUTLOGIC(m_Y, 0, delay[0]);
OUTLOGIC(m_YQ, 1, delay[1]);
m_A.inactivate();
m_B.inactivate();
m_C.inactivate();
m_last_G = G;
}
else
{
if (m_last_G)
{
m_last_G = G;
m_A.activate();
m_B.activate();
m_C.activate();
}
constexpr netlist_time delay[2] = { NLTIME_FROM_NS(33), NLTIME_FROM_NS(28) };
const NLUINT8 chan = INPLOGIC(m_A) | (INPLOGIC(m_B)<<1) | (INPLOGIC(m_C)<<2);
if (m_last_chan != chan)
{
m_D[m_last_chan].inactivate();
m_D[chan].activate();
}
const auto val = INPLOGIC(m_D[chan]);
OUTLOGIC(m_Y, val, delay[val]);
OUTLOGIC(m_YQ, !val, delay[!val]);
m_last_chan = chan;
}
}
NETLIB_RESET(9312)
{
}
#endif
NETLIB_DEVICE_IMPL(9312)
NETLIB_DEVICE_IMPL(9312_dip)
} //namespace devices
} // namespace netlist

60
src/lib/netlist/devices/nld_9312.h
View File

@ -1,60 +0,0 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_9312.h
*
* DM9312: One of Eight Line Data Selectors/Multiplexers
*
* +--------------+
* D0 |1 ++ 16| VCC
* D1 |2 15| Y
* D2 |3 14| YQ
* D3 |4 9312 13| C
* D4 |5 12| B
* D5 |6 11| A
* D6 |7 10| G Strobe
* GND |8 9| D7
* +--------------+
* __
* +---+---+---+---++---+---+
* | C | B | A | G || Y | YQ|
* +===+===+===+===++===+===+
* | X | X | X | 1 || 0| 1 |
* | 0 | 0 | 0 | 0 || D0|D0Q|
* | 0 | 0 | 1 | 0 || D1|D1Q|
* | 0 | 1 | 0 | 0 || D2|D2Q|
* | 0 | 1 | 1 | 0 || D3|D3Q|
* | 1 | 0 | 0 | 0 || D4|D4Q|
* | 1 | 0 | 1 | 0 || D5|D5Q|
* | 1 | 1 | 0 | 0 || D6|D6Q|
* | 1 | 1 | 1 | 0 || D7|D7Q|
* +---+---+---+---++---+---+
*
* Naming conventions follow National Semiconductor datasheet
*
*/
#ifndef NLD_9312_H_
#define NLD_9312_H_
#include "../nl_setup.h"
#define TTL_9312(name, cA, cB, cC, cD0, cD1, cD2, cD3, cD4, cD5, cD6, cD7, cSTROBE) \
NET_REGISTER_DEV(TTL_9312, name) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D0, cD0) \
NET_CONNECT(name, D1, cD1) \
NET_CONNECT(name, D2, cD2) \
NET_CONNECT(name, D3, cD3) \
NET_CONNECT(name, D4, cD4) \
NET_CONNECT(name, D5, cD5) \
NET_CONNECT(name, D6, cD6) \
NET_CONNECT(name, D7, cD7) \
NET_CONNECT(name, G, cSTROBE)
#define TTL_9312_DIP(name) \
NET_REGISTER_DEV(TTL_9312_DIP, name)
#endif /* NLD_9312_H_ */

18
src/lib/netlist/devices/nlid_proxy.cpp
View File

@ -64,12 +64,12 @@ namespace netlist
{
nl_assert(m_logic_family != nullptr);
// FIXME: Variable supply voltage!
double supply_V = logic_family().fixed_V();
double supply_V = logic_family()->fixed_V();
if (supply_V == 0.0) supply_V = 5.0;
if (m_I.Q_Analog() > logic_family().high_thresh_V(0.0, supply_V))
if (m_I.Q_Analog() > logic_family()->high_thresh_V(0.0, supply_V))
out().push(1, NLTIME_FROM_NS(1));
else if (m_I.Q_Analog() < logic_family().low_thresh_V(0.0, supply_V))
else if (m_I.Q_Analog() < logic_family()->low_thresh_V(0.0, supply_V))
out().push(0, NLTIME_FROM_NS(1));
else
{
@ -136,15 +136,15 @@ namespace netlist
void nld_d_to_a_proxy::reset()
{
// FIXME: Variable voltage
double supply_V = logic_family().fixed_V();
double supply_V = logic_family()->fixed_V();
if (supply_V == 0.0) supply_V = 5.0;
//m_Q.initial(0.0);
m_last_state = -1;
m_RV.do_reset();
m_is_timestep = m_RV.m_P.net().solver()->has_timestep_devices();
m_RV.set(NL_FCONST(1.0) / logic_family().R_low(),
logic_family().low_V(0.0, supply_V), 0.0);
m_RV.set(NL_FCONST(1.0) / logic_family()->R_low(),
logic_family()->low_V(0.0, supply_V), 0.0);
}
NETLIB_UPDATE(d_to_a_proxy)
@ -153,11 +153,11 @@ namespace netlist
if (state != m_last_state)
{
// FIXME: Variable voltage
double supply_V = logic_family().fixed_V();
double supply_V = logic_family()->fixed_V();
if (supply_V == 0.0) supply_V = 5.0;
m_last_state = state;
const nl_double R = state ? logic_family().R_high() : logic_family().R_low();
const nl_double V = state ? logic_family().high_V(0.0, supply_V) : logic_family().low_V(0.0, supply_V);
const nl_double R = state ? logic_family()->R_high() : logic_family()->R_low();
const nl_double V = state ? logic_family()->high_V(0.0, supply_V) : logic_family()->low_V(0.0, supply_V);
// We only need to update the net first if this is a time stepping net
if (m_is_timestep)

6
src/lib/netlist/devices/nlid_proxy.h
View File

@ -35,12 +35,6 @@ namespace netlist
detail::core_terminal_t &proxy_term() const { return *m_proxy_term; }
protected:
const logic_family_desc_t *m_logic_family;
virtual const logic_family_desc_t &logic_family() const
{
return *m_logic_family;
}
private:
logic_t *m_term_proxied;

177
src/lib/netlist/devices/nlid_truthtable.cpp
View File

@ -14,6 +14,181 @@ namespace netlist
{
namespace devices
{
// ----------------------------------------------------------------------------------------
// Truthtable description ....
// ----------------------------------------------------------------------------------------
struct packed_int
{
template<typename C>
packed_int(C *data)
: m_data(data)
, m_size(sizeof(C))
{}
void set(const size_t pos, const uint_least64_t val)
{
switch (m_size)
{
case 1: static_cast<uint_least8_t *>(m_data)[pos] = static_cast<uint_least8_t>(val); break;
case 2: static_cast<uint_least16_t *>(m_data)[pos] = static_cast<uint_least16_t>(val); break;
case 4: static_cast<uint_least32_t *>(m_data)[pos] = static_cast<uint_least32_t>(val); break;
case 8: static_cast<uint_least64_t *>(m_data)[pos] = static_cast<uint_least64_t>(val); break;
default: { }
}
}
uint_least64_t operator[] (size_t pos) const
{
switch (m_size)
{
case 1: return static_cast<uint_least8_t *>(m_data)[pos];
case 2: return static_cast<uint_least16_t *>(m_data)[pos];
case 4: return static_cast<uint_least32_t *>(m_data)[pos];
case 8: return static_cast<uint_least64_t *>(m_data)[pos];
default:
return 0; //should never happen
}
}
uint_least64_t adjust(uint_least64_t val) const
{
switch (m_size)
{
case 1: return static_cast<uint_least8_t >(val);
case 2: return static_cast<uint_least16_t>(val);
case 4: return static_cast<uint_least32_t>(val);
case 8: return static_cast<uint_least64_t>(val);
default:
return 0; //should never happen
}
}
private:
void *m_data;
size_t m_size;
};
struct truthtable_desc_t
{
truthtable_desc_t(unsigned NO, unsigned NI, bool *initialized,
packed_int outs, uint_least8_t *timing, netlist_time *timing_nt)
: m_NO(NO), m_NI(NI), m_initialized(initialized),
m_outs(outs), m_timing(timing), m_timing_nt(timing_nt),
m_num_bits(m_NI),
m_size(1 << (m_num_bits))
{
}
void setup(const std::vector<pstring> &desc, uint_least64_t disabled_ignore);
private:
void help(unsigned cur, std::vector<pstring> list,
uint_least64_t state, uint_least64_t val, std::vector<uint_least8_t> &timing_index);
static unsigned count_bits(uint_least64_t v);
static uint_least64_t set_bits(uint_least64_t v, uint_least64_t b);
uint_least64_t get_ignored_simple(uint_least64_t i);
uint_least64_t get_ignored_extended(uint_least64_t i);
unsigned m_NO;
unsigned m_NI;
bool *m_initialized;
packed_int m_outs;
uint_least8_t *m_timing;
netlist_time *m_timing_nt;
/* additional values */
const std::size_t m_num_bits;
const std::size_t m_size;
};
template<unsigned m_NI, unsigned m_NO>
template <class C>
nld_truthtable_t<m_NI, m_NO>::nld_truthtable_t(C &owner, const pstring &name, const logic_family_desc_t *fam,
truthtable_t *ttp, const pstring *desc)
: device_t(owner, name)
, m_fam(*this, fam)
, m_ign(*this, "m_ign", 0)
, m_active(*this, "m_active", 1)
, m_ttp(ttp)
{
while (*desc != "" )
{
m_desc.push_back(*desc);
desc++;
}
init();
}
template<unsigned m_NI, unsigned m_NO>
void NETLIB_NAME(truthtable_t)<m_NI, m_NO>::init()
{
set_hint_deactivate(true);
pstring header = m_desc[0];
std::vector<pstring> io(plib::psplit(header,"|"));
// checks
nl_assert_always(io.size() == 2, "too many '|'");
std::vector<pstring> inout(plib::psplit(io[0], ","));
nl_assert_always(inout.size() == m_num_bits, "bitcount wrong");
std::vector<pstring> out(plib::psplit(io[1], ","));
nl_assert_always(out.size() == m_NO, "output count wrong");
for (std::size_t i=0; i < m_NI; i++)
{
inout[i] = inout[i].trim();
m_I.emplace(i, *this, inout[i]);
}
for (std::size_t i=0; i < m_NO; i++)
{
out[i] = out[i].trim();
m_Q.emplace(i, *this, out[i]);
}
// Connect output "Q" to input "_Q" if this exists
// This enables timed state without having explicit state ....
uint_least64_t disabled_ignore = 0;
for (std::size_t i=0; i < m_NO; i++)
{
pstring tmp = "_" + out[i];
const std::size_t idx = plib::container::indexof(inout, tmp);
if (idx != plib::container::npos)
{
connect(m_Q[i], m_I[idx]);
// disable ignore for this inputs altogether.
// FIXME: This shouldn't be necessary
disabled_ignore |= (1<<idx);
}
}
m_ign = 0;
truthtable_desc_t desc(m_NO, m_NI, &m_ttp->m_initialized,
packed_int(m_ttp->m_outs),
m_ttp->m_timing, m_ttp->m_timing_nt);
desc.setup(m_desc, disabled_ignore * 0);
#if 0
printf("%s\n", name().c_str());
for (int j=0; j < m_size; j++)
printf("%05x %04x %04x %04x\n", j, m_ttp->m_outs[j] & ((1 << m_NO)-1),
m_ttp->m_outs[j] >> m_NO, m_ttp->m_timing[j * m_NO + 0]);
for (int k=0; m_ttp->m_timing_nt[k] != netlist_time::zero(); k++)
printf("%d %f\n", k, m_ttp->m_timing_nt[k].as_double() * 1000000.0);
#endif
}
// ----------------------------------------------------------------------------------------
// Truthtable class ....
// ----------------------------------------------------------------------------------------
// ----------------------------------------------------------------------------------------
// Truthtable factory ....
// ----------------------------------------------------------------------------------------
template<unsigned m_NI, unsigned m_NO>
class netlist_factory_truthtable_t : public netlist_base_factory_truthtable_t
{
@ -293,6 +468,8 @@ void tt_factory_create(setup_t &setup, tt_desc &desc, const pstring &sourcefile)
ENTRY(8, sourcefile);
ENTRY(9, sourcefile);
ENTRY(10, sourcefile);
ENTRY(11, sourcefile);
ENTRY(12, sourcefile);
default:
pstring msg = plib::pfmt("unable to create truthtable<{1},{2}>")(desc.ni)(desc.no);
nl_assert_always(false, msg);

160
src/lib/netlist/devices/nlid_truthtable.h
View File

@ -31,6 +31,7 @@ namespace netlist
{
namespace devices
{
template<unsigned bits>
struct need_bytes_for_bits
{
@ -38,7 +39,7 @@ namespace netlist
bits <= 8 ? 1 :
bits <= 16 ? 2 :
bits <= 32 ? 4 :
8
8
};
};
@ -48,91 +49,6 @@ namespace netlist
template<> struct uint_for_size<4> { typedef uint_least32_t type; };
template<> struct uint_for_size<8> { typedef uint_least64_t type; };
struct packed_int
{
template<typename C>
packed_int(C *data)
: m_data(data)
, m_size(sizeof(C))
{}
void set(const size_t pos, const uint_least64_t val)
{
switch (m_size)
{
case 1: static_cast<uint_least8_t *>(m_data)[pos] = static_cast<uint_least8_t>(val); break;
case 2: static_cast<uint_least16_t *>(m_data)[pos] = static_cast<uint_least16_t>(val); break;
case 4: static_cast<uint_least32_t *>(m_data)[pos] = static_cast<uint_least32_t>(val); break;
case 8: static_cast<uint_least64_t *>(m_data)[pos] = static_cast<uint_least64_t>(val); break;
default: { }
}
}
uint_least64_t operator[] (size_t pos) const
{
switch (m_size)
{
case 1: return static_cast<uint_least8_t *>(m_data)[pos]; break;
case 2: return static_cast<uint_least16_t *>(m_data)[pos]; break;
case 4: return static_cast<uint_least32_t *>(m_data)[pos]; break;
case 8: return static_cast<uint_least64_t *>(m_data)[pos]; break;
default:
return 0; //should never happen
}
}
uint_least64_t adjust(uint_least64_t val) const
{
switch (m_size)
{
case 1: return static_cast<uint_least8_t >(val); break;
case 2: return static_cast<uint_least16_t>(val); break;
case 4: return static_cast<uint_least32_t>(val); break;
case 8: return static_cast<uint_least64_t>(val); break;
default:
return 0; //should never happen
}
}
private:
void *m_data;
size_t m_size;
};
struct truthtable_desc_t
{
truthtable_desc_t(unsigned NO, unsigned NI, bool *initialized,
packed_int outs, uint_least8_t *timing, netlist_time *timing_nt)
: m_NO(NO), m_NI(NI), m_initialized(initialized),
m_outs(outs), m_timing(timing), m_timing_nt(timing_nt),
m_num_bits(m_NI),
m_size(1 << (m_num_bits))
{
}
void setup(const std::vector<pstring> &desc, uint_least64_t disabled_ignore);
private:
void help(unsigned cur, std::vector<pstring> list,
uint_least64_t state, uint_least64_t val, std::vector<uint_least8_t> &timing_index);
static unsigned count_bits(uint_least64_t v);
static uint_least64_t set_bits(uint_least64_t v, uint_least64_t b);
uint_least64_t get_ignored_simple(uint_least64_t i);
uint_least64_t get_ignored_extended(uint_least64_t i);
unsigned m_NO;
unsigned m_NI;
bool *m_initialized;
packed_int m_outs;
uint_least8_t *m_timing;
netlist_time *m_timing_nt;
/* additional values */
const std::size_t m_num_bits;
const std::size_t m_size;
};
template<unsigned m_NI, unsigned m_NO>
NETLIB_OBJECT(truthtable_t)
{
@ -156,20 +72,7 @@ namespace netlist
template <class C>
nld_truthtable_t(C &owner, const pstring &name, const logic_family_desc_t *fam,
truthtable_t *ttp, const pstring *desc)
: device_t(owner, name)
, m_fam(*this, fam)
, m_ign(*this, "m_ign", 0)
, m_active(*this, "m_active", 1)
, m_ttp(ttp)
{
while (*desc != "" )
{
m_desc.push_back(*desc);
desc++;
}
init();
}
truthtable_t *ttp, const pstring *desc);
template <class C>
nld_truthtable_t(C &owner, const pstring &name, const logic_family_desc_t *fam,
@ -184,62 +87,7 @@ namespace netlist
init();
}
void init()
{
set_hint_deactivate(true);
pstring header = m_desc[0];
std::vector<pstring> io(plib::psplit(header,"|"));
// checks
nl_assert_always(io.size() == 2, "too many '|'");
std::vector<pstring> inout(plib::psplit(io[0], ","));
nl_assert_always(inout.size() == m_num_bits, "bitcount wrong");
std::vector<pstring> out(plib::psplit(io[1], ","));
nl_assert_always(out.size() == m_NO, "output count wrong");
for (std::size_t i=0; i < m_NI; i++)
{
inout[i] = inout[i].trim();
m_I.emplace(i, *this, inout[i]);
}
for (std::size_t i=0; i < m_NO; i++)
{
out[i] = out[i].trim();
m_Q.emplace(i, *this, out[i]);
}
// Connect output "Q" to input "_Q" if this exists
// This enables timed state without having explicit state ....
uint_least64_t disabled_ignore = 0;
for (std::size_t i=0; i < m_NO; i++)
{
pstring tmp = "_" + out[i];
const std::size_t idx = plib::container::indexof(inout, tmp);
if (idx != plib::container::npos)
{
connect(m_Q[i], m_I[idx]);
// disable ignore for this inputs altogether.
// FIXME: This shouldn't be necessary
disabled_ignore |= (1<<idx);
}
}
m_ign = 0;
truthtable_desc_t desc(m_NO, m_NI, &m_ttp->m_initialized,
packed_int(m_ttp->m_outs),
m_ttp->m_timing, m_ttp->m_timing_nt);
desc.setup(m_desc, disabled_ignore * 0);
#if 0
printf("%s\n", name().c_str());
for (int j=0; j < m_size; j++)
printf("%05x %04x %04x %04x\n", j, m_ttp->m_outs[j] & ((1 << m_NO)-1),
m_ttp->m_outs[j] >> m_NO, m_ttp->m_timing[j * m_NO + 0]);
for (int k=0; m_ttp->m_timing_nt[k] != netlist_time::zero(); k++)
printf("%d %f\n", k, m_ttp->m_timing_nt[k].as_double() * 1000000.0);
#endif
}
void init();
NETLIB_RESETI()
{

149
src/lib/netlist/macro/nlm_ttl74xx.cpp
View File

@ -577,6 +577,111 @@ static NETLIST_START(TTL_74260_DIP)
)
NETLIST_END()
/*
* DM74279: Quad S-R Latch
*
* +---+---+---++---+
* |S1 |S2 | R || Q |
* +===+===+===++===+
* | 0 | 0 | 0 || 1 |
* | 0 | 1 | 1 || 1 |
* | 1 | 0 | 1 || 1 |
* | 1 | 1 | 0 || 0 |
* | 1 | 1 | 1 ||QP |
* +---+---+---++---+
*
* QP: Previous Q
*
* Naming conventions follow Fairchild Semiconductor datasheet
*
*/
#ifndef __PLIB_PREPROCESSOR__
#define TTL_74279A(name) \
NET_REGISTER_DEV(TTL_74279A, name)
#define TTL_74279B(name) \
NET_REGISTER_DEV(TTL_74279B, name)
#endif
static NETLIST_START(TTL_74279_DIP)
TTL_74279B(s1)
TTL_74279A(s2)
TTL_74279B(s3)
TTL_74279A(s4)
DUMMY_INPUT(GND)
DUMMY_INPUT(VCC)
DIPPINS( /* +--------------+ */
s1.R, /* 1R |1 ++ 16| VCC */ VCC.I,
s1.S1, /* 1S1 |2 15| 4S */ s4.S,
s1.S2, /* 1S2 |3 14| 4R */ s4.R,
s1.Q, /* 1Q |4 74279 13| 4Q */ s4.Q,
s2.R, /* 2R |5 12| 3S2 */ s3.S2,
s2.S, /* 2S |6 11| 3S1 */ s3.S1,
s2.Q, /* 2Q |7 10| 3R */ s3.R,
GND.I, /* GND |8 9| 3Q */ s3.Q
/* +--------------+ */
)
NETLIST_END()
/*
* DM9312: One of Eight Line Data Selectors/Multiplexers
*
* +--------------+
* D0 |1 ++ 16| VCC
* D1 |2 15| Y
* D2 |3 14| YQ
* D3 |4 9312 13| C
* D4 |5 12| B
* D5 |6 11| A
* D6 |7 10| G Strobe
* GND |8 9| D7
* +--------------+
* __
* +---+---+---+---++---+---+
* | C | B | A | G || Y | YQ|
* +===+===+===+===++===+===+
* | X | X | X | 1 || 0| 1 |
* | 0 | 0 | 0 | 0 || D0|D0Q|
* | 0 | 0 | 1 | 0 || D1|D1Q|
* | 0 | 1 | 0 | 0 || D2|D2Q|
* | 0 | 1 | 1 | 0 || D3|D3Q|
* | 1 | 0 | 0 | 0 || D4|D4Q|
* | 1 | 0 | 1 | 0 || D5|D5Q|
* | 1 | 1 | 0 | 0 || D6|D6Q|
* | 1 | 1 | 1 | 0 || D7|D7Q|
* +---+---+---+---++---+---+
*
* Naming conventions follow National Semiconductor datasheet
*
*/
#ifndef __PLIB_PREPROCESSOR__
#define DM9312_TT(name) \
NET_REGISTER_DEV(DM9312_TT, name)
#endif
static NETLIST_START(DM9312_DIP)
DM9312_TT(s)
DUMMY_INPUT(GND)
DUMMY_INPUT(VCC)
DIPPINS( /* +--------------+ */
s.D0, /* D0 |1 ++ 16| VCC */ VCC.I,
s.D1, /* D1 |2 15| Y */ s.Y,
s.D2, /* D2 |3 14| YQ */ s.YQ,
s.D3, /* D3 |4 9312 13| C */ s.C,
s.D4, /* D4 |5 12| B */ s.B,
s.D5, /* D5 |6 11| A */ s.A,
s.D6, /* D6 |7 10| G */ s.G, //Strobe
GND.I, /* GND |8 9| D7 */ s.D7
/* +--------------+ */
)
NETLIST_END()
NETLIST_START(TTL74XX_lib)
TRUTHTABLE_START(TTL_7400_GATE, 2, 1, "")
@ -847,6 +952,48 @@ NETLIST_START(TTL74XX_lib)
TT_FAMILY("74XX")
TRUTHTABLE_END()
// FIXME: We need "private" devices
TRUTHTABLE_START(TTL_74279A, 3, 1, "")
TT_HEAD("S,R,_Q|Q")
TT_LINE("0,X,X|1|22")
TT_LINE("1,0,X|0|27")
TT_LINE("1,1,0|0|27")
TT_LINE("1,1,1|1|22")
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_74279B, 4, 1, "")
TT_HEAD("S1,S2,R,_Q|Q")
TT_LINE("0,X,X,X|1|22")
TT_LINE("X,0,X,X|1|22")
TT_LINE("1,1,0,X|0|27")
TT_LINE("1,1,1,0|0|27")
TT_LINE("1,1,1,1|1|22")
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(DM9312_TT, 12, 2, "+A,+B,+C,+G,+D0,+D1,+D2,+D3,+D4,+D5,+D6,+D7")
TT_HEAD(" C, B, A, G,D0,D1,D2,D3,D4,D5,D6,D7| Y,YQ")
TT_LINE(" X, X, X, 1, X, X, X, X, X, X, X, X| 0, 1|33,19")
TT_LINE(" 0, 0, 0, 0, 0, X, X, X, X, X, X, X| 0, 1|33,28")
TT_LINE(" 0, 0, 0, 0, 1, X, X, X, X, X, X, X| 1, 0|33,28")
TT_LINE(" 0, 0, 1, 0, X, 0, X, X, X, X, X, X| 0, 1|33,28")
TT_LINE(" 0, 0, 1, 0, X, 1, X, X, X, X, X, X| 1, 0|33,28")
TT_LINE(" 0, 1, 0, 0, X, X, 0, X, X, X, X, X| 0, 1|33,28")
TT_LINE(" 0, 1, 0, 0, X, X, 1, X, X, X, X, X| 1, 0|33,28")
TT_LINE(" 0, 1, 1, 0, X, X, X, 0, X, X, X, X| 0, 1|33,28")
TT_LINE(" 0, 1, 1, 0, X, X, X, 1, X, X, X, X| 1, 0|33,28")
TT_LINE(" 1, 0, 0, 0, X, X, X, X, 0, X, X, X| 0, 1|33,28")
TT_LINE(" 1, 0, 0, 0, X, X, X, X, 1, X, X, X| 1, 0|33,28")
TT_LINE(" 1, 0, 1, 0, X, X, X, X, X, 0, X, X| 0, 1|33,28")
TT_LINE(" 1, 0, 1, 0, X, X, X, X, X, 1, X, X| 1, 0|33,28")
TT_LINE(" 1, 1, 0, 0, X, X, X, X, X, X, 0, X| 0, 1|33,28")
TT_LINE(" 1, 1, 0, 0, X, X, X, X, X, X, 1, X| 1, 0|33,28")
TT_LINE(" 1, 1, 1, 0, X, X, X, X, X, X, X, 0| 0, 1|33,28")
TT_LINE(" 1, 1, 1, 0, X, X, X, X, X, X, X, 1| 1, 0|33,28")
TT_FAMILY("74XX")
TRUTHTABLE_END()
LOCAL_LIB_ENTRY(TTL_7400_DIP)
LOCAL_LIB_ENTRY(TTL_7402_DIP)
LOCAL_LIB_ENTRY(TTL_7404_DIP)
@ -862,4 +1009,6 @@ NETLIST_START(TTL74XX_lib)
LOCAL_LIB_ENTRY(TTL_7437_DIP)
LOCAL_LIB_ENTRY(TTL_7486_DIP)
LOCAL_LIB_ENTRY(TTL_74260_DIP)
LOCAL_LIB_ENTRY(TTL_74279_DIP)
LOCAL_LIB_ENTRY(DM9312_DIP)
NETLIST_END()

98
src/lib/netlist/macro/nlm_ttl74xx.h
View File

@ -36,7 +36,6 @@
#define TTL_7402_DIP(name) \
NET_REGISTER_DEV(TTL_7402_DIP, name)
#define TTL_7404_GATE(name) \
NET_REGISTER_DEV(TTL_7404_GATE, name)
@ -103,88 +102,88 @@
NET_CONNECT(name, C, cI3) \
NET_CONNECT(name, D, cI4)
#define TTL_7420_DIP(name) \
#define TTL_7420_DIP(name) \
NET_REGISTER_DEV(TTL_7420_DIP, name)
#define TTL_7425_GATE(name) \
#define TTL_7425_GATE(name) \
NET_REGISTER_DEV(TTL_7425_GATE, name)
#define TTL_7425_NOR(name, cI1, cI2, cI3, cI4) \
NET_REGISTER_DEV(TTL_7425_NOR, name) \
NET_CONNECT(name, A, cI1) \
NET_CONNECT(name, B, cI2) \
NET_CONNECT(name, C, cI3) \
#define TTL_7425_NOR(name, cI1, cI2, cI3, cI4) \
NET_REGISTER_DEV(TTL_7425_NOR, name) \
NET_CONNECT(name, A, cI1) \
NET_CONNECT(name, B, cI2) \
NET_CONNECT(name, C, cI3) \
NET_CONNECT(name, D, cI4)
#define TTL_7425_DIP(name) \
#define TTL_7425_DIP(name) \
NET_REGISTER_DEV(TTL_7425_DIP, name)
#define TTL_7427_GATE(name) \
#define TTL_7427_GATE(name) \
NET_REGISTER_DEV(TTL_7427_GATE, name)
#define TTL_7427_NOR(name, cI1, cI2, cI3) \
NET_REGISTER_DEV(TTL_7427_NOR, name) \
NET_CONNECT(name, A, cI1) \
NET_CONNECT(name, B, cI2) \
#define TTL_7427_NOR(name, cI1, cI2, cI3) \
NET_REGISTER_DEV(TTL_7427_NOR, name) \
NET_CONNECT(name, A, cI1) \
NET_CONNECT(name, B, cI2) \
NET_CONNECT(name, C, cI3)
#define TTL_7427_DIP(name) \
#define TTL_7427_DIP(name) \
NET_REGISTER_DEV(TTL_7427_DIP, name)
#define TTL_7430_GATE(name) \
#define TTL_7430_GATE(name) \
NET_REGISTER_DEV(TTL_7430_GATE, name)
#define TTL_7430_NAND(name, cI1, cI2, cI3, cI4, cI5, cI6, cI7, cI8) \
NET_REGISTER_DEV(TTL_7430_NAND, name) \
NET_CONNECT(name, A, cI1) \
NET_CONNECT(name, B, cI2) \
NET_CONNECT(name, C, cI3) \
NET_CONNECT(name, D, cI4) \
NET_CONNECT(name, E, cI5) \
NET_CONNECT(name, F, cI6) \
NET_CONNECT(name, G, cI7) \
#define TTL_7430_NAND(name, cI1, cI2, cI3, cI4, cI5, cI6, cI7, cI8) \
NET_REGISTER_DEV(TTL_7430_NAND, name) \
NET_CONNECT(name, A, cI1) \
NET_CONNECT(name, B, cI2) \
NET_CONNECT(name, C, cI3) \
NET_CONNECT(name, D, cI4) \
NET_CONNECT(name, E, cI5) \
NET_CONNECT(name, F, cI6) \
NET_CONNECT(name, G, cI7) \
NET_CONNECT(name, H, cI8)
#define TTL_7430_DIP(name) \
#define TTL_7430_DIP(name) \
NET_REGISTER_DEV(TTL_7430_DIP, name)
#define TTL_7432_GATE(name) \
#define TTL_7432_GATE(name) \
NET_REGISTER_DEV(TTL_7432_OR, name)
#define TTL_7432_OR(name, cI1, cI2) \
NET_REGISTER_DEV(TTL_7432_OR, name) \
NET_CONNECT(name, A, cI1) \
#define TTL_7432_OR(name, cI1, cI2) \
NET_REGISTER_DEV(TTL_7432_OR, name) \
NET_CONNECT(name, A, cI1) \
NET_CONNECT(name, B, cI2)
#define TTL_7432_DIP(name) \
#define TTL_7432_DIP(name) \
NET_REGISTER_DEV(TTL_7432_DIP, name)
#define TTL_7437_GATE(name) \
#define TTL_7437_GATE(name) \
NET_REGISTER_DEV(TTL_7437_GATE, name)
#define TTL_7437_NAND(name, cA, cB) \
#define TTL_7437_NAND(name, cA, cB) \
NET_REGISTER_DEV(TTL_7437_NAND, name) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB)
#define TTL_7437_DIP(name) \
#define TTL_7437_DIP(name) \
NET_REGISTER_DEV(TTL_7437_DIP, name)
#define TTL_7486_GATE(name) \
#define TTL_7486_GATE(name) \
NET_REGISTER_DEV(TTL_7486_GATE, name)
#define TTL_7486_XOR(name, cA, cB) \
NET_REGISTER_DEV(TTL_7486_XOR, name) \
NET_CONNECT(name, A, cA) \
#define TTL_7486_XOR(name, cA, cB) \
NET_REGISTER_DEV(TTL_7486_XOR, name) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB)
#define TTL_7486_DIP(name) \
#define TTL_7486_DIP(name) \
NET_REGISTER_DEV(TTL_7486_DIP, name)
@ -202,6 +201,27 @@
#define TTL_74260_DIP(name) \
NET_REGISTER_DEV(TTL_74260_DIP, name)
#define TTL_74279_DIP(name) \
NET_REGISTER_DEV(TTL_74279_DIP, name)
#define DM9312(name, cA, cB, cC, cSTROBE, cD0, cD1, cD2, cD3, cD4, cD5, cD6, cD7) \
NET_REGISTER_DEV(DM9312_TT, name) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, G, cSTROBE) \
NET_CONNECT(name, D0, cD0) \
NET_CONNECT(name, D1, cD1) \
NET_CONNECT(name, D2, cD2) \
NET_CONNECT(name, D3, cD3) \
NET_CONNECT(name, D4, cD4) \
NET_CONNECT(name, D5, cD5) \
NET_CONNECT(name, D6, cD6) \
NET_CONNECT(name, D7, cD7)
#define DM9312_DIP(name) \
NET_REGISTER_DEV(DM9312_DIP, name)
#endif
/* ----------------------------------------------------------------------------

4
src/lib/netlist/plib/pstream.cpp
View File

@ -277,7 +277,7 @@ pimemstream::pos_type pimemstream::vread(void *buf, const pos_type n)
if (ret > 0)
{
std::copy(m_mem + m_pos, m_mem + m_pos + ret, (char *) buf);
std::copy(m_mem + m_pos, m_mem + m_pos + ret, static_cast<char *>(buf));
m_pos += ret;
}
@ -334,7 +334,7 @@ void pomemstream::vwrite(const void *buf, const pos_type n)
pfree_array(o);
}
std::copy((char *) buf, (char *) buf + n, m_mem + m_pos);
std::copy(static_cast<const char *>(buf), static_cast<const char *>(buf) + n, m_mem + m_pos);
m_pos += n;
m_size = std::max(m_pos, m_size);
}

2
src/lib/netlist/plib/pstream.h
View File

@ -78,7 +78,7 @@ public:
bool eof() const { return ((flags() & FLAG_EOF) != 0); }
pos_type read(void *buf, const unsigned n)
pos_type read(void *buf, const pos_type n)
{
return vread(buf, n);
}

8
src/lib/netlist/plib/pstring.cpp
View File

@ -80,7 +80,7 @@ int pstring_t<F>::pcmp(const pstring_t &right) const
ri++;
si++;
}
int ret = (si == this->end() ? 0 : *si - *ri);
int ret = (si == this->end() ? 0 : static_cast<int>(*si) - static_cast<int>(*ri));
if (ret == 0)
{
if (this->blen() > right.blen())
@ -97,8 +97,8 @@ void pstring_t<F>::pcopy(const mem_t *from, std::size_t size)
{
pstr_t *n = salloc(size * sizeof(mem_t));
if (size > 0)
n->copy_from((char *)from, size);
*((mem_t *) n->str() + size) = 0;
n->copy_from(static_cast<const char *>(from), size);
*(static_cast<mem_t *>(n->str()) + size) = 0;
sfree(m_ptr);
m_ptr = n;
}
@ -357,7 +357,7 @@ void pstringbuffer::pcat(const void *m, std::size_t l)
{
const std::size_t nl = m_len + l + 1;
resize(nl);
std::copy((char *) m, (char *) m + l, m_ptr + m_len);
std::copy(static_cast<const char *>(m), static_cast<const char *>(m) + l, m_ptr + m_len);
m_len += l;
*(m_ptr + m_len) = 0;
}

2
src/lib/netlist/plib/pstring.h
View File

@ -31,7 +31,7 @@ struct pstr_t
std::size_t len() const { return m_len; }
void inc() { m_ref_count++; }
bool dec_and_check() { --m_ref_count; return m_ref_count == 0; }
void copy_from(char *p, std::size_t n) { std::copy(p, p + n, str()); }
void copy_from(const char *p, std::size_t n) { std::copy(p, p + n, str()); }
private:
int m_ref_count;
std::size_t m_len;

5
src/lib/netlist/prg/nltool.cpp
View File

@ -197,7 +197,8 @@ public:
{
std::size_t sz = s->m_dt.size * s->m_count;
if (s->m_dt.is_float || s->m_dt.is_integral)
std::copy((char *)s->m_ptr, (char *) s->m_ptr + sz, p);
std::copy(static_cast<char *>(s->m_ptr),
static_cast<char *>(s->m_ptr) + sz, p);
else
log().fatal("found unsupported save element {1}\n", s->m_name);
p += sz;
@ -220,7 +221,7 @@ public:
{
std::size_t sz = s->m_dt.size * s->m_count;
if (s->m_dt.is_float || s->m_dt.is_integral)
std::copy(p, p + sz, (char *) s->m_ptr);
std::copy(p, p + sz, static_cast<char *>(s->m_ptr));
else
log().fatal("found unsupported save element {1}\n", s->m_name);
p += sz;

12
src/mame/machine/nl_breakout.cpp
View File

@ -272,7 +272,7 @@ CIRCUIT_LAYOUT( breakout )
CHIP("H2", 7408)
CHIP("H3", 7427)
CHIP("H4", 7400)
CHIP("H5", 9312)
DM9312_DIP(H5)
CHIP("H6", 9310)
CHIP("H7", 7408) //sometimes looks like N7 on schematic
//PARAM(H7.USE_DEACTIVATE, 0)
@ -282,7 +282,7 @@ CIRCUIT_LAYOUT( breakout )
CHIP("J1", 74175)
CHIP("J2", 7404)
CHIP("J3", 7402)
CHIP("J4", 9312)
DM9312_DIP(J4)
CHIP("J5", 7448)
#if USE_TRUTHTABLE_7448
PARAM(J5.USE_DEACTIVATE, 0) // only use this if compiled with 7448 as a truthtable
@ -296,7 +296,7 @@ CIRCUIT_LAYOUT( breakout )
CHIP("K2", 7486)
CHIP("K3", 7430)
CHIP("K4", 7408)
CHIP("K5", 9312)
DM9312_DIP(K5)
CHIP("K6", 9310)
CHIP("K7", 7486)
CHIP("K8", 7474) //TODO: one more than bom?
@ -306,7 +306,7 @@ CIRCUIT_LAYOUT( breakout )
CHIP("L2", 7486)
CHIP("L3", 82S16) //RAM
CHIP("L4", 7411)
CHIP("L5", 9312)
DM9312_DIP(L5)
CHIP("L6", 9310)
CHIP("L7", 7486)
CHIP("L8", 74193)
@ -316,7 +316,7 @@ CIRCUIT_LAYOUT( breakout )
CHIP("M2", 7483)
CHIP("M3", 7486)
CHIP("M4", 7410)
CHIP("M5", 9312)
DM9312_DIP(M5)
CHIP("M6", 9310)
CHIP("M8", 7427)
CHIP("M9", 7404)
@ -325,7 +325,7 @@ CIRCUIT_LAYOUT( breakout )
CHIP("N2", 7483)
CHIP("N3", 7486)
CHIP("N4", 7411)
CHIP("N5", 9312)
DM9312_DIP(N5)
CHIP("N6", 9310)
CHIP("N7", 7408) //sometimes looks like H7 on schematic
CHIP_9602_Mono(N8, &n8_desc)

4
src/mame/machine/nl_stuntcyc.cpp
View File

@ -436,8 +436,8 @@ NETLIST_START(stuntcyc)
TTL_9322(C7, 16H, S5, S1, S6, S2, GROUND, S4, GROUND, S3, GROUND)
TTL_7448(C6, C7.Y1, C7.Y2, C7.Y4, C7.Y3, P, SCORE_WINDOW, 16H)
TTL_9312(B6, 2H, 4H, 8H, C6.f, GROUND, GROUND, C6.b, C6.e, GROUND, GROUND, C6.c, 8H)
TTL_9312(A6, 2V, 4V, 8V, C6.a, GROUND, GROUND, C6.g, GROUND, GROUND, GROUND, C6.d, 8H)
DM9312(B6, 2H, 4H, 8H, 8H, C6.f, GROUND, GROUND, C6.b, C6.e, GROUND, GROUND, C6.c)
DM9312(A6, 2V, 4V, 8V, 8H, C6.a, GROUND, GROUND, C6.g, GROUND, GROUND, GROUND, C6.d)
TTL_7408_AND(B5_4, A6.YQ, B6.YQ)
TTL_7474(A5_1, CLOCK, B5_4.Q, P, P)
ALIAS(COMP_SCORE_Q, A5_1.Q)