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dsp56k : Hooked up new execution engine. [Andrew Gardner]

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This commit is contained in:
Andrew Gardner 2010-08-07 18:42:59 +00:00
parent e87dfd57bf
commit 0946c173cb
15 changed files with 1221 additions and 1102 deletions
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2
.gitattributes vendored
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@ -92,8 +92,10 @@ src/emu/cpu/dsp56k/dsp56dsm.c svneol=native#text/plain
src/emu/cpu/dsp56k/dsp56k.c svneol=native#text/plain src/emu/cpu/dsp56k/dsp56k.c svneol=native#text/plain
src/emu/cpu/dsp56k/dsp56k.h svneol=native#text/plain src/emu/cpu/dsp56k/dsp56k.h svneol=native#text/plain
src/emu/cpu/dsp56k/dsp56mem.c svneol=native#text/plain src/emu/cpu/dsp56k/dsp56mem.c svneol=native#text/plain
src/emu/cpu/dsp56k/dsp56mem.h svneol=native#text/plain
src/emu/cpu/dsp56k/dsp56ops.c svneol=native#text/plain src/emu/cpu/dsp56k/dsp56ops.c svneol=native#text/plain
src/emu/cpu/dsp56k/dsp56pcu.c svneol=native#text/plain src/emu/cpu/dsp56k/dsp56pcu.c svneol=native#text/plain
src/emu/cpu/dsp56k/dsp56pcu.h svneol=native#text/plain
src/emu/cpu/dsp56k/inst.c svneol=native#text/plain src/emu/cpu/dsp56k/inst.c svneol=native#text/plain
src/emu/cpu/dsp56k/inst.h svneol=native#text/plain src/emu/cpu/dsp56k/inst.h svneol=native#text/plain
src/emu/cpu/dsp56k/opcode.c svneol=native#text/plain src/emu/cpu/dsp56k/opcode.c svneol=native#text/plain

27
src/emu/cpu/cpu.mak
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@ -1053,6 +1053,8 @@ $(CPUOBJ)/m68000/m68kcpu.o: $(CPUOBJ)/m68000/m68kops.c \
ifneq ($(filter DSP56156,$(CPUS)),) ifneq ($(filter DSP56156,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/dsp56k OBJDIRS += $(CPUOBJ)/dsp56k
CPUOBJS += $(CPUOBJ)/dsp56k/dsp56k.o CPUOBJS += $(CPUOBJ)/dsp56k/dsp56k.o
CPUOBJS += $(CPUOBJ)/dsp56k/dsp56mem.o
CPUOBJS += $(CPUOBJ)/dsp56k/dsp56pcu.o
DASMOBJS += $(CPUOBJ)/dsp56k/dsp56dsm.o DASMOBJS += $(CPUOBJ)/dsp56k/dsp56dsm.o
DASMOBJS += $(CPUOBJ)/dsp56k/opcode.o DASMOBJS += $(CPUOBJ)/dsp56k/opcode.o
DASMOBJS += $(CPUOBJ)/dsp56k/inst.o DASMOBJS += $(CPUOBJ)/dsp56k/inst.o
@ -1060,16 +1062,27 @@ DASMOBJS += $(CPUOBJ)/dsp56k/pmove.o
DASMOBJS += $(CPUOBJ)/dsp56k/tables.o DASMOBJS += $(CPUOBJ)/dsp56k/tables.o
endif endif
$(CPUOBJ)/dsp56k/dsp56mem.o: $(CPUSRC)/dsp56k/dsp56mem.c \
$(CPUSRC)/dsp56k/dsp56mem.h
$(CPUOBJ)/dsp56k/dsp56pcu.o: $(CPUSRC)/dsp56k/dsp56pcu.c \
$(CPUSRC)/dsp56k/dsp56pcu.h
$(CPUOBJ)/dsp56k/dsp56k.o: $(CPUSRC)/dsp56k/dsp56k.c \ $(CPUOBJ)/dsp56k/dsp56k.o: $(CPUSRC)/dsp56k/dsp56k.c \
$(CPUSRC)/dsp56k/opcode.c \
$(CPUSRC)/dsp56k/inst.c \
$(CPUSRC)/dsp56k/pmove.c \
$(CPUSRC)/dsp56k/tables.c \
$(CPUSRC)/dsp56k/dsp56ops.c \
$(CPUSRC)/dsp56k/dsp56mem.c \
$(CPUSRC)/dsp56k/dsp56pcu.c \
$(CPUSRC)/dsp56k/dsp56k.h $(CPUSRC)/dsp56k/dsp56k.h
$(CPUOBJ)/dsp56k/opcode.o: $(CPUSRC)/dsp56k/opcode.c \
$(CPUSRC)/dsp56k/opcode.h
$(CPUOBJ)/dsp56k/inst.o: $(CPUSRC)/dsp56k/inst.c \
$(CPUSRC)/dsp56k/inst.h
$(CPUOBJ)/dsp56k/pmove.o: $(CPUSRC)/dsp56k/pmove.c \
$(CPUSRC)/dsp56k/pmove.h
$(CPUOBJ)/dsp56k/tables.o: $(CPUSRC)/dsp56k/tables.c \
$(CPUSRC)/dsp56k/tables.h
$(CPUOBJ)/dsp56k/dsp56dsm.o: $(CPUSRC)/dsp56k/opcode.c \ $(CPUOBJ)/dsp56k/dsp56dsm.o: $(CPUSRC)/dsp56k/opcode.c \
$(CPUSRC)/dsp56k/opcode.h \ $(CPUSRC)/dsp56k/opcode.h \
$(CPUSRC)/dsp56k/inst.c \ $(CPUSRC)/dsp56k/inst.c \

385
src/emu/cpu/dsp56k/dsp56def.h
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@ -2,6 +2,14 @@
// All the macros that are fit to print. // // All the macros that are fit to print. //
/////////////////////////////////////////// ///////////////////////////////////////////
#ifndef __DSP56_DEF_H__
#define __DSP56_DEF_H__
#include "dsp56k.h"
namespace DSP56K
{
/*************************************************************************** /***************************************************************************
ALU ALU
***************************************************************************/ ***************************************************************************/
@ -42,379 +50,6 @@
#define TEMP cpustate->AGU.temp #define TEMP cpustate->AGU.temp
} // namespace DSP56K
/*************************************************************************** #endif
PCU
***************************************************************************/
static void pcu_reset(dsp56k_core* cpustate);
#define PC (cpustate->PCU.pc)
#define LA (cpustate->PCU.la)
#define LC (cpustate->PCU.lc)
#define SR (cpustate->PCU.sr)
#define OMR (cpustate->PCU.omr)
#define SP (cpustate->PCU.sp)
#define SS (cpustate->PCU.ss)
#define SSH (SS[SP].w.h)
#define SSL (SS[SP].w.l)
#define ST0 (SS[0].d)
#define ST1 (SS[1].d)
#define ST2 (SS[2].d)
#define ST3 (SS[3].d)
#define ST4 (SS[4].d)
#define ST5 (SS[5].d)
#define ST6 (SS[6].d)
#define ST7 (SS[7].d)
#define ST8 (SS[8].d)
#define ST9 (SS[9].d)
#define ST10 (SS[10].d)
#define ST11 (SS[11].d)
#define ST12 (SS[12].d)
#define ST13 (SS[13].d)
#define ST14 (SS[14].d)
#define ST15 (SS[15].d)
/* STATUS REGISTER (SR) BITS (1-25) */
/* MR */
static UINT8 LF_bit(dsp56k_core* cpustate);
static UINT8 FV_bit(dsp56k_core* cpustate);
//static UINT8 S_bits(dsp56k_core* cpustate);
static UINT8 I_bits(dsp56k_core* cpustate);
/* CCR - with macros for easy access */
#define S() (S_bit(cpustate))
static UINT8 S_bit(dsp56k_core* cpustate);
#define L() (L_bit(cpustate))
static UINT8 L_bit(dsp56k_core* cpustate);
#define E() (E_bit(cpustate))
static UINT8 E_bit(dsp56k_core* cpustate);
#define U() (U_bit(cpustate))
static UINT8 U_bit(dsp56k_core* cpustate);
#define N() (N_bit(cpustate))
static UINT8 N_bit(dsp56k_core* cpustate);
#define Z() (Z_bit(cpustate))
static UINT8 Z_bit(dsp56k_core* cpustate);
#define V() (V_bit(cpustate))
static UINT8 V_bit(dsp56k_core* cpustate);
#define C() (C_bit(cpustate))
static UINT8 C_bit(dsp56k_core* cpustate);
/* MR setters */
static void LF_bit_set(dsp56k_core* cpustate, UINT8 value);
static void FV_bit_set(dsp56k_core* cpustate, UINT8 value);
static void S_bits_set(dsp56k_core* cpustate, UINT8 value);
static void I_bits_set(dsp56k_core* cpustate, UINT8 value);
/* CCR setters - with macros for easy access */
#define DSP56K_S_SET() (S_bit_set(cpustate, 1))
#define DSP56K_S_CLEAR() (S_bit_set(cpustate, 0))
static void S_bit_set(dsp56k_core* cpustate, UINT8 value);
#define DSP56K_L_SET() (L_bit_set(cpustate, 1))
#define DSP56K_L_CLEAR() (L_bit_set(cpustate, 0))
static void L_bit_set(dsp56k_core* cpustate, UINT8 value);
#define DSP56K_E_SET() (E_bit_set(cpustate, 1))
#define DSP56K_E_CLEAR() (E_bit_set(cpustate, 0))
static void E_bit_set(dsp56k_core* cpustate, UINT8 value);
#define DSP56K_U_SET() (U_bit_set(cpustate, 1))
#define DSP56K_U_CLEAR() (U_bit_set(cpustate, 0))
static void U_bit_set(dsp56k_core* cpustate, UINT8 value);
#define DSP56K_N_SET() (N_bit_set(cpustate, 1))
#define DSP56K_N_CLEAR() (N_bit_set(cpustate, 0))
static void N_bit_set(dsp56k_core* cpustate, UINT8 value);
#define DSP56K_Z_SET() (Z_bit_set(cpustate, 1))
#define DSP56K_Z_CLEAR() (Z_bit_set(cpustate, 0))
static void Z_bit_set(dsp56k_core* cpustate, UINT8 value);
#define DSP56K_V_SET() (V_bit_set(cpustate, 1))
#define DSP56K_V_CLEAR() (V_bit_set(cpustate, 0))
static void V_bit_set(dsp56k_core* cpustate, UINT8 value);
#define DSP56K_C_SET() (C_bit_set(cpustate, 1))
#define DSP56K_C_CLEAR() (C_bit_set(cpustate, 0))
static void C_bit_set(dsp56k_core* cpustate, UINT8 value);
// TODO: Maybe some functions for Interrupt Mask and Scaling Mode go here?
/* 1-28 OPERATING MODE REGISTER (OMR) BITS */
//static UINT8 CD_bit(dsp56k_core* cpustate);
//static UINT8 SD_bit(dsp56k_core* cpustate);
//static UINT8 R_bit(dsp56k_core* cpustate);
//static UINT8 SA_bit(dsp56k_core* cpustate);
//static UINT8 MC_bit(dsp56k_core* cpustate);
static UINT8 MB_bit(dsp56k_core* cpustate);
static UINT8 MA_bit(dsp56k_core* cpustate);
static void CD_bit_set(dsp56k_core* cpustate, UINT8 value);
static void SD_bit_set(dsp56k_core* cpustate, UINT8 value);
static void R_bit_set(dsp56k_core* cpustate, UINT8 value);
static void SA_bit_set(dsp56k_core* cpustate, UINT8 value);
static void MC_bit_set(dsp56k_core* cpustate, UINT8 value);
static void MB_bit_set(dsp56k_core* cpustate, UINT8 value);
static void MA_bit_set(dsp56k_core* cpustate, UINT8 value);
/* 1-27 STACK POINTER (SP) BITS */
static UINT8 UF_bit(dsp56k_core* cpustate);
static UINT8 SE_bit(dsp56k_core* cpustate);
//static void UF_bit_set(dsp56k_core* cpustate, UINT8 value) {};
//static void SE_bit_set(dsp56k_core* cpustate, UINT8 value) {};
// HACK - Bootstrap modes
#define BOOTSTRAP_OFF (0)
#define BOOTSTRAP_SSIX (1)
#define BOOTSTRAP_HI (2)
/* PCU IRQ goodies */
static void pcu_service_interrupts(dsp56k_core* cpustate);
static void dsp56k_irq_table_init(void);
static void dsp56k_set_irq_source(UINT8 irq_num, UINT16 iv, const char* source);
static int dsp56k_get_irq_index_by_tag(const char* tag);
static void dsp56k_add_pending_interrupt(dsp56k_core* cpustate, const char* name); // Call me to add an interrupt to the queue
static void dsp56k_clear_pending_interrupts(dsp56k_core* cpustate);
static int dsp56k_count_pending_interrupts(dsp56k_core* cpustate);
static void dsp56k_sort_pending_interrupts(dsp56k_core* cpustate, int num);
static INT8 dsp56k_get_irq_priority(dsp56k_core* cpustate, int index);
/***************************************************************************
MEMORY
***************************************************************************/
// Adjusts the documented address to match the offset in peripheral RAM
#define A2O(a) (a-0xffc0)
// Adjusts the offset in peripheral RAM to match the documented address
#define O2A(a) (a+0xffc0)
// The memory 'registers'
#define PBC (dsp56k_peripheral_ram[A2O(0xffc0)])
#define PCC (dsp56k_peripheral_ram[A2O(0xffc1)])
#define PBDDR (dsp56k_peripheral_ram[A2O(0xffc2)])
#define PCDDR (dsp56k_peripheral_ram[A2O(0xffc3)])
#define HCR (dsp56k_peripheral_ram[A2O(0xffc4)])
#define COCR (dsp56k_peripheral_ram[A2O(0xffc8)])
#define CRASSI0 (dsp56k_peripheral_ram[A2O(0xffd0)])
#define CRBSSI0 (dsp56k_peripheral_ram[A2O(0xffd1)])
#define CRASSI1 (dsp56k_peripheral_ram[A2O(0xffd8)])
#define CRBSSI1 (dsp56k_peripheral_ram[A2O(0xffd9)])
#define PLCR (dsp56k_peripheral_ram[A2O(0xffdc)])
#define BCR (dsp56k_peripheral_ram[A2O(0xffde)])
#define IPR (dsp56k_peripheral_ram[A2O(0xffdf)])
#define PBD (dsp56k_peripheral_ram[A2O(0xffe2)])
#define PCD (dsp56k_peripheral_ram[A2O(0xffe3)])
#define HSR (dsp56k_peripheral_ram[A2O(0xffe4)])
#define HTXHRX (dsp56k_peripheral_ram[A2O(0xffe5)])
#define COSR (dsp56k_peripheral_ram[A2O(0xffe8)])
#define CRXCTX (dsp56k_peripheral_ram[A2O(0xffe9)])
#define TCR (dsp56k_peripheral_ram[A2O(0xffec)])
#define TCTR (dsp56k_peripheral_ram[A2O(0xffed)])
#define TCPR (dsp56k_peripheral_ram[A2O(0xffee)])
#define TPR (dsp56k_peripheral_ram[A2O(0xffef)])
#define TSRSSI0 (dsp56k_peripheral_ram[A2O(0xfff0)])
#define TRXSSI0 (dsp56k_peripheral_ram[A2O(0xfff1)])
#define RSMA0 (dsp56k_peripheral_ram[A2O(0xfff2)])
#define RSMB0 (dsp56k_peripheral_ram[A2O(0xfff3)])
#define TSMA0 (dsp56k_peripheral_ram[A2O(0xfff4)])
#define TSMB0 (dsp56k_peripheral_ram[A2O(0xfff5)])
#define TSRSSI1 (dsp56k_peripheral_ram[A2O(0xfff8)])
#define TRXSSI1 (dsp56k_peripheral_ram[A2O(0xfff9)])
#define RSMA1 (dsp56k_peripheral_ram[A2O(0xfffa)])
#define RSMB1 (dsp56k_peripheral_ram[A2O(0xfffb)])
#define TSMA1 (dsp56k_peripheral_ram[A2O(0xfffc)])
#define TSMB1 (dsp56k_peripheral_ram[A2O(0xfffd)])
/* Interrupt priority register (IPR) bits */
static void IPR_set(dsp56k_core* cpustate, UINT16 value);
/* A return value of -1 means disabled */
static INT8 irqa_ipl(dsp56k_core* cpustate);
static INT8 irqb_ipl(dsp56k_core* cpustate);
static UINT8 irqa_trigger(dsp56k_core* cpustate);
static UINT8 irqb_trigger(dsp56k_core* cpustate);
static INT8 codec_ipl(dsp56k_core* cpustate);
static INT8 host_ipl(dsp56k_core* cpustate);
static INT8 ssi0_ipl(dsp56k_core* cpustate);
static INT8 ssi1_ipl(dsp56k_core* cpustate);
static INT8 tm_ipl(dsp56k_core* cpustate);
/***************************************************************************
HOST INTERFACE
***************************************************************************/
static void dsp56k_host_interface_reset(dsp56k_core* cpustate);
#define HTX (HTXHRX)
#define HRX (HTXHRX)
#define ICR (cpustate->HI.icr)
#define CVR (cpustate->HI.cvr)
#define ISR (cpustate->HI.isr)
#define IVR (cpustate->HI.ivr)
#define TXH (cpustate->HI.trxh)
#define TXL (cpustate->HI.trxl)
#define RXH (cpustate->HI.trxh)
#define RXL (cpustate->HI.trxl)
/***************/
/* DSP56k SIDE */
/***************/
/* Host Control Register (HCR) Bits */
static void HCR_set(dsp56k_core* cpustate, UINT16 value);
//static UINT16 HF3_bit(dsp56k_core* cpustate); #define hf3BIT ((HCR & 0x0010) != 0)
//static UINT16 HF2_bit(dsp56k_core* cpustate); #define hf2BIT ((HCR & 0x0008) != 0)
static UINT16 HCIE_bit(dsp56k_core* cpustate);
static UINT16 HTIE_bit(dsp56k_core* cpustate);
static UINT16 HRIE_bit(dsp56k_core* cpustate);
static void HF3_bit_set(dsp56k_core* cpustate, UINT16 value);
static void HF2_bit_set(dsp56k_core* cpustate, UINT16 value);
static void HCIE_bit_set(dsp56k_core* cpustate, UINT16 value);
static void HTIE_bit_set(dsp56k_core* cpustate, UINT16 value);
static void HRIE_bit_set(dsp56k_core* cpustate, UINT16 value);
/* Host Status Register (HSR) Bits */
//static void HSR_set(dsp56k_core* cpustate, UINT16 value);
//static UINT16 DMA_bit(dsp56k_core* cpustate); #define dmaBIT ((HSR & 0x0080) != 0)
//static UINT16 HF1_bit(dsp56k_core* cpustate); #define hf1BIT ((HSR & 0x0010) != 0)
//static UINT16 HF0_bit(dsp56k_core* cpustate); #define hf0BIT ((HSR & 0x0008) != 0)
//static UINT16 HCP_bit(dsp56k_core* cpustate); #define hcpBIT ((HSR & 0x0004) != 0)
static UINT16 HTDE_bit(dsp56k_core* cpustate);
static UINT16 HRDF_bit(dsp56k_core* cpustate);
static void DMA_bit_set(dsp56k_core* cpustate, UINT16 value);
static void HF1_bit_set(dsp56k_core* cpustate, UINT16 value);
static void HF0_bit_set(dsp56k_core* cpustate, UINT16 value);
static void HCP_bit_set(dsp56k_core* cpustate, UINT16 value);
static void HTDE_bit_set(dsp56k_core* cpustate, UINT16 value);
static void HRDF_bit_set(dsp56k_core* cpustate, UINT16 value);
/*************/
/* HOST SIDE */
/*************/
/* Interrupt Control Register (ICR) Bits */
static void ICR_set(dsp56k_core* cpustate, UINT8 value);
//static UINT8 INIT_bit(dsp56k_core* cpustate); #define x_initBIT ((dsp56k.HI.ICR & 0x0080) != 0)
//static UINT8 HM1_bit(dsp56k_core* cpustate); #define x_hm1BIT ((dsp56k.HI.ICR & 0x0040) != 0)
//static UINT8 HM0_bit(dsp56k_core* cpustate); #define x_hm0BIT ((dsp56k.HI.ICR & 0x0020) != 0)
//static UINT8 HF1_bit_host(dsp56k_core* cpustate); #define x_hf1BIT ((dsp56k.HI.ICR & 0x0010) != 0)
//static UINT8 HF0_bit_host(dsp56k_core* cpustate); #define x_hf0BIT ((dsp56k.HI.ICR & 0x0008) != 0)
//static UINT8 TREQ_bit(dsp56k_core* cpustate); #define x_treqBIT ((dsp56k.HI.ICR & 0x0002) != 0)
//static UINT8 RREQ_bit(dsp56k_core* cpustate); #define x_rreqBIT ((dsp56k.HI.ICR & 0x0001) != 0)
//static void INIT_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_initBIT() (dsp56k.HI.ICR &= (~0x0080))
//static void HM1_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hm1BIT() (dsp56k.HI.ICR &= (~0x0040))
//static void HM0_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hm0BIT() (dsp56k.HI.ICR &= (~0x0020))
static void HF1_bit_host_set(dsp56k_core* cpustate, UINT8 value);
static void HF0_bit_host_set(dsp56k_core* cpustate, UINT8 value);
static void TREQ_bit_set(dsp56k_core* cpustate, UINT8 value);
static void RREQ_bit_set(dsp56k_core* cpustate, UINT8 value);
/* Command Vector Register (CVR) Bits */
static void CVR_set(dsp56k_core* cpustate, UINT8 value);
//static UINT8 HC_bit();
static UINT8 HV_bits(dsp56k_core* cpustate);
static void HC_bit_set(dsp56k_core* cpustate, UINT8 value);
static void HV_bits_set(dsp56k_core* cpustate, UINT8 value);
/* Interrupt Status Register (ISR) Bits */
// static void ISR_set(dsp56k_core* cpustate, UINT8 value);
//static UINT8 HREQ_bit(dsp56k_core* cpustate); #define x_hreqBIT ((dsp56k.HI.ISR & 0x0080) != 0)
//static UINT8 DMA_bit(dsp56k_core* cpustate); #define x_dmaBIT ((dsp56k.HI.ISR & 0x0040) != 0)
//static UINT8 HF3_bit_host(dsp56k_core* cpustate); #define x_hf3BIT ((dsp56k.HI.ISR & 0x0010) != 0)
//static UINT8 HF2_bit_host(dsp56k_core* cpustate); #define x_hf2BIT ((dsp56k.HI.ISR & 0x0008) != 0)
//static UINT8 TRDY_bit(dsp56k_core* cpustate); #define x_trdyBIT ((dsp56k.HI.ISR & 0x0004) != 0)
static UINT8 TXDE_bit(dsp56k_core* cpustate);
static UINT8 RXDF_bit(dsp56k_core* cpustate);
//static void HREQ_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hreqBIT() (dsp56k.HI.ISR &= (~0x0080))
//static void DMA_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_dmaBIT() (dsp56k.HI.ISR &= (~0x0040))
static void HF3_bit_host_set(dsp56k_core* cpustate, UINT8 value);
static void HF2_bit_host_set(dsp56k_core* cpustate, UINT8 value);
//static void TRDY_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_trdyBIT() (dsp56k.HI.ISR &= (~0x0004))
static void TXDE_bit_set(dsp56k_core* cpustate, UINT8 value);
static void RXDF_bit_set(dsp56k_core* cpustate, UINT8 value);
/* Interrupt Vector Register (IVR) Bits */
//static void IVR_set(dsp56k_core* cpustate, UINT8 value);
//static UINT8 IV7_bit(dsp56k_core* cpustate);
//static UINT8 IV6_bit(dsp56k_core* cpustate);
//static UINT8 IV5_bit(dsp56k_core* cpustate);
//static UINT8 IV4_bit(dsp56k_core* cpustate);
//static UINT8 IV3_bit(dsp56k_core* cpustate);
//static UINT8 IV2_bit(dsp56k_core* cpustate);
//static UINT8 IV1_bit(dsp56k_core* cpustate);
//static UINT8 IV0_bit(dsp56k_core* cpustate);
//static void IV7_bit_set(dsp56k_core* cpustate, UINT8 value);
//static void IV6_bit_set(dsp56k_core* cpustate, UINT8 value);
//static void IV5_bit_set(dsp56k_core* cpustate, UINT8 value);
//static void IV4_bit_set(dsp56k_core* cpustate, UINT8 value);
//static void IV3_bit_set(dsp56k_core* cpustate, UINT8 value);
//static void IV2_bit_set(dsp56k_core* cpustate, UINT8 value);
//static void IV1_bit_set(dsp56k_core* cpustate, UINT8 value);
//static void IV0_bit_set(dsp56k_core* cpustate, UINT8 value);
/* PROTOTYPES */
static void dsp56k_host_interface_HTX_to_host(dsp56k_core* cpustate);
static void dsp56k_host_interface_host_to_HTX(dsp56k_core* cpustate);
/***************************************************************************
I/O INTERFACE
***************************************************************************/
static void dsp56k_io_reset(dsp56k_core* cpustate);
/* Port A Bus Control Register (BCR) */
static void BCR_set(dsp56k_core* cpustate, UINT16 value);
//static UINT16 RH_bit(dsp56k_core* cpustate);
//static UINT16 BS_bit(dsp56k_core* cpustate);
//static UINT16 external_x_wait_states(dsp56k_core* cpustate);
//static UINT16 external_p_wait_states(dsp56k_core* cpustate);
static void RH_bit_set(dsp56k_core* cpustate, UINT16 value);
static void BS_bit_set(dsp56k_core* cpustate, UINT16 value);
static void external_x_wait_states_set(dsp56k_core* cpustate, UINT16 value);
static void external_p_wait_states_set(dsp56k_core* cpustate, UINT16 value);
/* Port B Control Register (PBC) */
static void PBC_set(dsp56k_core* cpustate, UINT16 value);
//static int host_interface_active(dsp56k_core* cpustate);
/* Port B Data Direction Register (PBDDR) */
static void PBDDR_set(dsp56k_core* cpustate, UINT16 value);
/* Port B Data Register (PBD) */
static void PBD_set(dsp56k_core* cpustate, UINT16 value);
/* Port C Control Register (PCC) */
static void PCC_set(dsp56k_core* cpustate, UINT16 value);
/* Port C Data Direction Register (PCDDR) */
static void PCDDR_set(dsp56k_core* cpustate, UINT16 value);
/* Port C Dtaa Register (PCD) */
static void PCD_set(dsp56k_core* cpustate, UINT16 value);
INLINE dsp56k_core *get_safe_token(running_device *device)
{
assert(device != NULL);
assert(device->type() == DSP56156);
return (dsp56k_core *)downcast<legacy_cpu_device *>(device)->token();
}

78
src/emu/cpu/dsp56k/dsp56k.c
View File

@ -29,12 +29,16 @@
- 1-21 Vectored exception requests on the Host Interface! - 1-21 Vectored exception requests on the Host Interface!
***************************************************************************/ ***************************************************************************/
#include "opcode.h"
#include "emu.h" #include "emu.h"
#include "debugger.h" #include "debugger.h"
#include "dsp56k.h" #include "dsp56k.h"
#include "dsp56def.h" #include "dsp56def.h"
using namespace DSP56K;
/*************************************************************************** /***************************************************************************
FUNCTION PROTOTYPES FUNCTION PROTOTYPES
***************************************************************************/ ***************************************************************************/
@ -42,30 +46,29 @@ static CPU_RESET( dsp56k );
/*************************************************************************** /***************************************************************************
ONBOARD MEMORY ALLOCATION ONBOARD MEMORY
***************************************************************************/ ***************************************************************************/
// TODO: Put these in the cpustate!!! UINT16 *dsp56k_peripheral_ram;
static UINT16 *dsp56k_peripheral_ram; UINT16 *dsp56k_program_ram;
static UINT16 *dsp56k_program_ram;
/*************************************************************************** /***************************************************************************
COMPONENT FUNCTIONALITY COMPONENT FUNCTIONALITY
***************************************************************************/ ***************************************************************************/
/* 1-9 ALU */ /* 1-9 ALU */
// #include "dsp56alu.c" // #include "dsp56alu.h"
/* 1-10 Address Generation Unit (AGU) */ /* 1-10 Address Generation Unit (AGU) */
// #include "dsp56agu.c" // #include "dsp56agu.h"
/* 1-11 Program Control Unit (PCU) */ /* 1-11 Program Control Unit (PCU) */
#include "dsp56pcu.c" #include "dsp56pcu.h"
/* 5-1 Host Interface (HI) */ /* 5-1 Host Interface (HI) */
//#include "dsp56hi.c" //#include "dsp56hi.h"
/* 4-8 Memory handlers for on-chip peripheral memory. */ /* 4-8 Memory handlers for on-chip peripheral memory. */
#include "dsp56mem.c" #include "dsp56mem.h"
/*************************************************************************** /***************************************************************************
@ -306,13 +309,30 @@ static CPU_EXIT( dsp56k )
/*************************************************************************** /***************************************************************************
CORE INCLUDE CORE INCLUDE
***************************************************************************/ ***************************************************************************/
#define OP (cpustate->op)
#include "dsp56ops.c" #include "dsp56ops.c"
/*************************************************************************** /***************************************************************************
CORE EXECUTION LOOP CORE EXECUTION LOOP
***************************************************************************/ ***************************************************************************/
// Execute a single opcode and return how many cycles it took.
static size_t execute_one_new(dsp56k_core* cpustate)
{
// For MAME
cpustate->op = ROPCODE(ADDRESS(PC));
debugger_instruction_hook(cpustate->device, PC);
UINT16 w0 = ROPCODE(ADDRESS(PC));
UINT16 w1 = ROPCODE(ADDRESS(PC) + ADDRESS(1));
Opcode op(w0, w1);
op.evaluate(cpustate);
PC += op.evalSize(); // Special size function needed to handle jmps, etc.
// TODO: Currently all operations take up 4 cycles (inst->cycles()).
return 4;
}
static CPU_EXECUTE( dsp56k ) static CPU_EXECUTE( dsp56k )
{ {
dsp56k_core* cpustate = get_safe_token(device); dsp56k_core* cpustate = get_safe_token(device);
@ -331,17 +351,15 @@ static CPU_EXECUTE( dsp56k )
return; return;
} }
cpustate->icount -= cpustate->interrupt_cycles; //cpustate->icount -= cpustate->interrupt_cycles;
cpustate->interrupt_cycles = 0; //cpustate->interrupt_cycles = 0;
while(cpustate->icount > 0) while(cpustate->icount > 0)
{ {
execute_one(cpustate); execute_one(cpustate);
pcu_service_interrupts(cpustate); /* TODO: There is definitely something un-right about this */ if (0) cpustate->icount -= execute_one_new(cpustate);
pcu_service_interrupts(cpustate); // TODO: Is it incorrect to service after each instruction?
} }
cpustate->icount -= cpustate->interrupt_cycles;
cpustate->interrupt_cycles = 0;
} }
@ -452,18 +470,18 @@ CPU_GET_INFO( dsp56k )
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 2; break; case CPUINFO_INT_CLOCK_DIVIDER: info->i = 2; break;
case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break; case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break;
case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break; case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break;
case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; // ? case CPUINFO_INT_MIN_CYCLES: info->i = 1; // ? break;
case CPUINFO_INT_MAX_CYCLES: info->i = 8; break; // ? case CPUINFO_INT_MAX_CYCLES: info->i = 8; // ? break;
case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 16; break; /* 1-5 */ case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 16; break;
case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 16; break; /* 1-5 */ case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 16; break;
case DEVINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = -1; break; case DEVINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = -1; break;
case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 16; break; case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 16; break;
case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 16; break; case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 16; break;
case DEVINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = -1; break; case DEVINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = -1; break;
case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; case DEVINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break;
case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break; case DEVINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break;
case DEVINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break; case DEVINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
case CPUINFO_INT_INPUT_STATE + DSP56K_IRQ_MODA: info->i = DSP56K_IRQ_MODA; break; case CPUINFO_INT_INPUT_STATE + DSP56K_IRQ_MODA: info->i = DSP56K_IRQ_MODA; break;
case CPUINFO_INT_INPUT_STATE + DSP56K_IRQ_MODB: info->i = DSP56K_IRQ_MODB; break; case CPUINFO_INT_INPUT_STATE + DSP56K_IRQ_MODB: info->i = DSP56K_IRQ_MODB; break;
@ -503,8 +521,8 @@ CPU_GET_INFO( dsp56k )
case CPUINFO_INT_REGISTER + DSP56K_M2: info->i = M2; break; case CPUINFO_INT_REGISTER + DSP56K_M2: info->i = M2; break;
case CPUINFO_INT_REGISTER + DSP56K_M3: info->i = M3; break; case CPUINFO_INT_REGISTER + DSP56K_M3: info->i = M3; break;
/* case CPUINFO_INT_REGISTER + DSP56K_TEMP: info->i = TEMP; break; */ /* case CPUINFO_INT_REGISTER + DSP56K_TEMP: info->i = TEMP; break; */
/* case CPUINFO_INT_REGISTER + DSP56K_STATUS: info->i = STATUS; break; */ /* case CPUINFO_INT_REGISTER + DSP56K_STATUS: info->i = STATUS; break; */
/* The CPU stack */ /* The CPU stack */
case CPUINFO_INT_REGISTER + DSP56K_ST0: info->i = ST0; break; case CPUINFO_INT_REGISTER + DSP56K_ST0: info->i = ST0; break;
@ -568,7 +586,7 @@ CPU_GET_INFO( dsp56k )
/* Stack Pointer */ /* Stack Pointer */
UF_bit(cpustate) ? "U" : ".", UF_bit(cpustate) ? "U" : ".",
SE_bit(cpustate) ? "S" : "."); SE_bit(cpustate) ? "S" : ".");
break; break;
case CPUINFO_STR_REGISTER + DSP56K_PC: sprintf(info->s, "PC : %04x", PC); break; case CPUINFO_STR_REGISTER + DSP56K_PC: sprintf(info->s, "PC : %04x", PC); break;
case CPUINFO_STR_REGISTER + DSP56K_SR: sprintf(info->s, "SR : %04x", SR); break; case CPUINFO_STR_REGISTER + DSP56K_SR: sprintf(info->s, "SR : %04x", SR); break;

9
src/emu/cpu/dsp56k/dsp56k.h
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@ -12,6 +12,7 @@
#ifndef __DSP56K_H__ #ifndef __DSP56K_H__
#define __DSP56K_H__ #define __DSP56K_H__
#include "emu.h"
/*************************************************************************** /***************************************************************************
REGISTER ENUMERATION REGISTER ENUMERATION
@ -237,6 +238,14 @@ typedef struct
} dsp56k_core; } dsp56k_core;
INLINE dsp56k_core *get_safe_token(running_device *device)
{
assert(device != NULL);
assert(device->type() == DSP56156);
return (dsp56k_core *)downcast<legacy_cpu_device *>(device)->token();
}
/*************************************************************************** /***************************************************************************
PUBLIC FUNCTIONS - ACCESSIBLE TO DRIVERS PUBLIC FUNCTIONS - ACCESSIBLE TO DRIVERS
***************************************************************************/ ***************************************************************************/

977
src/emu/cpu/dsp56k/dsp56mem.c
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File diff suppressed because it is too large Load Diff

243
src/emu/cpu/dsp56k/dsp56mem.h Normal file
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@ -0,0 +1,243 @@
#ifndef __DSP56_MEM_H__
#define __DSP56_MEM_H__
#include "dsp56k.h"
namespace DSP56K
{
/***************************************************************************
MEMORY
***************************************************************************/
void mem_reset(dsp56k_core* cpustate);
// Adjusts the documented address to match the offset in peripheral RAM
#define A2O(a) (a-0xffc0)
// Adjusts the offset in peripheral RAM to match the documented address
#define O2A(a) (a+0xffc0)
// The memory 'registers'
#define PBC (dsp56k_peripheral_ram[A2O(0xffc0)])
#define PCC (dsp56k_peripheral_ram[A2O(0xffc1)])
#define PBDDR (dsp56k_peripheral_ram[A2O(0xffc2)])
#define PCDDR (dsp56k_peripheral_ram[A2O(0xffc3)])
#define HCR (dsp56k_peripheral_ram[A2O(0xffc4)])
#define COCR (dsp56k_peripheral_ram[A2O(0xffc8)])
#define CRASSI0 (dsp56k_peripheral_ram[A2O(0xffd0)])
#define CRBSSI0 (dsp56k_peripheral_ram[A2O(0xffd1)])
#define CRASSI1 (dsp56k_peripheral_ram[A2O(0xffd8)])
#define CRBSSI1 (dsp56k_peripheral_ram[A2O(0xffd9)])
#define PLCR (dsp56k_peripheral_ram[A2O(0xffdc)])
#define BCR (dsp56k_peripheral_ram[A2O(0xffde)])
#define IPR (dsp56k_peripheral_ram[A2O(0xffdf)])
#define PBD (dsp56k_peripheral_ram[A2O(0xffe2)])
#define PCD (dsp56k_peripheral_ram[A2O(0xffe3)])
#define HSR (dsp56k_peripheral_ram[A2O(0xffe4)])
#define HTXHRX (dsp56k_peripheral_ram[A2O(0xffe5)])
#define COSR (dsp56k_peripheral_ram[A2O(0xffe8)])
#define CRXCTX (dsp56k_peripheral_ram[A2O(0xffe9)])
#define TCR (dsp56k_peripheral_ram[A2O(0xffec)])
#define TCTR (dsp56k_peripheral_ram[A2O(0xffed)])
#define TCPR (dsp56k_peripheral_ram[A2O(0xffee)])
#define TPR (dsp56k_peripheral_ram[A2O(0xffef)])
#define TSRSSI0 (dsp56k_peripheral_ram[A2O(0xfff0)])
#define TRXSSI0 (dsp56k_peripheral_ram[A2O(0xfff1)])
#define RSMA0 (dsp56k_peripheral_ram[A2O(0xfff2)])
#define RSMB0 (dsp56k_peripheral_ram[A2O(0xfff3)])
#define TSMA0 (dsp56k_peripheral_ram[A2O(0xfff4)])
#define TSMB0 (dsp56k_peripheral_ram[A2O(0xfff5)])
#define TSRSSI1 (dsp56k_peripheral_ram[A2O(0xfff8)])
#define TRXSSI1 (dsp56k_peripheral_ram[A2O(0xfff9)])
#define RSMA1 (dsp56k_peripheral_ram[A2O(0xfffa)])
#define RSMB1 (dsp56k_peripheral_ram[A2O(0xfffb)])
#define TSMA1 (dsp56k_peripheral_ram[A2O(0xfffc)])
#define TSMB1 (dsp56k_peripheral_ram[A2O(0xfffd)])
/* Interrupt priority register (IPR) bits */
void IPR_set(dsp56k_core* cpustate, UINT16 value);
/* A return value of -1 means disabled */
INT8 irqa_ipl(dsp56k_core* cpustate);
INT8 irqb_ipl(dsp56k_core* cpustate);
UINT8 irqa_trigger(dsp56k_core* cpustate);
UINT8 irqb_trigger(dsp56k_core* cpustate);
INT8 codec_ipl(dsp56k_core* cpustate);
INT8 host_ipl(dsp56k_core* cpustate);
INT8 ssi0_ipl(dsp56k_core* cpustate);
INT8 ssi1_ipl(dsp56k_core* cpustate);
INT8 tm_ipl(dsp56k_core* cpustate);
/***************************************************************************
HOST INTERFACE
***************************************************************************/
void dsp56k_host_interface_reset(dsp56k_core* cpustate);
#define HTX (HTXHRX)
#define HRX (HTXHRX)
#define ICR (cpustate->HI.icr)
#define CVR (cpustate->HI.cvr)
#define ISR (cpustate->HI.isr)
#define IVR (cpustate->HI.ivr)
#define TXH (cpustate->HI.trxh)
#define TXL (cpustate->HI.trxl)
#define RXH (cpustate->HI.trxh)
#define RXL (cpustate->HI.trxl)
/***************/
/* DSP56k SIDE */
/***************/
/* Host Control Register (HCR) Bits */
void HCR_set(dsp56k_core* cpustate, UINT16 value);
//UINT16 HF3_bit(dsp56k_core* cpustate); #define hf3BIT ((HCR & 0x0010) != 0)
//UINT16 HF2_bit(dsp56k_core* cpustate); #define hf2BIT ((HCR & 0x0008) != 0)
UINT16 HCIE_bit(dsp56k_core* cpustate);
UINT16 HTIE_bit(dsp56k_core* cpustate);
UINT16 HRIE_bit(dsp56k_core* cpustate);
void HF3_bit_set(dsp56k_core* cpustate, UINT16 value);
void HF2_bit_set(dsp56k_core* cpustate, UINT16 value);
void HCIE_bit_set(dsp56k_core* cpustate, UINT16 value);
void HTIE_bit_set(dsp56k_core* cpustate, UINT16 value);
void HRIE_bit_set(dsp56k_core* cpustate, UINT16 value);
/* Host Status Register (HSR) Bits */
//void HSR_set(dsp56k_core* cpustate, UINT16 value);
//UINT16 DMA_bit(dsp56k_core* cpustate); #define dmaBIT ((HSR & 0x0080) != 0)
//UINT16 HF1_bit(dsp56k_core* cpustate); #define hf1BIT ((HSR & 0x0010) != 0)
//UINT16 HF0_bit(dsp56k_core* cpustate); #define hf0BIT ((HSR & 0x0008) != 0)
//UINT16 HCP_bit(dsp56k_core* cpustate); #define hcpBIT ((HSR & 0x0004) != 0)
UINT16 HTDE_bit(dsp56k_core* cpustate);
UINT16 HRDF_bit(dsp56k_core* cpustate);
void DMA_bit_set(dsp56k_core* cpustate, UINT16 value);
void HF1_bit_set(dsp56k_core* cpustate, UINT16 value);
void HF0_bit_set(dsp56k_core* cpustate, UINT16 value);
void HCP_bit_set(dsp56k_core* cpustate, UINT16 value);
void HTDE_bit_set(dsp56k_core* cpustate, UINT16 value);
void HRDF_bit_set(dsp56k_core* cpustate, UINT16 value);
/*************/
/* HOST SIDE */
/*************/
/* Interrupt Control Register (ICR) Bits */
void ICR_set(dsp56k_core* cpustate, UINT8 value);
//UINT8 INIT_bit(dsp56k_core* cpustate); #define x_initBIT ((dsp56k.HI.ICR & 0x0080) != 0)
//UINT8 HM1_bit(dsp56k_core* cpustate); #define x_hm1BIT ((dsp56k.HI.ICR & 0x0040) != 0)
//UINT8 HM0_bit(dsp56k_core* cpustate); #define x_hm0BIT ((dsp56k.HI.ICR & 0x0020) != 0)
//UINT8 HF1_bit_host(dsp56k_core* cpustate); #define x_hf1BIT ((dsp56k.HI.ICR & 0x0010) != 0)
//UINT8 HF0_bit_host(dsp56k_core* cpustate); #define x_hf0BIT ((dsp56k.HI.ICR & 0x0008) != 0)
//UINT8 TREQ_bit(dsp56k_core* cpustate); #define x_treqBIT ((dsp56k.HI.ICR & 0x0002) != 0)
//UINT8 RREQ_bit(dsp56k_core* cpustate); #define x_rreqBIT ((dsp56k.HI.ICR & 0x0001) != 0)
//void INIT_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_initBIT() (dsp56k.HI.ICR &= (~0x0080))
//void HM1_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hm1BIT() (dsp56k.HI.ICR &= (~0x0040))
//void HM0_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hm0BIT() (dsp56k.HI.ICR &= (~0x0020))
void HF1_bit_host_set(dsp56k_core* cpustate, UINT8 value);
void HF0_bit_host_set(dsp56k_core* cpustate, UINT8 value);
void TREQ_bit_set(dsp56k_core* cpustate, UINT8 value);
void RREQ_bit_set(dsp56k_core* cpustate, UINT8 value);
/* Command Vector Register (CVR) Bits */
void CVR_set(dsp56k_core* cpustate, UINT8 value);
//UINT8 HC_bit();
UINT8 HV_bits(dsp56k_core* cpustate);
void HC_bit_set(dsp56k_core* cpustate, UINT8 value);
void HV_bits_set(dsp56k_core* cpustate, UINT8 value);
/* Interrupt Status Register (ISR) Bits */
// void ISR_set(dsp56k_core* cpustate, UINT8 value);
//UINT8 HREQ_bit(dsp56k_core* cpustate); #define x_hreqBIT ((dsp56k.HI.ISR & 0x0080) != 0)
//UINT8 DMA_bit(dsp56k_core* cpustate); #define x_dmaBIT ((dsp56k.HI.ISR & 0x0040) != 0)
//UINT8 HF3_bit_host(dsp56k_core* cpustate); #define x_hf3BIT ((dsp56k.HI.ISR & 0x0010) != 0)
//UINT8 HF2_bit_host(dsp56k_core* cpustate); #define x_hf2BIT ((dsp56k.HI.ISR & 0x0008) != 0)
//UINT8 TRDY_bit(dsp56k_core* cpustate); #define x_trdyBIT ((dsp56k.HI.ISR & 0x0004) != 0)
UINT8 TXDE_bit(dsp56k_core* cpustate);
UINT8 RXDF_bit(dsp56k_core* cpustate);
//void HREQ_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_hreqBIT() (dsp56k.HI.ISR &= (~0x0080))
//void DMA_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_dmaBIT() (dsp56k.HI.ISR &= (~0x0040))
void HF3_bit_host_set(dsp56k_core* cpustate, UINT8 value);
void HF2_bit_host_set(dsp56k_core* cpustate, UINT8 value);
//void TRDY_bit_set(dsp56k_core* cpustate, UINT8 value); #define CLEAR_x_trdyBIT() (dsp56k.HI.ISR &= (~0x0004))
void TXDE_bit_set(dsp56k_core* cpustate, UINT8 value);
void RXDF_bit_set(dsp56k_core* cpustate, UINT8 value);
/* Interrupt Vector Register (IVR) Bits */
//void IVR_set(dsp56k_core* cpustate, UINT8 value);
//UINT8 IV7_bit(dsp56k_core* cpustate);
//UINT8 IV6_bit(dsp56k_core* cpustate);
//UINT8 IV5_bit(dsp56k_core* cpustate);
//UINT8 IV4_bit(dsp56k_core* cpustate);
//UINT8 IV3_bit(dsp56k_core* cpustate);
//UINT8 IV2_bit(dsp56k_core* cpustate);
//UINT8 IV1_bit(dsp56k_core* cpustate);
//UINT8 IV0_bit(dsp56k_core* cpustate);
//void IV7_bit_set(dsp56k_core* cpustate, UINT8 value);
//void IV6_bit_set(dsp56k_core* cpustate, UINT8 value);
//void IV5_bit_set(dsp56k_core* cpustate, UINT8 value);
//void IV4_bit_set(dsp56k_core* cpustate, UINT8 value);
//void IV3_bit_set(dsp56k_core* cpustate, UINT8 value);
//void IV2_bit_set(dsp56k_core* cpustate, UINT8 value);
//void IV1_bit_set(dsp56k_core* cpustate, UINT8 value);
//void IV0_bit_set(dsp56k_core* cpustate, UINT8 value);
/* PROTOTYPES */
void dsp56k_host_interface_HTX_to_host(dsp56k_core* cpustate);
void dsp56k_host_interface_host_to_HTX(dsp56k_core* cpustate);
/***************************************************************************
I/O INTERFACE
***************************************************************************/
void dsp56k_io_reset(dsp56k_core* cpustate);
/* Port A Bus Control Register (BCR) */
void BCR_set(dsp56k_core* cpustate, UINT16 value);
//UINT16 RH_bit(dsp56k_core* cpustate);
//UINT16 BS_bit(dsp56k_core* cpustate);
//UINT16 external_x_wait_states(dsp56k_core* cpustate);
//UINT16 external_p_wait_states(dsp56k_core* cpustate);
void RH_bit_set(dsp56k_core* cpustate, UINT16 value);
void BS_bit_set(dsp56k_core* cpustate, UINT16 value);
void external_x_wait_states_set(dsp56k_core* cpustate, UINT16 value);
void external_p_wait_states_set(dsp56k_core* cpustate, UINT16 value);
/* Port B Control Register (PBC) */
void PBC_set(dsp56k_core* cpustate, UINT16 value);
//int host_interface_active(dsp56k_core* cpustate);
/* Port B Data Direction Register (PBDDR) */
void PBDDR_set(dsp56k_core* cpustate, UINT16 value);
/* Port B Data Register (PBD) */
void PBD_set(dsp56k_core* cpustate, UINT16 value);
/* Port C Control Register (PCC) */
void PCC_set(dsp56k_core* cpustate, UINT16 value);
/* Port C Data Direction Register (PCDDR) */
void PCDDR_set(dsp56k_core* cpustate, UINT16 value);
/* Port C Dtaa Register (PCD) */
void PCD_set(dsp56k_core* cpustate, UINT16 value);
} // namespace DSP56K
READ16_HANDLER( peripheral_register_r );
WRITE16_HANDLER( peripheral_register_w );
#endif

3
src/emu/cpu/dsp56k/dsp56ops.c
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@ -44,7 +44,6 @@ typedef struct _typed_pointer typed_pointer;
#define ADDRESS(X) (X<<1) #define ADDRESS(X) (X<<1)
#define BITS(CUR,MASK) (Dsp56kOpMask(CUR,MASK)) #define BITS(CUR,MASK) (Dsp56kOpMask(CUR,MASK))
/*********************/ /*********************/
/* Opcode prototypes */ /* Opcode prototypes */
/*********************/ /*********************/
@ -240,8 +239,8 @@ static void execute_one(dsp56k_core* cpustate)
UINT8 cycle_count = 0; UINT8 cycle_count = 0;
/* For MAME */ /* For MAME */
cpustate->op = ROPCODE(ADDRESS(PC));
debugger_instruction_hook(cpustate->device, PC); debugger_instruction_hook(cpustate->device, PC);
OP = ROPCODE(ADDRESS(PC));
/* The words we're going to be working with */ /* The words we're going to be working with */
op = ROPCODE(ADDRESS(PC)); op = ROPCODE(ADDRESS(PC));

121
src/emu/cpu/dsp56k/dsp56pcu.c
View File

@ -1,3 +1,12 @@
#include "dsp56pcu.h"
#include "dsp56mem.h"
extern UINT16 *dsp56k_peripheral_ram;
extern UINT16 *dsp56k_program_ram;
namespace DSP56K
{
/* ************************************************************************* */ /* ************************************************************************* */
/* Status Register */ /* Status Register */
/* ************************************************************************* */ /* ************************************************************************* */
@ -7,34 +16,34 @@
/* |-------------------------------------| |-------------------------------| */ /* |-------------------------------------| |-------------------------------| */
/* */ /* */
/* ************************************************************************* */ /* ************************************************************************* */
static UINT8 LF_bit(dsp56k_core* cpustate) { return (SR & 0x8000) >> 15; } UINT8 LF_bit(dsp56k_core* cpustate) { return (SR & 0x8000) >> 15; }
static UINT8 FV_bit(dsp56k_core* cpustate) { return (SR & 0x4000) >> 14; } UINT8 FV_bit(dsp56k_core* cpustate) { return (SR & 0x4000) >> 14; }
// static UINT8 S_bits(dsp56k_core* cpustate) { return (SR & 0x0c00) >> 10; } // UINT8 S_bits(dsp56k_core* cpustate) { return (SR & 0x0c00) >> 10; }
static UINT8 I_bits(dsp56k_core* cpustate) { return (SR & 0x0300) >> 8; } UINT8 I_bits(dsp56k_core* cpustate) { return (SR & 0x0300) >> 8; }
static UINT8 S_bit (dsp56k_core* cpustate) { return (SR & 0x0080) >> 7; } UINT8 S_bit (dsp56k_core* cpustate) { return (SR & 0x0080) >> 7; }
static UINT8 L_bit (dsp56k_core* cpustate) { return (SR & 0x0040) >> 6; } UINT8 L_bit (dsp56k_core* cpustate) { return (SR & 0x0040) >> 6; }
static UINT8 E_bit (dsp56k_core* cpustate) { return (SR & 0x0020) >> 5; } UINT8 E_bit (dsp56k_core* cpustate) { return (SR & 0x0020) >> 5; }
static UINT8 U_bit (dsp56k_core* cpustate) { return (SR & 0x0010) >> 4; } UINT8 U_bit (dsp56k_core* cpustate) { return (SR & 0x0010) >> 4; }
static UINT8 N_bit (dsp56k_core* cpustate) { return (SR & 0x0008) >> 3; } UINT8 N_bit (dsp56k_core* cpustate) { return (SR & 0x0008) >> 3; }
static UINT8 Z_bit (dsp56k_core* cpustate) { return (SR & 0x0004) >> 2; } UINT8 Z_bit (dsp56k_core* cpustate) { return (SR & 0x0004) >> 2; }
static UINT8 V_bit (dsp56k_core* cpustate) { return (SR & 0x0002) >> 1; } UINT8 V_bit (dsp56k_core* cpustate) { return (SR & 0x0002) >> 1; }
static UINT8 C_bit (dsp56k_core* cpustate) { return (SR & 0x0001) >> 0; } UINT8 C_bit (dsp56k_core* cpustate) { return (SR & 0x0001) >> 0; }
/* MR setters */ /* MR setters */
static void LF_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x8000); else (SR &= (~0x8000)); } void LF_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x8000); else (SR &= (~0x8000)); }
static void FV_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x4000); else (SR &= (~0x4000)); } void FV_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x4000); else (SR &= (~0x4000)); }
static void S_bits_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x03; SR &= ~(0x0c00); SR |= (value << 10); } void S_bits_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x03; SR &= ~(0x0c00); SR |= (value << 10); }
static void I_bits_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x03; SR &= ~(0x0300); SR |= (value << 8); } void I_bits_set(dsp56k_core* cpustate, UINT8 value) { value = value & 0x03; SR &= ~(0x0300); SR |= (value << 8); }
/* CCR setters */ /* CCR setters */
static void S_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0080); else (SR &= (~0x0080)); } void S_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0080); else (SR &= (~0x0080)); }
static void L_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0040); else (SR &= (~0x0040)); } void L_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0040); else (SR &= (~0x0040)); }
static void E_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0020); else (SR &= (~0x0020)); } void E_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0020); else (SR &= (~0x0020)); }
static void U_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0010); else (SR &= (~0x0010)); } void U_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0010); else (SR &= (~0x0010)); }
static void N_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0008); else (SR &= (~0x0008)); } void N_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0008); else (SR &= (~0x0008)); }
static void Z_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0004); else (SR &= (~0x0004)); } void Z_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0004); else (SR &= (~0x0004)); }
static void V_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0002); else (SR &= (~0x0002)); } void V_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0002); else (SR &= (~0x0002)); }
static void C_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0001); else (SR &= (~0x0001)); } void C_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x0001); else (SR &= (~0x0001)); }
@ -47,23 +56,23 @@ static void C_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (SR |= 0x
/* |---------------------------------------------------------------------| */ /* |---------------------------------------------------------------------| */
/* */ /* */
/* ************************************************************************* */ /* ************************************************************************* */
// static UINT8 CD_bit(dsp56k_core* cpustate) { return ((OMR & 0x0080) != 0); } // UINT8 CD_bit(dsp56k_core* cpustate) { return ((OMR & 0x0080) != 0); }
// static UINT8 SD_bit(dsp56k_core* cpustate) { return ((OMR & 0x0040) != 0); } // UINT8 SD_bit(dsp56k_core* cpustate) { return ((OMR & 0x0040) != 0); }
// static UINT8 R_bit(dsp56k_core* cpustate) { return ((OMR & 0x0020) != 0); } // UINT8 R_bit(dsp56k_core* cpustate) { return ((OMR & 0x0020) != 0); }
// static UINT8 SA_bit(dsp56k_core* cpustate) { return ((OMR & 0x0010) != 0); } // UINT8 SA_bit(dsp56k_core* cpustate) { return ((OMR & 0x0010) != 0); }
// static UINT8 MC_bit(dsp56k_core* cpustate) { return ((OMR & 0x0004) != 0); } // UINT8 MC_bit(dsp56k_core* cpustate) { return ((OMR & 0x0004) != 0); }
static UINT8 MB_bit(dsp56k_core* cpustate) { return ((OMR & 0x0002) != 0); } UINT8 MB_bit(dsp56k_core* cpustate) { return ((OMR & 0x0002) != 0); }
static UINT8 MA_bit(dsp56k_core* cpustate) { return ((OMR & 0x0001) != 0); } UINT8 MA_bit(dsp56k_core* cpustate) { return ((OMR & 0x0001) != 0); }
static void CD_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0080); else (OMR &= (~0x0080)); } void CD_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0080); else (OMR &= (~0x0080)); }
static void SD_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0040); else (OMR &= (~0x0040)); } void SD_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0040); else (OMR &= (~0x0040)); }
static void R_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0020); else (OMR &= (~0x0020)); } void R_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0020); else (OMR &= (~0x0020)); }
static void SA_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0010); else (OMR &= (~0x0010)); } void SA_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0010); else (OMR &= (~0x0010)); }
static void MC_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0004); else (OMR &= (~0x0004)); } void MC_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0004); else (OMR &= (~0x0004)); }
static void MB_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0002); else (OMR &= (~0x0002)); } void MB_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0002); else (OMR &= (~0x0002)); }
static void MA_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0001); else (OMR &= (~0x0001)); } void MA_bit_set(dsp56k_core* cpustate, UINT8 value) { if (value) (OMR |= 0x0001); else (OMR &= (~0x0001)); }
static UINT8 dsp56k_operating_mode(dsp56k_core* cpustate) UINT8 dsp56k_operating_mode(dsp56k_core* cpustate)
{ {
return ((MB_bit(cpustate) << 1) | MA_bit(cpustate)); return ((MB_bit(cpustate) << 1) | MA_bit(cpustate));
} }
@ -79,18 +88,18 @@ static UINT8 dsp56k_operating_mode(dsp56k_core* cpustate)
/* |---------------------------------------------------------------------| */ /* |---------------------------------------------------------------------| */
/* */ /* */
/* ************************************************************************* */ /* ************************************************************************* */
static UINT8 UF_bit(dsp56k_core* cpustate) { return ((SP & 0x0020) != 0); } UINT8 UF_bit(dsp56k_core* cpustate) { return ((SP & 0x0020) != 0); }
static UINT8 SE_bit(dsp56k_core* cpustate) { return ((SP & 0x0010) != 0); } UINT8 SE_bit(dsp56k_core* cpustate) { return ((SP & 0x0010) != 0); }
//static void UF_bit_set(dsp56k_core* cpustate, UINT8 value) {}; //void UF_bit_set(dsp56k_core* cpustate, UINT8 value) {};
//static void SE_bit_set(dsp56k_core* cpustate, UINT8 value) {}; //void SE_bit_set(dsp56k_core* cpustate, UINT8 value) {};
/*************************************************************************** /***************************************************************************
INITIALIZATION AND RESET INITIALIZATION AND RESET
***************************************************************************/ ***************************************************************************/
static void pcu_init(dsp56k_core* cpustate, running_device *device) void pcu_init(dsp56k_core* cpustate, running_device *device)
{ {
/* Init the irq table */ /* Init the irq table */
dsp56k_irq_table_init(); dsp56k_irq_table_init();
@ -107,7 +116,7 @@ static void pcu_init(dsp56k_core* cpustate, running_device *device)
state_save_register_device_item(device, 0, cpustate->PCU.reset_vector); state_save_register_device_item(device, 0, cpustate->PCU.reset_vector);
} }
static void pcu_reset(dsp56k_core* cpustate) void pcu_reset(dsp56k_core* cpustate)
{ {
int i; int i;
@ -236,10 +245,10 @@ typedef struct
char irq_source[128]; char irq_source[128];
} dsp56k_irq_data; } dsp56k_irq_data;
static dsp56k_irq_data dsp56k_interrupt_sources[32]; dsp56k_irq_data dsp56k_interrupt_sources[32];
/* TODO: Figure out how to switch on level versus edge-triggered. */ /* TODO: Figure out how to switch on level versus edge-triggered. */
static void pcu_service_interrupts(dsp56k_core* cpustate) void pcu_service_interrupts(dsp56k_core* cpustate)
{ {
int i; int i;
@ -292,7 +301,7 @@ static void pcu_service_interrupts(dsp56k_core* cpustate)
/* Register an interrupt */ /* Register an interrupt */
static void dsp56k_add_pending_interrupt(dsp56k_core* cpustate, const char* name) void dsp56k_add_pending_interrupt(dsp56k_core* cpustate, const char* name)
{ {
int i; int i;
int irq_index = dsp56k_get_irq_index_by_tag(name); int irq_index = dsp56k_get_irq_index_by_tag(name);
@ -308,14 +317,14 @@ static void dsp56k_add_pending_interrupt(dsp56k_core* cpustate, const char* name
} }
/* Utility function to construct IRQ table */ /* Utility function to construct IRQ table */
static void dsp56k_set_irq_source(UINT8 irq_num, UINT16 iv, const char* source) void dsp56k_set_irq_source(UINT8 irq_num, UINT16 iv, const char* source)
{ {
dsp56k_interrupt_sources[irq_num].irq_vector = iv; dsp56k_interrupt_sources[irq_num].irq_vector = iv;
strcpy(dsp56k_interrupt_sources[irq_num].irq_source, source); strcpy(dsp56k_interrupt_sources[irq_num].irq_source, source);
} }
/* Construct a table containing pertient IRQ information */ /* Construct a table containing pertient IRQ information */
static void dsp56k_irq_table_init(void) void dsp56k_irq_table_init(void)
{ {
/* 1-14 + 1-18 */ /* 1-14 + 1-18 */
/* TODO: Cull host command stuff appropriately */ /* TODO: Cull host command stuff appropriately */
@ -355,7 +364,7 @@ static void dsp56k_irq_table_init(void)
} }
/* Clear all entries from the pending table */ /* Clear all entries from the pending table */
static void dsp56k_clear_pending_interrupts(dsp56k_core* cpustate) void dsp56k_clear_pending_interrupts(dsp56k_core* cpustate)
{ {
int i; int i;
for (i = 0; i < 32; i++) for (i = 0; i < 32; i++)
@ -365,7 +374,7 @@ static void dsp56k_clear_pending_interrupts(dsp56k_core* cpustate)
} }
/* Recover number of pending irqs */ /* Recover number of pending irqs */
static int dsp56k_count_pending_interrupts(dsp56k_core* cpustate) int dsp56k_count_pending_interrupts(dsp56k_core* cpustate)
{ {
int numI = 0; int numI = 0;
while (cpustate->PCU.pending_interrupts[numI] != -1) while (cpustate->PCU.pending_interrupts[numI] != -1)
@ -377,7 +386,7 @@ static int dsp56k_count_pending_interrupts(dsp56k_core* cpustate)
} }
/* Sort the pending irqs by priority */ /* Sort the pending irqs by priority */
static void dsp56k_sort_pending_interrupts(dsp56k_core* cpustate, int num) void dsp56k_sort_pending_interrupts(dsp56k_core* cpustate, int num)
{ {
int i, j; int i, j;
@ -414,7 +423,7 @@ static void dsp56k_sort_pending_interrupts(dsp56k_core* cpustate, int num)
} }
/* Given an index into the irq table, return the interrupt's current priority */ /* Given an index into the irq table, return the interrupt's current priority */
static INT8 dsp56k_get_irq_priority(dsp56k_core* cpustate, int index) INT8 dsp56k_get_irq_priority(dsp56k_core* cpustate, int index)
{ {
/* 1-12 */ /* 1-12 */
switch (index) switch (index)
@ -462,7 +471,7 @@ static INT8 dsp56k_get_irq_priority(dsp56k_core* cpustate, int index)
} }
/* Given an IRQ name, return its index in the irq table */ /* Given an IRQ name, return its index in the irq table */
static int dsp56k_get_irq_index_by_tag(const char* tag) int dsp56k_get_irq_index_by_tag(const char* tag)
{ {
int i; int i;
for (i = 0; i < 32; i++) for (i = 0; i < 32; i++)
@ -476,3 +485,5 @@ static int dsp56k_get_irq_index_by_tag(const char* tag)
fatalerror("DSP56K ERROR : IRQ TAG specified incorrectly (get_vector_by_tag) : %s.\n", tag); fatalerror("DSP56K ERROR : IRQ TAG specified incorrectly (get_vector_by_tag) : %s.\n", tag);
return -1; return -1;
} }
} // namespace DSP56K

149
src/emu/cpu/dsp56k/dsp56pcu.h Normal file
View File

@ -0,0 +1,149 @@
#ifndef __DSP56_PCU_H__
#define __DSP56_PCU_H__
#include "dsp56k.h"
namespace DSP56K
{
/***************************************************************************
PCU
***************************************************************************/
void pcu_reset(dsp56k_core* cpustate);
void pcu_init(dsp56k_core* cpustate, running_device *device);
#define PC (cpustate->PCU.pc)
#define LA (cpustate->PCU.la)
#define LC (cpustate->PCU.lc)
#define SR (cpustate->PCU.sr)
#define OMR (cpustate->PCU.omr)
#define SP (cpustate->PCU.sp)
#define SS (cpustate->PCU.ss)
#define SSH (SS[SP].w.h)
#define SSL (SS[SP].w.l)
#define ST0 (SS[0].d)
#define ST1 (SS[1].d)
#define ST2 (SS[2].d)
#define ST3 (SS[3].d)
#define ST4 (SS[4].d)
#define ST5 (SS[5].d)
#define ST6 (SS[6].d)
#define ST7 (SS[7].d)
#define ST8 (SS[8].d)
#define ST9 (SS[9].d)
#define ST10 (SS[10].d)
#define ST11 (SS[11].d)
#define ST12 (SS[12].d)
#define ST13 (SS[13].d)
#define ST14 (SS[14].d)
#define ST15 (SS[15].d)
/* STATUS REGISTER (SR) BITS (1-25) */
/* MR */
UINT8 LF_bit(dsp56k_core* cpustate);
UINT8 FV_bit(dsp56k_core* cpustate);
//UINT8 S_bits(dsp56k_core* cpustate);
UINT8 I_bits(dsp56k_core* cpustate);
/* CCR - with macros for easy access */
#define S() (S_bit(cpustate))
UINT8 S_bit(dsp56k_core* cpustate);
#define L() (L_bit(cpustate))
UINT8 L_bit(dsp56k_core* cpustate);
#define E() (E_bit(cpustate))
UINT8 E_bit(dsp56k_core* cpustate);
#define U() (U_bit(cpustate))
UINT8 U_bit(dsp56k_core* cpustate);
#define N() (N_bit(cpustate))
UINT8 N_bit(dsp56k_core* cpustate);
#define Z() (Z_bit(cpustate))
UINT8 Z_bit(dsp56k_core* cpustate);
#define V() (V_bit(cpustate))
UINT8 V_bit(dsp56k_core* cpustate);
#define C() (C_bit(cpustate))
UINT8 C_bit(dsp56k_core* cpustate);
/* MR setters */
void LF_bit_set(dsp56k_core* cpustate, UINT8 value);
void FV_bit_set(dsp56k_core* cpustate, UINT8 value);
void S_bits_set(dsp56k_core* cpustate, UINT8 value);
void I_bits_set(dsp56k_core* cpustate, UINT8 value);
/* CCR setters - with macros for easy access */
#define DSP56K_S_SET() (S_bit_set(cpustate, 1))
#define DSP56K_S_CLEAR() (S_bit_set(cpustate, 0))
void S_bit_set(dsp56k_core* cpustate, UINT8 value);
#define DSP56K_L_SET() (L_bit_set(cpustate, 1))
#define DSP56K_L_CLEAR() (L_bit_set(cpustate, 0))
void L_bit_set(dsp56k_core* cpustate, UINT8 value);
#define DSP56K_E_SET() (E_bit_set(cpustate, 1))
#define DSP56K_E_CLEAR() (E_bit_set(cpustate, 0))
void E_bit_set(dsp56k_core* cpustate, UINT8 value);
#define DSP56K_U_SET() (U_bit_set(cpustate, 1))
#define DSP56K_U_CLEAR() (U_bit_set(cpustate, 0))
void U_bit_set(dsp56k_core* cpustate, UINT8 value);
#define DSP56K_N_SET() (N_bit_set(cpustate, 1))
#define DSP56K_N_CLEAR() (N_bit_set(cpustate, 0))
void N_bit_set(dsp56k_core* cpustate, UINT8 value);
#define DSP56K_Z_SET() (Z_bit_set(cpustate, 1))
#define DSP56K_Z_CLEAR() (Z_bit_set(cpustate, 0))
void Z_bit_set(dsp56k_core* cpustate, UINT8 value);
#define DSP56K_V_SET() (V_bit_set(cpustate, 1))
#define DSP56K_V_CLEAR() (V_bit_set(cpustate, 0))
void V_bit_set(dsp56k_core* cpustate, UINT8 value);
#define DSP56K_C_SET() (C_bit_set(cpustate, 1))
#define DSP56K_C_CLEAR() (C_bit_set(cpustate, 0))
void C_bit_set(dsp56k_core* cpustate, UINT8 value);
// TODO: Maybe some functions for Interrupt Mask and Scaling Mode go here?
/* 1-28 OPERATING MODE REGISTER (OMR) BITS */
//UINT8 CD_bit(dsp56k_core* cpustate);
//UINT8 SD_bit(dsp56k_core* cpustate);
//UINT8 R_bit(dsp56k_core* cpustate);
//UINT8 SA_bit(dsp56k_core* cpustate);
//UINT8 MC_bit(dsp56k_core* cpustate);
UINT8 MB_bit(dsp56k_core* cpustate);
UINT8 MA_bit(dsp56k_core* cpustate);
void CD_bit_set(dsp56k_core* cpustate, UINT8 value);
void SD_bit_set(dsp56k_core* cpustate, UINT8 value);
void R_bit_set(dsp56k_core* cpustate, UINT8 value);
void SA_bit_set(dsp56k_core* cpustate, UINT8 value);
void MC_bit_set(dsp56k_core* cpustate, UINT8 value);
void MB_bit_set(dsp56k_core* cpustate, UINT8 value);
void MA_bit_set(dsp56k_core* cpustate, UINT8 value);
/* 1-27 STACK POINTER (SP) BITS */
UINT8 UF_bit(dsp56k_core* cpustate);
UINT8 SE_bit(dsp56k_core* cpustate);
//void UF_bit_set(dsp56k_core* cpustate, UINT8 value) {};
//void SE_bit_set(dsp56k_core* cpustate, UINT8 value) {};
// HACK - Bootstrap modes
#define BOOTSTRAP_OFF (0)
#define BOOTSTRAP_SSIX (1)
#define BOOTSTRAP_HI (2)
/* PCU IRQ goodies */
void pcu_service_interrupts(dsp56k_core* cpustate);
void dsp56k_irq_table_init(void);
void dsp56k_set_irq_source(UINT8 irq_num, UINT16 iv, const char* source);
int dsp56k_get_irq_index_by_tag(const char* tag);
void dsp56k_add_pending_interrupt(dsp56k_core* cpustate, const char* name); // Call me to add an interrupt to the queue
void dsp56k_clear_pending_interrupts(dsp56k_core* cpustate);
int dsp56k_count_pending_interrupts(dsp56k_core* cpustate);
void dsp56k_sort_pending_interrupts(dsp56k_core* cpustate, int num);
INT8 dsp56k_get_irq_priority(dsp56k_core* cpustate, int index);
} // namespace DSP56K
#endif

4
src/emu/cpu/dsp56k/inst.c
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@ -40,7 +40,8 @@ Instruction* Instruction::decodeInstruction(const Opcode* opc,
dynamic_cast<Neg*>(op) || dynamic_cast<Neg*>(op) ||
dynamic_cast<Sub*>(op) || dynamic_cast<Sub*>(op) ||
dynamic_cast<Tfr*>(op) || dynamic_cast<Tfr*>(op) ||
dynamic_cast<Tst*>(op)) dynamic_cast<Tst*>(op)
/* TODO: More? */)
{ {
op->m_sizeIncrement = 1; op->m_sizeIncrement = 1;
return op; return op;
@ -48,7 +49,6 @@ Instruction* Instruction::decodeInstruction(const Opcode* opc,
} }
global_free(op); global_free(op);
//return NULL;
} }

298
src/emu/cpu/dsp56k/inst.h
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File diff suppressed because it is too large Load Diff

14
src/emu/cpu/dsp56k/opcode.c
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@ -41,9 +41,9 @@ std::string Opcode::disassemble() const
} }
void Opcode::evaluate() const void Opcode::evaluate(dsp56k_core* cpustate) const
{ {
if (m_instruction) m_instruction->evaluate(); if (m_instruction) m_instruction->evaluate(cpustate);
if (m_parallelMove) m_parallelMove->evaluate(); if (m_parallelMove) m_parallelMove->evaluate();
} }
@ -57,6 +57,16 @@ size_t Opcode::size() const
return 1; return 1;
} }
size_t Opcode::evalSize() const
{
if (m_instruction && m_instruction->valid())
return m_instruction->evalSize(); // Probably doesn't matter : + m_instruction->sizeIncrement();
// Opcode failed to decode, so push it past dc
return 1;
}
const std::string& Opcode::instSource() const { return m_instruction->source(); } const std::string& Opcode::instSource() const { return m_instruction->source(); }
const std::string& Opcode::instDestination() const { return m_instruction->destination(); } const std::string& Opcode::instDestination() const { return m_instruction->destination(); }
const size_t Opcode::instAccumulatorBitsModified() const { return m_instruction->accumulatorBitsModified(); } const size_t Opcode::instAccumulatorBitsModified() const { return m_instruction->accumulatorBitsModified(); }

5
src/emu/cpu/dsp56k/opcode.h
View File

@ -7,6 +7,8 @@
#include "inst.h" #include "inst.h"
#include "pmove.h" #include "pmove.h"
#include "dsp56k.h"
// //
// An Opcode contains an instruction and a parallel move operation. // An Opcode contains an instruction and a parallel move operation.
// //
@ -23,8 +25,9 @@ public:
virtual ~Opcode(); virtual ~Opcode();
std::string disassemble() const; std::string disassemble() const;
void evaluate() const; void evaluate(dsp56k_core* cpustate) const;
size_t size() const; size_t size() const;
size_t evalSize() const;
// Peek through to the instruction // Peek through to the instruction
const std::string& instSource() const; const std::string& instSource() const;

6
src/emu/cpu/dsp56k/pmove.h
View File

@ -314,13 +314,13 @@ public:
} }
bool decode(const UINT16 word0, const UINT16 word1) bool decode(const UINT16 word0, const UINT16 word1)
{ {
INT8 B; INT8 b;
std::string SD; std::string SD;
std::string args; std::string args;
B = (char)(word0 & 0x00ff); b = (char)(word0 & 0x00ff);
decode_HHH_table(BITSn(word1,0x0e00), SD); decode_HHH_table(BITSn(word1,0x0e00), SD);
assemble_reg_from_W_table(BITSn(word1,0x0100), 'X', SD, B, m_source, m_destination); assemble_reg_from_W_table(BITSn(word1,0x0100), 'X', SD, b, m_source, m_destination);
return true; return true;
} }