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i960.c: Modernized cpu core (nw)

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This commit is contained in:
Wilbert Pol 2013-08-04 12:16:02 +00:00
parent fbf7820fbf
commit 1a9ef1251f
4 changed files with 1007 additions and 1018 deletions
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1900
src/emu/cpu/i960/i960.c
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File diff suppressed because it is too large Load Diff

113
src/emu/cpu/i960/i960.h
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@ -60,9 +60,116 @@ enum
I960_IRQ3 = 3
};
DECLARE_LEGACY_CPU_DEVICE(I960, i960);
void i960_noburst(device_t *device);
void i960_stall(device_t *device);
enum { I960_RCACHE_SIZE = 4 };
class i960_cpu_device : public cpu_device
{
public:
// construction/destruction
i960_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
// call from any read/write handler for a memory area that can't be bursted
// on the real hardware (e.g. Model 2's interrupt control registers)
void i960_noburst() { m_bursting = 0; }
void i960_stall() { m_IP = m_PIP; }
protected:
// device-level overrides
virtual void device_start();
virtual void device_reset();
// device_execute_interface overrides
virtual UINT32 execute_min_cycles() const { return 1; } /* ???? TODO: Exact timing unknown */
virtual UINT32 execute_max_cycles() const { return 1; } /* ???? TODO: Exact timing unknown */
virtual UINT32 execute_input_lines() const { return 4; }
virtual UINT32 execute_default_irq_vector() const { return 0xffffffff; }
virtual void execute_run();
virtual void execute_set_input(int inputnum, int state);
// device_memory_interface overrides
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
// device_state_interface overrides
void state_string_export(const device_state_entry &entry, astring &string);
// device_disasm_interface overrides
virtual UINT32 disasm_min_opcode_bytes() const { return 4; }
virtual UINT32 disasm_max_opcode_bytes() const { return 8; }
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
private:
address_space_config m_program_config;
UINT32 m_r[0x20];
UINT32 m_rcache[I960_RCACHE_SIZE][0x10];
UINT32 m_rcache_frame_addr[I960_RCACHE_SIZE];
// rcache_pos = how deep in the stack we are. 0-(I960_RCACHE_SIZE-1) means in-cache.
// I960_RCACHE_SIZE or greater means out of cache, must save to memory.
INT32 m_rcache_pos;
double m_fp[4];
UINT32 m_SAT;
UINT32 m_PRCB;
UINT32 m_PC;
UINT32 m_AC;
UINT32 m_IP;
UINT32 m_PIP;
UINT32 m_ICR;
int m_bursting;
int m_immediate_irq;
int m_immediate_vector;
int m_immediate_pri;
address_space *m_program;
direct_read_data *m_direct;
int m_icount;
UINT32 i960_read_dword_unaligned(UINT32 address);
UINT16 i960_read_word_unaligned(UINT32 address);
void i960_write_dword_unaligned(UINT32 address, UINT32 data);
void i960_write_word_unaligned(UINT32 address, UINT16 data);
void send_iac(UINT32 adr);
UINT32 get_ea(UINT32 opcode);
UINT32 get_1_ri(UINT32 opcode);
UINT32 get_2_ri(UINT32 opcode);
UINT64 get_2_ri64(UINT32 opcode);
void set_ri(UINT32 opcode, UINT32 val);
void set_ri2(UINT32 opcode, UINT32 val, UINT32 val2);
void set_ri64(UINT32 opcode, UINT64 val);
double get_1_rif(UINT32 opcode);
double get_2_rif(UINT32 opcode);
void set_rif(UINT32 opcode, double val);
double get_1_rifl(UINT32 opcode);
double get_2_rifl(UINT32 opcode);
void set_rifl(UINT32 opcode, double val);
UINT32 get_1_ci(UINT32 opcode);
UINT32 get_2_ci(UINT32 opcode);
UINT32 get_disp(UINT32 opcode);
UINT32 get_disp_s(UINT32 opcode);
void cmp_s(INT32 v1, INT32 v2);
void cmp_u(UINT32 v1, UINT32 v2);
void concmp_s(INT32 v1, INT32 v2);
void concmp_u(UINT32 v1, UINT32 v2);
void cmp_d(double v1, double v2);
void bxx(UINT32 opcode, int mask);
void bxx_s(UINT32 opcode, int mask);
void test(UINT32 opcode, int mask);
void execute_op(UINT32 opcode);
void take_interrupt(int vector, int lvl);
void check_irqs();
void do_call(UINT32 adr, int type, UINT32 stack);
void do_ret_0();
void do_ret();
};
extern const device_type I960;
#endif /* __I960_H__ */

10
src/mame/drivers/model2.c
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@ -183,7 +183,7 @@ static UINT32 copro_fifoout_pop(address_space &space)
if (state->m_copro_fifoout_num == 0)
{
/* Reading from empty FIFO causes the i960 to enter wait state */
i960_stall(&space.device());
downcast<i960_cpu_device &>(space.device()).i960_stall();
/* spin the main cpu and let the TGP catch up */
space.device().execute().spin_until_time(attotime::from_usec(100));
@ -259,7 +259,7 @@ static void copro_fifoout_push(device_t *device, UINT32 data)
/* Timers - these count down at 25 MHz and pull IRQ2 when they hit 0 */
READ32_MEMBER(model2_state::timers_r)
{
i960_noburst(&space.device());
m_maincpu->i960_noburst();
// if timer is running, calculate current value
if (m_timerrun[offset])
@ -278,7 +278,7 @@ WRITE32_MEMBER(model2_state::timers_w)
{
attotime period;
i960_noburst(&space.device());
m_maincpu->i960_noburst();
COMBINE_DATA(&m_timervals[offset]);
m_timerorig[offset] = m_timervals[offset];
@ -935,7 +935,7 @@ READ32_MEMBER(model2_state::desert_unk_r)
READ32_MEMBER(model2_state::model2_irq_r)
{
i960_noburst(&space.device());
m_maincpu->i960_noburst();
if (offset)
{
@ -947,7 +947,7 @@ READ32_MEMBER(model2_state::model2_irq_r)
WRITE32_MEMBER(model2_state::model2_irq_w)
{
i960_noburst(&space.device());
m_maincpu->i960_noburst();
if (offset)
{

2
src/mame/includes/model2.h
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@ -41,7 +41,7 @@ public:
optional_shared_ptr<UINT16> m_soundram;
optional_shared_ptr<UINT32> m_tgp_program;
required_device<cpu_device> m_maincpu;
required_device<i960_cpu_device> m_maincpu;
optional_device<dsbz80_device> m_dsbz80; // Z80-based MPEG Digital Sound Board
required_device<cpu_device> m_audiocpu;
optional_device<multipcm_device> m_multipcm_1;