mirror of
https://github.com/holub/mame
synced 2025-05-14 18:08:13 +03:00
Hooked up basic devices in Queen, guess this is too far to be emulated ...
This commit is contained in:
Angelo Salese
parent
f55b4b99e9
commit
1b0cbe7661
@ -2,6 +2,18 @@
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/*
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TODO:
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- goes to la-la-land almost immediately:
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000F4023: sbb [42F9h],ah
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000F4027: loop 0F4003h
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000F4003: ror word ptr [si+48B2h],1
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000F4007: cmp ax,44B2h
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000F400A: retf
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000903D3: add [bx+si],al
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000903D5: add [bx+si],al
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(Reads stack from BIOS ROM?)
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Produttore STG
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N.revisione
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CPU main PCB is a standard EPIA
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@ -23,6 +35,18 @@ processor speed is 533MHz <- likely to be a Celeron or a Pentium III class CPU -
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#include "emu.h"
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#include "cpu/i386/i386.h"
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#include "memconv.h"
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#include "devconv.h"
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#include "machine/8237dma.h"
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#include "machine/pic8259.h"
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#include "machine/pit8253.h"
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#include "machine/mc146818.h"
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#include "machine/pcshare.h"
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#include "machine/pci.h"
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#include "machine/8042kbdc.h"
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#include "machine/pckeybrd.h"
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#include "machine/idectrl.h"
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#include "video/pc_vga.h"
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class queen_state : public driver_device
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@ -30,82 +54,667 @@ class queen_state : public driver_device
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public:
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queen_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag),
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m_maincpu(*this, "maincpu")
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{ }
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m_maincpu(*this, "maincpu"),
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m_pit8254(*this, "pit8254"),
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m_dma8237_1(*this, "dma8237_1"),
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m_dma8237_2(*this, "dma8237_2"),
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m_pic8259_1(*this, "pic8259_1"),
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m_pic8259_2(*this, "pic8259_2")
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{ }
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protected:
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UINT32 *m_bios_ram;
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UINT32 *m_bios_ext1_ram;
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UINT32 *m_bios_ext2_ram;
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UINT32 *m_bios_ext3_ram;
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UINT32 *m_bios_ext4_ram;
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UINT32 *m_isa_ram1;
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UINT32 *m_isa_ram2;
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int m_dma_channel;
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UINT8 m_dma_offset[2][4];
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UINT8 m_at_pages[0x10];
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UINT8 m_mxtc_config_reg[256];
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UINT8 m_piix4_config_reg[4][256];
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// devices
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required_device<cpu_device> m_maincpu;
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required_device<pit8254_device> m_pit8254;
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required_device<i8237_device> m_dma8237_1;
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required_device<i8237_device> m_dma8237_2;
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required_device<pic8259_device> m_pic8259_1;
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required_device<pic8259_device> m_pic8259_2;
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// driver_device overrides
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virtual void video_start();
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virtual bool screen_update(screen_device &screen, bitmap_t &bitmap, const rectangle &cliprect);
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DECLARE_READ8_MEMBER( get_slave_ack );
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DECLARE_WRITE32_MEMBER( isa_ram1_w );
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DECLARE_WRITE32_MEMBER( isa_ram2_w );
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DECLARE_WRITE32_MEMBER( bios_ext1_ram_w );
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DECLARE_WRITE32_MEMBER( bios_ext2_ram_w );
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DECLARE_WRITE32_MEMBER( bios_ext3_ram_w );
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DECLARE_WRITE32_MEMBER( bios_ext4_ram_w );
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DECLARE_WRITE32_MEMBER( bios_ram_w );
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};
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void queen_state::video_start()
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{
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// Intel 82439TX System Controller (MXTC)
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static UINT8 mxtc_config_r(device_t *busdevice, device_t *device, int function, int reg)
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{
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queen_state *state = busdevice->machine().driver_data<queen_state>();
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// mame_printf_debug("MXTC: read %d, %02X\n", function, reg);
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return state->m_mxtc_config_reg[reg];
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}
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bool queen_state::screen_update(screen_device &screen, bitmap_t &bitmap, const rectangle &cliprect)
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static void mxtc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data)
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{
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return 0;
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queen_state *state = busdevice->machine().driver_data<queen_state>();
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printf("MXTC: write %d, %02X, %02X\n", function, reg, data);
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/*
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memory banking with North Bridge:
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0x59 (PAM0) xxxx ---- BIOS area 0xf0000-0xfffff
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---- xxxx Reserved
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0x5a (PAM1) xxxx ---- ISA add-on BIOS 0xc4000 - 0xc7fff
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---- xxxx ISA add-on BIOS 0xc0000 - 0xc3fff
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0x5b (PAM2) xxxx ---- ISA add-on BIOS 0xcc000 - 0xcffff
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---- xxxx ISA add-on BIOS 0xc8000 - 0xcbfff
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0x5c (PAM3) xxxx ---- ISA add-on BIOS 0xd4000 - 0xd7fff
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---- xxxx ISA add-on BIOS 0xd0000 - 0xd3fff
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0x5d (PAM4) xxxx ---- ISA add-on BIOS 0xdc000 - 0xdffff
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---- xxxx ISA add-on BIOS 0xd8000 - 0xdbfff
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0x5e (PAM5) xxxx ---- BIOS extension 0xe4000 - 0xe7fff
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---- xxxx BIOS extension 0xe0000 - 0xe3fff
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0x5f (PAM6) xxxx ---- BIOS extension 0xec000 - 0xeffff
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---- xxxx BIOS extension 0xe8000 - 0xebfff
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3210 -> 3 = reserved, 2 = Cache Enable, 1 = Write Enable, 0 = Read Enable
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*/
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switch(reg)
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{
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case 0x59: // PAM0
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{
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if (data & 0x10) // enable RAM access to region 0xf0000 - 0xfffff
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memory_set_bankptr(busdevice->machine(), "bios_bank", state->m_bios_ram);
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else // disable RAM access (reads go to BIOS ROM)
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memory_set_bankptr(busdevice->machine(), "bios_bank", busdevice->machine().region("bios")->base() + 0x10000);
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break;
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}
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case 0x5a: // PAM1
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{
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if (data & 0x1)
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memory_set_bankptr(busdevice->machine(), "video_bank1", state->m_isa_ram1);
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else
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memory_set_bankptr(busdevice->machine(), "video_bank1", busdevice->machine().region("video_bios")->base() + 0);
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if (data & 0x10)
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memory_set_bankptr(busdevice->machine(), "video_bank2", state->m_isa_ram2);
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else
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memory_set_bankptr(busdevice->machine(), "video_bank2", busdevice->machine().region("video_bios")->base() + 0x4000);
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break;
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}
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case 0x5e: // PAM5
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{
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if (data & 0x1)
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memory_set_bankptr(busdevice->machine(), "bios_ext1", state->m_bios_ext1_ram);
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else
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memory_set_bankptr(busdevice->machine(), "bios_ext1", busdevice->machine().region("bios")->base() + 0);
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if (data & 0x10)
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memory_set_bankptr(busdevice->machine(), "bios_ext2", state->m_bios_ext2_ram);
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else
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memory_set_bankptr(busdevice->machine(), "bios_ext2", busdevice->machine().region("bios")->base() + 0x4000);
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break;
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}
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case 0x5f: // PAM6
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{
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if (data & 0x1)
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memory_set_bankptr(busdevice->machine(), "bios_ext3", state->m_bios_ext3_ram);
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else
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memory_set_bankptr(busdevice->machine(), "bios_ext3", busdevice->machine().region("bios")->base() + 0x8000);
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if (data & 0x10)
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memory_set_bankptr(busdevice->machine(), "bios_ext4", state->m_bios_ext4_ram);
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else
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memory_set_bankptr(busdevice->machine(), "bios_ext4", busdevice->machine().region("bios")->base() + 0xc000);
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break;
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}
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}
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state->m_mxtc_config_reg[reg] = data;
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}
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static void intel82439tx_init(running_machine &machine)
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{
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queen_state *state = machine.driver_data<queen_state>();
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state->m_mxtc_config_reg[0x60] = 0x02;
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state->m_mxtc_config_reg[0x61] = 0x02;
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state->m_mxtc_config_reg[0x62] = 0x02;
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state->m_mxtc_config_reg[0x63] = 0x02;
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state->m_mxtc_config_reg[0x64] = 0x02;
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state->m_mxtc_config_reg[0x65] = 0x02;
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}
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static UINT32 intel82439tx_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask)
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{
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UINT32 r = 0;
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if (ACCESSING_BITS_24_31)
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{
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r |= mxtc_config_r(busdevice, device, function, reg + 3) << 24;
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}
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if (ACCESSING_BITS_16_23)
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{
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r |= mxtc_config_r(busdevice, device, function, reg + 2) << 16;
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}
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if (ACCESSING_BITS_8_15)
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{
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r |= mxtc_config_r(busdevice, device, function, reg + 1) << 8;
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}
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if (ACCESSING_BITS_0_7)
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{
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r |= mxtc_config_r(busdevice, device, function, reg + 0) << 0;
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}
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return r;
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}
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static void intel82439tx_pci_w(device_t *busdevice, device_t *device, int function, int reg, UINT32 data, UINT32 mem_mask)
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{
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if (ACCESSING_BITS_24_31)
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{
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mxtc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
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}
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if (ACCESSING_BITS_16_23)
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{
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mxtc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
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}
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if (ACCESSING_BITS_8_15)
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{
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mxtc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
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}
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if (ACCESSING_BITS_0_7)
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{
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mxtc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
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}
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}
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// Intel 82371AB PCI-to-ISA / IDE bridge (PIIX4)
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static UINT8 piix4_config_r(device_t *busdevice, device_t *device, int function, int reg)
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{
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queen_state *state = busdevice->machine().driver_data<queen_state>();
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// mame_printf_debug("PIIX4: read %d, %02X\n", function, reg);
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return state->m_piix4_config_reg[function][reg];
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}
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static void piix4_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data)
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{
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queen_state *state = busdevice->machine().driver_data<queen_state>();
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// mame_printf_debug("%s:PIIX4: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data);
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state->m_piix4_config_reg[function][reg] = data;
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}
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static UINT32 intel82371ab_pci_r(device_t *busdevice, device_t *device, int function, int reg, UINT32 mem_mask)
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{
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UINT32 r = 0;
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if (ACCESSING_BITS_24_31)
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{
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r |= piix4_config_r(busdevice, device, function, reg + 3) << 24;
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}
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if (ACCESSING_BITS_16_23)
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{
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r |= piix4_config_r(busdevice, device, function, reg + 2) << 16;
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}
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if (ACCESSING_BITS_8_15)
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{
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r |= piix4_config_r(busdevice, device, function, reg + 1) << 8;
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}
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if (ACCESSING_BITS_0_7)
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{
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r |= piix4_config_r(busdevice, device, function, reg + 0) << 0;
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}
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return r;
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}
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static void intel82371ab_pci_w(device_t *busdevice, device_t *device, int function, int reg, UINT32 data, UINT32 mem_mask)
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{
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if (ACCESSING_BITS_24_31)
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{
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piix4_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
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}
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if (ACCESSING_BITS_16_23)
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{
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piix4_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
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}
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if (ACCESSING_BITS_8_15)
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{
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piix4_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
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}
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if (ACCESSING_BITS_0_7)
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{
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piix4_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
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}
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}
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WRITE32_MEMBER(queen_state::isa_ram1_w)
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{
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if (m_mxtc_config_reg[0x5a] & 0x2) // write to RAM if this region is write-enabled
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{
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COMBINE_DATA(m_isa_ram1 + offset);
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}
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}
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WRITE32_MEMBER(queen_state::isa_ram2_w)
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{
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if (m_mxtc_config_reg[0x5a] & 0x2) // write to RAM if this region is write-enabled
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{
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COMBINE_DATA(m_isa_ram2 + offset);
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}
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}
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WRITE32_MEMBER(queen_state::bios_ext1_ram_w)
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{
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if (m_mxtc_config_reg[0x5e] & 0x2) // write to RAM if this region is write-enabled
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{
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COMBINE_DATA(m_bios_ext1_ram + offset);
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}
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}
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WRITE32_MEMBER(queen_state::bios_ext2_ram_w)
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{
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if (m_mxtc_config_reg[0x5e] & 0x20) // write to RAM if this region is write-enabled
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{
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COMBINE_DATA(m_bios_ext2_ram + offset);
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}
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}
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WRITE32_MEMBER(queen_state::bios_ext3_ram_w)
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{
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if (m_mxtc_config_reg[0x5f] & 0x2) // write to RAM if this region is write-enabled
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{
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COMBINE_DATA(m_bios_ext3_ram + offset);
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}
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}
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WRITE32_MEMBER(queen_state::bios_ext4_ram_w)
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{
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if (m_mxtc_config_reg[0x5f] & 0x20) // write to RAM if this region is write-enabled
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{
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COMBINE_DATA(m_bios_ext4_ram + offset);
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}
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}
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WRITE32_MEMBER(queen_state::bios_ram_w)
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{
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if (m_mxtc_config_reg[0x59] & 0x20) // write to RAM if this region is write-enabled
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{
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COMBINE_DATA(m_bios_ram + offset);
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}
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}
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static READ32_DEVICE_HANDLER( ide_r )
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{
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return ide_controller32_r(device, 0x1f0/4 + offset, mem_mask);
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}
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static WRITE32_DEVICE_HANDLER( ide_w )
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{
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ide_controller32_w(device, 0x1f0/4 + offset, data, mem_mask);
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}
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static READ32_DEVICE_HANDLER( fdc_r )
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{
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return ide_controller32_r(device, 0x3f0/4 + offset, mem_mask);
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}
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static WRITE32_DEVICE_HANDLER( fdc_w )
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{
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//mame_printf_debug("FDC: write %08X, %08X, %08X\n", data, offset, mem_mask);
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ide_controller32_w(device, 0x3f0/4 + offset, data, mem_mask);
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}
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static READ8_HANDLER(at_page8_r)
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{
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queen_state *state = space->machine().driver_data<queen_state>();
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UINT8 data = state->m_at_pages[offset % 0x10];
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switch(offset % 8) {
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case 1:
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data = state->m_dma_offset[(offset / 8) & 1][2];
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break;
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case 2:
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data = state->m_dma_offset[(offset / 8) & 1][3];
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break;
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case 3:
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data = state->m_dma_offset[(offset / 8) & 1][1];
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break;
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case 7:
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data = state->m_dma_offset[(offset / 8) & 1][0];
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break;
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}
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return data;
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}
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static WRITE8_HANDLER(at_page8_w)
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{
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queen_state *state = space->machine().driver_data<queen_state>();
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state->m_at_pages[offset % 0x10] = data;
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switch(offset % 8) {
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case 1:
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state->m_dma_offset[(offset / 8) & 1][2] = data;
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break;
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case 2:
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state->m_dma_offset[(offset / 8) & 1][3] = data;
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break;
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case 3:
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state->m_dma_offset[(offset / 8) & 1][1] = data;
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break;
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case 7:
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state->m_dma_offset[(offset / 8) & 1][0] = data;
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break;
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}
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}
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static READ32_HANDLER(at_page32_r)
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{
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return read32le_with_read8_handler(at_page8_r, space, offset, mem_mask);
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}
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|
||||
|
||||
static WRITE32_HANDLER(at_page32_w)
|
||||
{
|
||||
write32le_with_write8_handler(at_page8_w, space, offset, data, mem_mask);
|
||||
}
|
||||
|
||||
static READ8_DEVICE_HANDLER(at_dma8237_2_r)
|
||||
{
|
||||
return i8237_r(device, offset / 2);
|
||||
}
|
||||
|
||||
static WRITE8_DEVICE_HANDLER(at_dma8237_2_w)
|
||||
{
|
||||
i8237_w(device, offset / 2, data);
|
||||
}
|
||||
|
||||
static READ32_DEVICE_HANDLER(at32_dma8237_2_r)
|
||||
{
|
||||
return read32le_with_read8_device_handler(at_dma8237_2_r, device, offset, mem_mask);
|
||||
}
|
||||
|
||||
static WRITE32_DEVICE_HANDLER(at32_dma8237_2_w)
|
||||
{
|
||||
write32le_with_write8_device_handler(at_dma8237_2_w, device, offset, data, mem_mask);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dma_hrq_changed )
|
||||
{
|
||||
cputag_set_input_line(device->machine(), "maincpu", INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
|
||||
|
||||
/* Assert HLDA */
|
||||
i8237_hlda_w( device, state );
|
||||
}
|
||||
|
||||
|
||||
static READ8_HANDLER( pc_dma_read_byte )
|
||||
{
|
||||
queen_state *state = space->machine().driver_data<queen_state>();
|
||||
offs_t page_offset = (((offs_t) state->m_dma_offset[0][state->m_dma_channel]) << 16)
|
||||
& 0xFF0000;
|
||||
|
||||
return space->read_byte(page_offset + offset);
|
||||
}
|
||||
|
||||
|
||||
static WRITE8_HANDLER( pc_dma_write_byte )
|
||||
{
|
||||
queen_state *state = space->machine().driver_data<queen_state>();
|
||||
offs_t page_offset = (((offs_t) state->m_dma_offset[0][state->m_dma_channel]) << 16)
|
||||
& 0xFF0000;
|
||||
|
||||
space->write_byte(page_offset + offset, data);
|
||||
}
|
||||
|
||||
static void set_dma_channel(device_t *device, int channel, int state)
|
||||
{
|
||||
queen_state *drvstate = device->machine().driver_data<queen_state>();
|
||||
if (!state) drvstate->m_dma_channel = channel;
|
||||
}
|
||||
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack0_w ) { set_dma_channel(device, 0, state); }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack1_w ) { set_dma_channel(device, 1, state); }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack2_w ) { set_dma_channel(device, 2, state); }
|
||||
static WRITE_LINE_DEVICE_HANDLER( pc_dack3_w ) { set_dma_channel(device, 3, state); }
|
||||
|
||||
static I8237_INTERFACE( dma8237_1_config )
|
||||
{
|
||||
DEVCB_LINE(pc_dma_hrq_changed),
|
||||
DEVCB_NULL,
|
||||
DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_read_byte),
|
||||
DEVCB_MEMORY_HANDLER("maincpu", PROGRAM, pc_dma_write_byte),
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_LINE(pc_dack0_w), DEVCB_LINE(pc_dack1_w), DEVCB_LINE(pc_dack2_w), DEVCB_LINE(pc_dack3_w) }
|
||||
};
|
||||
|
||||
static I8237_INTERFACE( dma8237_2_config )
|
||||
{
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL,
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL },
|
||||
{ DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }
|
||||
};
|
||||
|
||||
static ADDRESS_MAP_START( queen_map, AS_PROGRAM, 32, queen_state )
|
||||
AM_RANGE(0x00000000, 0x0009ffff) AM_RAM
|
||||
AM_RANGE(0x000a0000, 0x000bffff) AM_RAM
|
||||
AM_RANGE(0x000c0000, 0x000fffff) AM_ROM AM_REGION("bios", 0) AM_WRITENOP
|
||||
AM_RANGE(0x000c0000, 0x000c3fff) AM_ROMBANK("video_bank1") AM_WRITE(isa_ram1_w)
|
||||
AM_RANGE(0x000c4000, 0x000c7fff) AM_ROMBANK("video_bank2") AM_WRITE(isa_ram2_w)
|
||||
AM_RANGE(0x000e0000, 0x000e3fff) AM_ROMBANK("bios_ext1") AM_WRITE(bios_ext1_ram_w)
|
||||
AM_RANGE(0x000e4000, 0x000e7fff) AM_ROMBANK("bios_ext2") AM_WRITE(bios_ext2_ram_w)
|
||||
AM_RANGE(0x000e8000, 0x000ebfff) AM_ROMBANK("bios_ext3") AM_WRITE(bios_ext3_ram_w)
|
||||
AM_RANGE(0x000ec000, 0x000effff) AM_ROMBANK("bios_ext4") AM_WRITE(bios_ext4_ram_w)
|
||||
AM_RANGE(0x000f0000, 0x000fffff) AM_ROMBANK("bios_bank") AM_WRITE(bios_ram_w)
|
||||
AM_RANGE(0x00100000, 0x01ffffff) AM_RAM
|
||||
AM_RANGE(0x10000000, 0x100001ff) AM_RAM
|
||||
AM_RANGE(0x20000000, 0x200001ff) AM_RAM
|
||||
AM_RANGE(0x30000000, 0x300001ff) AM_RAM
|
||||
AM_RANGE(0x40000000, 0x400001ff) AM_RAM
|
||||
AM_RANGE(0x50000000, 0x500001ff) AM_RAM
|
||||
AM_RANGE(0xfffc0000, 0xffffffff) AM_ROM AM_REGION("bios", 0) /* System BIOS */
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( queen_io, AS_IO, 32, queen_state )
|
||||
AM_RANGE(0x0000, 0x001f) AM_RAM//AM_DEVREADWRITE8("dma8237_1", dma8237_r, dma8237_w, 0xffffffff)
|
||||
AM_RANGE(0x0020, 0x003f) AM_RAM//AM_DEVREADWRITE8("pic8259_1", pic8259_r, pic8259_w, 0xffffffff)
|
||||
AM_RANGE(0x0040, 0x005f) AM_RAM//AM_DEVREADWRITE8("pit8254", pit8253_r, pit8253_w, 0xffffffff)
|
||||
AM_RANGE(0x0060, 0x006f) AM_RAM//AM_READWRITE(kbdc8042_32le_r, kbdc8042_32le_w)
|
||||
AM_RANGE(0x0070, 0x007f) AM_RAM//AM_DEVREADWRITE8_MODERN("rtc", mc146818_device, read, write, 0xffffffff)
|
||||
AM_RANGE(0x0080, 0x009f) AM_RAM//AM_READWRITE(at_page32_r, at_page32_w)
|
||||
AM_RANGE(0x00a0, 0x00bf) AM_RAM//AM_DEVREADWRITE8("pic8259_2", pic8259_r, pic8259_w, 0xffffffff)
|
||||
AM_RANGE(0x00c0, 0x00df) AM_RAM//AM_DEVREADWRITE("dma8237_2", at32_dma8237_2_r, at32_dma8237_2_w)
|
||||
AM_RANGE(0x00e8, 0x00eb) AM_NOP
|
||||
AM_RANGE(0x01f0, 0x01f7) AM_RAM//AM_DEVREADWRITE("ide", ide_r, ide_w)
|
||||
AM_RANGE(0x0300, 0x03af) AM_NOP
|
||||
AM_RANGE(0x03b0, 0x03df) AM_NOP
|
||||
AM_RANGE(0x0278, 0x027b) AM_WRITENOP//AM_WRITE(pnp_config_w)
|
||||
AM_RANGE(0x03f0, 0x03ff) AM_RAM//AM_DEVREADWRITE("ide", fdc_r, fdc_w)
|
||||
AM_RANGE(0x0a78, 0x0a7b) AM_WRITENOP//AM_WRITE(pnp_data_w)
|
||||
AM_RANGE(0x0cf8, 0x0cff) AM_RAM//AM_DEVREADWRITE("pcibus", pci_32le_r, pci_32le_w)
|
||||
AM_RANGE(0x4004, 0x4007) AM_RAM // - todo: identify these two.
|
||||
AM_RANGE(0x5000, 0x5007) AM_RAM // /
|
||||
AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8_LEGACY("dma8237_1", i8237_r, i8237_w, 0xffffffff)
|
||||
AM_RANGE(0x0020, 0x003f) AM_DEVREADWRITE8_LEGACY("pic8259_1", pic8259_r, pic8259_w, 0xffffffff)
|
||||
AM_RANGE(0x0040, 0x005f) AM_DEVREADWRITE8_LEGACY("pit8254", pit8253_r, pit8253_w, 0xffffffff)
|
||||
AM_RANGE(0x0060, 0x006f) AM_READWRITE_LEGACY(kbdc8042_32le_r, kbdc8042_32le_w)
|
||||
AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE8("rtc", mc146818_device, read, write, 0xffffffff) /* todo: nvram (CMOS Setup Save)*/
|
||||
AM_RANGE(0x0080, 0x009f) AM_READWRITE_LEGACY(at_page32_r, at_page32_w)
|
||||
AM_RANGE(0x00a0, 0x00bf) AM_DEVREADWRITE8_LEGACY("pic8259_2", pic8259_r, pic8259_w, 0xffffffff)
|
||||
AM_RANGE(0x00c0, 0x00df) AM_DEVREADWRITE_LEGACY("dma8237_2", at32_dma8237_2_r, at32_dma8237_2_w)
|
||||
AM_RANGE(0x00e8, 0x00ef) AM_NOP
|
||||
|
||||
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE_LEGACY("ide", ide_r, ide_w)
|
||||
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE_LEGACY("ide", fdc_r, fdc_w)
|
||||
|
||||
AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE_LEGACY("pcibus", pci_32le_r, pci_32le_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static const struct pit8253_config queen_pit8254_config =
|
||||
{
|
||||
{
|
||||
{
|
||||
4772720/4, /* heartbeat IRQ */
|
||||
DEVCB_NULL,
|
||||
DEVCB_DEVICE_LINE("pic8259_1", pic8259_ir0_w)
|
||||
}, {
|
||||
4772720/4, /* dram refresh */
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL
|
||||
}, {
|
||||
4772720/4, /* pio port c pin 4, and speaker polling enough */
|
||||
DEVCB_NULL,
|
||||
DEVCB_NULL
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
static WRITE_LINE_DEVICE_HANDLER( queen_pic8259_1_set_int_line )
|
||||
{
|
||||
queen_state *drvstate = device->machine().driver_data<queen_state>();
|
||||
device_set_input_line(drvstate->m_maincpu, 0, state ? HOLD_LINE : CLEAR_LINE);
|
||||
}
|
||||
|
||||
READ8_MEMBER( queen_state::get_slave_ack )
|
||||
{
|
||||
if (offset==2) { // IRQ = 2
|
||||
logerror("pic8259_slave_ACK!\n");
|
||||
return pic8259_acknowledge(m_pic8259_2);
|
||||
}
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
static const struct pic8259_interface queen_pic8259_1_config =
|
||||
{
|
||||
DEVCB_LINE(queen_pic8259_1_set_int_line),
|
||||
DEVCB_LINE_VCC,
|
||||
DEVCB_MEMBER(queen_state,get_slave_ack)
|
||||
};
|
||||
|
||||
static const struct pic8259_interface queen_pic8259_2_config =
|
||||
{
|
||||
DEVCB_DEVICE_LINE("pic8259_1", pic8259_ir2_w),
|
||||
DEVCB_LINE_GND,
|
||||
DEVCB_NULL
|
||||
};
|
||||
|
||||
static void set_gate_a20(running_machine &machine, int a20)
|
||||
{
|
||||
queen_state *state = machine.driver_data<queen_state>();
|
||||
|
||||
device_set_input_line(state->m_maincpu, INPUT_LINE_A20, a20);
|
||||
}
|
||||
|
||||
static void keyboard_interrupt(running_machine &machine, int state)
|
||||
{
|
||||
queen_state *drvstate = machine.driver_data<queen_state>();
|
||||
pic8259_ir1_w(drvstate->m_pic8259_1, state);
|
||||
}
|
||||
|
||||
static int queen_get_out2(running_machine &machine)
|
||||
{
|
||||
queen_state *state = machine.driver_data<queen_state>();
|
||||
return pit8253_get_output(state->m_pit8254, 2 );
|
||||
}
|
||||
|
||||
static const struct kbdc8042_interface at8042 =
|
||||
{
|
||||
KBDC8042_AT386, set_gate_a20, keyboard_interrupt, NULL, queen_get_out2
|
||||
};
|
||||
|
||||
static void queen_set_keyb_int(running_machine &machine, int state)
|
||||
{
|
||||
queen_state *drvstate = machine.driver_data<queen_state>();
|
||||
pic8259_ir1_w(drvstate->m_pic8259_1, state);
|
||||
}
|
||||
|
||||
static IRQ_CALLBACK(irq_callback)
|
||||
{
|
||||
queen_state *state = device->machine().driver_data<queen_state>();
|
||||
return pic8259_acknowledge( state->m_pic8259_1);
|
||||
}
|
||||
|
||||
static void ide_interrupt(device_t *device, int state)
|
||||
{
|
||||
queen_state *drvstate = device->machine().driver_data<queen_state>();
|
||||
pic8259_ir6_w(drvstate->m_pic8259_2, state);
|
||||
}
|
||||
|
||||
static READ8_HANDLER( vga_setting ) { return 0xff; } // hard-code to color
|
||||
|
||||
static const struct pc_vga_interface vga_interface =
|
||||
{
|
||||
NULL,
|
||||
NULL,
|
||||
vga_setting,
|
||||
AS_PROGRAM,
|
||||
0xa0000,
|
||||
AS_IO,
|
||||
0x0000
|
||||
};
|
||||
|
||||
static MACHINE_START( queen )
|
||||
{
|
||||
queen_state *state = machine.driver_data<queen_state>();
|
||||
|
||||
state->m_bios_ram = auto_alloc_array(machine, UINT32, 0x10000/4);
|
||||
state->m_bios_ext1_ram = auto_alloc_array(machine, UINT32, 0x4000/4);
|
||||
state->m_bios_ext2_ram = auto_alloc_array(machine, UINT32, 0x4000/4);
|
||||
state->m_bios_ext3_ram = auto_alloc_array(machine, UINT32, 0x4000/4);
|
||||
state->m_bios_ext4_ram = auto_alloc_array(machine, UINT32, 0x4000/4);
|
||||
state->m_isa_ram1 = auto_alloc_array(machine, UINT32, 0x4000/4);
|
||||
state->m_isa_ram2 = auto_alloc_array(machine, UINT32, 0x4000/4);
|
||||
|
||||
init_pc_common(machine, PCCOMMON_KEYBOARD_AT, queen_set_keyb_int);
|
||||
|
||||
device_set_irq_callback(state->m_maincpu, irq_callback);
|
||||
intel82439tx_init(machine);
|
||||
|
||||
kbdc8042_init(machine, &at8042);
|
||||
pc_vga_init(machine, &vga_interface, NULL);
|
||||
}
|
||||
|
||||
static MACHINE_RESET( queen )
|
||||
{
|
||||
memory_set_bankptr(machine, "bios_bank", machine.region("bios")->base() + 0x30000);
|
||||
memory_set_bankptr(machine, "bios_ext1", machine.region("bios")->base() + 0x20000);
|
||||
memory_set_bankptr(machine, "bios_ext2", machine.region("bios")->base() + 0x24000);
|
||||
memory_set_bankptr(machine, "bios_ext3", machine.region("bios")->base() + 0x28000);
|
||||
memory_set_bankptr(machine, "bios_ext4", machine.region("bios")->base() + 0x2c000);
|
||||
memory_set_bankptr(machine, "video_bank1", machine.region("video_bios")->base() + 0);
|
||||
memory_set_bankptr(machine, "video_bank2", machine.region("video_bios")->base() + 0x4000);
|
||||
}
|
||||
|
||||
|
||||
|
||||
static INPUT_PORTS_START( queen )
|
||||
INPUT_PORTS_END
|
||||
|
||||
|
||||
static MACHINE_CONFIG_START( queen, queen_state )
|
||||
MCFG_CPU_ADD("maincpu", PENTIUM, 533000000) // Celeron or Pentium 3, 533 Mhz
|
||||
MCFG_CPU_ADD("maincpu", PENTIUM, 533000000/16) // Celeron or Pentium 3, 533 Mhz
|
||||
MCFG_CPU_PROGRAM_MAP(queen_map)
|
||||
MCFG_CPU_IO_MAP(queen_io)
|
||||
|
||||
MCFG_SCREEN_ADD("screen", RASTER)
|
||||
MCFG_SCREEN_REFRESH_RATE(60)
|
||||
MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
|
||||
MCFG_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
|
||||
MCFG_SCREEN_SIZE(64*8, 32*8)
|
||||
MCFG_SCREEN_VISIBLE_AREA(0*8, 64*8-1, 0*8, 32*8-1)
|
||||
MCFG_MACHINE_START(queen)
|
||||
MCFG_MACHINE_RESET(queen)
|
||||
|
||||
MCFG_PALETTE_LENGTH(0x200)
|
||||
MCFG_PIT8254_ADD( "pit8254", queen_pit8254_config )
|
||||
MCFG_I8237_ADD( "dma8237_1", XTAL_14_31818MHz/3, dma8237_1_config )
|
||||
MCFG_I8237_ADD( "dma8237_2", XTAL_14_31818MHz/3, dma8237_2_config )
|
||||
MCFG_PIC8259_ADD( "pic8259_1", queen_pic8259_1_config )
|
||||
MCFG_PIC8259_ADD( "pic8259_2", queen_pic8259_2_config )
|
||||
|
||||
MCFG_MC146818_ADD( "rtc", MC146818_STANDARD )
|
||||
|
||||
MCFG_PCI_BUS_ADD("pcibus", 0)
|
||||
MCFG_PCI_BUS_DEVICE(0, NULL, intel82439tx_pci_r, intel82439tx_pci_w)
|
||||
MCFG_PCI_BUS_DEVICE(7, NULL, intel82371ab_pci_r, intel82371ab_pci_w)
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_interrupt)
|
||||
|
||||
/* video hardware */
|
||||
MCFG_FRAGMENT_ADD( pcvideo_vga )
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
@ -115,9 +724,13 @@ ROM_START( queen )
|
||||
ROM_REGION( 0x40000, "bios", 0 )
|
||||
ROM_LOAD( "bios-original.bin", 0x00000, 0x40000, CRC(feb542d4) SHA1(3cc5d8aeb0e3b7d9ed33248a4f3dc507d29debd9) )
|
||||
|
||||
ROM_REGION( 0x8000, "video_bios", ROMREGION_ERASEFF ) // TODO: no VGA card is hooked up, to be removed
|
||||
// ROM_LOAD16_BYTE( "trident_tgui9680_bios.bin", 0x0000, 0x4000, BAD_DUMP CRC(1eebde64) SHA1(67896a854d43a575037613b3506aea6dae5d6a19) )
|
||||
// ROM_CONTINUE( 0x0001, 0x4000 )
|
||||
|
||||
DISK_REGION( "ide" )
|
||||
DISK_IMAGE( "pqiidediskonmodule", 0,SHA1(a56efcc711b1c5a2e63160b3088001a8c4fb56c2) )
|
||||
ROM_END
|
||||
|
||||
|
||||
GAME( 2002?, queen, 0, queen, queen, 0, ROT0, "STG", "Queen?", GAME_IS_SKELETON )
|
||||
GAME( 2002?, queen, 0, queen, at_keyboard, 0, ROT0, "STG", "Queen?", GAME_IS_SKELETON )
|
||||
|
||||
@ -100,9 +100,6 @@ public:
|
||||
DECLARE_WRITE32_MEMBER( bios_ext4_ram_w );
|
||||
|
||||
DECLARE_WRITE32_MEMBER( bios_ram_w );
|
||||
|
||||
|
||||
protected:
|
||||
};
|
||||
|
||||
// Intel 82439TX System Controller (MXTC)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user