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Cleanups/version bump.

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This commit is contained in:
Aaron Giles 2008-11-09 01:04:37 +00:00
parent ac7689264e
commit 1e16c45212
33 changed files with 237 additions and 237 deletions
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10
src/emu/cpu/adsp2100/adsp2100.c
View File

@ -249,7 +249,7 @@ typedef struct
int chip_type;
int mstat_mask;
int imask_mask;
/* register maps */
void * alu_xregs[8];
void * alu_yregs[4];
@ -577,7 +577,7 @@ static CPU_SET_CONTEXT( adsp21xx )
static adsp2100_state *adsp21xx_init(const device_config *device, int index, int clock, const void *config, cpu_irq_callback irqcallback)
{
adsp2100_state *adsp = device->token;
token = device->token; // temporary
/* create the tables */
@ -587,7 +587,7 @@ static adsp2100_state *adsp21xx_init(const device_config *device, int index, int
/* set the IRQ callback */
adsp->irq_callback = irqcallback;
adsp->device = device;
/* set up ALU register pointers */
adsp->alu_xregs[0] = &adsp->core.ax0;
adsp->alu_xregs[1] = &adsp->core.ax1;
@ -601,7 +601,7 @@ static adsp2100_state *adsp21xx_init(const device_config *device, int index, int
adsp->alu_yregs[1] = &adsp->core.ay1;
adsp->alu_yregs[2] = &adsp->core.af;
adsp->alu_yregs[3] = &adsp->core.zero;
/* set up MAC register pointers */
adsp->mac_xregs[0] = &adsp->core.mx0;
adsp->mac_xregs[1] = &adsp->core.mx1;
@ -706,7 +706,7 @@ static adsp2100_state *adsp21xx_init(const device_config *device, int index, int
state_save_register_item("adsp2100", index, adsp->ifc);
state_save_register_item_array("adsp2100", index, adsp->irq_state);
state_save_register_item_array("adsp2100", index, adsp->irq_latch);
return adsp;
}

2
src/emu/cpu/dsp32/dsp32.c
View File

@ -354,7 +354,7 @@ static CPU_INIT( dsp32c )
/* copy in config data */
if (configdata)
dsp32.output_pins_changed = configdata->output_pins_changed;
dsp32.device = device;
}

8
src/emu/cpu/dsp56k/dsp56dsm.c
View File

@ -344,10 +344,10 @@ CPU_DISASSEMBLE( dsp56k )
/* Now check it against all the other potential collisions */
/* This is necessary because "don't care bits" get in the way. */
/*
MOVE(M) : 0000 0101 BBBB BBBB 0000 001W --0- -HHH : A-152
MOVE(C) : 0000 0101 BBBB BBBB 0011 1WDD DDD0 ---- : A-144
MOVE : 0000 0101 BBBB BBBB ---- HHHW 0001 0001 : A-128
*/
MOVE(M) : 0000 0101 BBBB BBBB 0000 001W --0- -HHH : A-152
MOVE(C) : 0000 0101 BBBB BBBB 0011 1WDD DDD0 ---- : A-144
MOVE : 0000 0101 BBBB BBBB ---- HHHW 0001 0001 : A-128
*/
if (((op2 & 0xfe20) != 0x0200) &&
((op2 & 0xf810) != 0x3800) &&
((op2 & 0x00ff) != 0x0011))

60
src/emu/cpu/dsp56k/dsp56ops.c
View File

@ -367,10 +367,10 @@ static void execute_one(void)
/* Now check it against all the other potential collisions */
/* This is necessary because "don't care bits" get in the way. */
/*
MOVE(M) : 0000 0101 BBBB BBBB 0000 001W --0- -HHH : A-152
MOVE(C) : 0000 0101 BBBB BBBB 0011 1WDD DDD0 ---- : A-144
MOVE : 0000 0101 BBBB BBBB ---- HHHW 0001 0001 : A-128
*/
MOVE(M) : 0000 0101 BBBB BBBB 0000 001W --0- -HHH : A-152
MOVE(C) : 0000 0101 BBBB BBBB 0011 1WDD DDD0 ---- : A-144
MOVE : 0000 0101 BBBB BBBB ---- HHHW 0001 0001 : A-128
*/
if (((op2 & 0xfe20) != 0x0200) &&
((op2 & 0xf810) != 0x3800) &&
((op2 & 0x00ff) != 0x0011))
@ -1821,7 +1821,7 @@ static size_t dsp56k_op_cmpm(const UINT16 op_byte, typed_pointer* d_register, UI
typed_pointer S = {NULL, DT_BYTE};
typed_pointer D = {NULL, DT_BYTE};
decode_JJJF_table(BITS(op_byte,0x0007),BITS(op_byte,0x0008), &S, &D);
decode_JJJF_table(BITS(op_byte,0x0007),BITS(op_byte,0x0008), &S, &D);
*p_accum = *((UINT64*)D.addr);
@ -1833,7 +1833,7 @@ static size_t dsp56k_op_cmpm(const UINT16 op_byte, typed_pointer* d_register, UI
absS |= U64(0xffffff8000000000);
}
else
{
{
absS = (*((UINT16*)S.addr)) << 16;
if (absS & U64(0x0000000080000000))
absS |= U64(0xffffffff80000000);
@ -1842,13 +1842,13 @@ static size_t dsp56k_op_cmpm(const UINT16 op_byte, typed_pointer* d_register, UI
/* Sign extend and get absolute value of the destination */
if (D.addr == &A || D.addr == &B)
{
{
absD = *((UINT64*)D.addr);
if (absD & U64(0x0000008000000000))
absD |= U64(0xffffff8000000000);
}
else
{
{
absD = (*((UINT16*)D.addr)) << 16;
if (absS & U64(0x0000000080000000))
absS |= U64(0xffffffff80000000);
@ -4032,64 +4032,64 @@ static void decode_uuuuF_table(UINT16 uuuu, UINT16 F, UINT8 add_sub_other, typed
switch(switchVal)
{
case 0x00: add_sub_other = OP_ADD;
case 0x00: add_sub_other = OP_ADD;
src_ret->addr = &X0; src_ret->data_type = DT_WORD;
dst_ret->addr = &A; dst_ret->data_type = DT_LONG_WORD; break;
case 0x08: add_sub_other = OP_SUB;
case 0x08: add_sub_other = OP_SUB;
src_ret->addr = &X0; src_ret->data_type = DT_WORD;
dst_ret->addr = &A; dst_ret->data_type = DT_LONG_WORD; break;
case 0x01: add_sub_other = OP_ADD;
case 0x01: add_sub_other = OP_ADD;
src_ret->addr = &X0; src_ret->data_type = DT_WORD;
dst_ret->addr = &B; dst_ret->data_type = DT_LONG_WORD; break;
case 0x09: add_sub_other = OP_SUB;
case 0x09: add_sub_other = OP_SUB;
src_ret->addr = &X0; src_ret->data_type = DT_WORD;
dst_ret->addr = &B; dst_ret->data_type = DT_LONG_WORD; break;
case 0x02: add_sub_other = OP_ADD;
case 0x02: add_sub_other = OP_ADD;
src_ret->addr = &Y0; src_ret->data_type = DT_WORD;
dst_ret->addr = &A; dst_ret->data_type = DT_LONG_WORD; break;
case 0x0a: add_sub_other = OP_SUB;
case 0x0a: add_sub_other = OP_SUB;
src_ret->addr = &Y0; src_ret->data_type = DT_WORD;
dst_ret->addr = &A; dst_ret->data_type = DT_LONG_WORD; break;
case 0x03: add_sub_other = OP_ADD;
case 0x03: add_sub_other = OP_ADD;
src_ret->addr = &Y0; src_ret->data_type = DT_WORD;
dst_ret->addr = &B; dst_ret->data_type = DT_LONG_WORD; break;
case 0x0b: add_sub_other = OP_SUB;
case 0x0b: add_sub_other = OP_SUB;
src_ret->addr = &Y0; src_ret->data_type = DT_WORD;
dst_ret->addr = &B; dst_ret->data_type = DT_LONG_WORD; break;
case 0x04: add_sub_other = OP_ADD;
case 0x04: add_sub_other = OP_ADD;
src_ret->addr = &X1; src_ret->data_type = DT_WORD;
dst_ret->addr = &A; dst_ret->data_type = DT_LONG_WORD; break;
case 0x0c: add_sub_other = OP_SUB;
case 0x0c: add_sub_other = OP_SUB;
src_ret->addr = &X1; src_ret->data_type = DT_WORD;
dst_ret->addr = &A; dst_ret->data_type = DT_LONG_WORD; break;
case 0x05: add_sub_other = OP_ADD;
case 0x05: add_sub_other = OP_ADD;
src_ret->addr = &X1; src_ret->data_type = DT_WORD;
dst_ret->addr = &B; dst_ret->data_type = DT_LONG_WORD; break;
case 0x0d: add_sub_other = OP_SUB;
case 0x0d: add_sub_other = OP_SUB;
src_ret->addr = &X1; src_ret->data_type = DT_WORD;
dst_ret->addr = &B; dst_ret->data_type = DT_LONG_WORD; break;
case 0x06: add_sub_other = OP_ADD;
case 0x06: add_sub_other = OP_ADD;
src_ret->addr = &Y1; src_ret->data_type = DT_WORD;
dst_ret->addr = &A; dst_ret->data_type = DT_LONG_WORD; break;
case 0x0e: add_sub_other = OP_SUB;
case 0x0e: add_sub_other = OP_SUB;
src_ret->addr = &Y1; src_ret->data_type = DT_WORD;
dst_ret->addr = &A; dst_ret->data_type = DT_LONG_WORD; break;
case 0x07: add_sub_other = OP_ADD;
case 0x07: add_sub_other = OP_ADD;
src_ret->addr = &Y1; src_ret->data_type = DT_WORD;
dst_ret->addr = &B; dst_ret->data_type = DT_LONG_WORD; break;
case 0x0f: add_sub_other = OP_SUB;
case 0x0f: add_sub_other = OP_SUB;
src_ret->addr = &Y1; src_ret->data_type = DT_WORD;
dst_ret->addr = &B; dst_ret->data_type = DT_LONG_WORD; break;
case 0x18: add_sub_other = OP_ADD;
case 0x18: add_sub_other = OP_ADD;
src_ret->addr = &B; src_ret->data_type = DT_LONG_WORD;
dst_ret->addr = &A; dst_ret->data_type = DT_LONG_WORD; break;
case 0x1a: add_sub_other = OP_SUB;
case 0x1a: add_sub_other = OP_SUB;
src_ret->addr = &B; src_ret->data_type = DT_LONG_WORD;
dst_ret->addr = &A; dst_ret->data_type = DT_LONG_WORD; break;
case 0x19: add_sub_other = OP_ADD;
case 0x19: add_sub_other = OP_ADD;
src_ret->addr = &A; src_ret->data_type = DT_LONG_WORD;
dst_ret->addr = &B; dst_ret->data_type = DT_LONG_WORD; break;
case 0x1b: add_sub_other = OP_SUB;
case 0x1b: add_sub_other = OP_SUB;
src_ret->addr = &A; src_ret->data_type = DT_LONG_WORD;
dst_ret->addr = &B; dst_ret->data_type = DT_LONG_WORD; break;
}
@ -4458,8 +4458,8 @@ static void execute_dual_x_memory_data_read(const UINT16 op, typed_pointer* d_re
if (R.addr == &R3)
fatalerror("Dsp56k: Error. Dual x memory data read specified R3 as its first source!");
/* The note on A-142 is very interesting.
You can effectively access external memory in the last 64 bytes of X data memory! */
/* The note on A-142 is very interesting.
You can effectively access external memory in the last 64 bytes of X data memory! */
if (*((UINT16*)D2.addr) >= 0xffc0)
fatalerror("Dsp56k: Unimplemented access to external X Data Memory >= 0xffc0 in Dual X Memory Data Read.");

26
src/emu/cpu/m6502/m4510.c
View File

@ -141,11 +141,11 @@ struct _m4510_Regs {
UINT8 irq_state;
UINT16 low, high;
UINT32 mem[8];
cpu_irq_callback irq_callback;
const device_config *device;
int icount;
read8_machine_func rdmem_id; /* readmem callback for indexed instructions */
write8_machine_func wrmem_id; /* writemem callback for indexed instructions */
@ -179,20 +179,20 @@ INLINE int m4510_cpu_readop_arg(m4510_Regs *m4510)
static READ8_HANDLER( default_rdmem_id )
{
m4510_Regs *m4510 = token;
return program_read_byte_8le(M4510_MEM(offset));
return program_read_byte_8le(M4510_MEM(offset));
}
static WRITE8_HANDLER( default_wrmem_id )
static WRITE8_HANDLER( default_wrmem_id )
{
m4510_Regs *m4510 = token;
program_write_byte_8le(M4510_MEM(offset), data);
program_write_byte_8le(M4510_MEM(offset), data);
}
static CPU_INIT( m4510 )
{
m4510_Regs *m4510 = device->token;
token = device->token;
m4510->interrupt_inhibit = 0;
m4510->rdmem_id = default_rdmem_id;
m4510->wrmem_id = default_wrmem_id;
@ -203,7 +203,7 @@ static CPU_INIT( m4510 )
static CPU_RESET( m4510 )
{
m4510_Regs *m4510 = device->token;
m4510->insn = insn4510;
/* wipe out the rest of the m65ce02 structure */
@ -276,7 +276,7 @@ INLINE void m4510_take_irq(m4510_Regs *m4510)
static CPU_EXECUTE( m4510 )
{
m4510_Regs *m4510 = token;
m4510->icount = cycles;
CHANGE_PC;
@ -378,7 +378,7 @@ static READ8_HANDLER( m4510_read_0000 )
static WRITE8_HANDLER( m4510_write_0000 )
{
m4510_Regs *m4510 = token;
switch(offset)
{
case 0x0000: /* DDR */
@ -400,7 +400,7 @@ ADDRESS_MAP_END
static CPU_TRANSLATE( m4510 )
{
m4510_Regs *m4510 = token;
if (space == ADDRESS_SPACE_PROGRAM)
*address = M4510_MEM(*address);
return TRUE;
@ -413,7 +413,7 @@ static CPU_TRANSLATE( m4510 )
static CPU_SET_INFO( m4510 )
{
m4510_Regs *m4510 = token;
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
@ -460,7 +460,7 @@ static CPU_SET_INFO( m4510 )
CPU_GET_INFO( m4510 )
{
m4510_Regs *m4510 = token;
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */

30
src/emu/cpu/m6502/m6502.c
View File

@ -137,7 +137,7 @@ static void m6502_common_init(const device_config *device, int index, int clock,
m6502_Regs *m6502 = device->token;
token = device->token; // temporary
m6502->irq_callback = irqcallback;
m6502->device = device;
m6502->subtype = subtype;
@ -201,7 +201,7 @@ static CPU_GET_CONTEXT( m6502 )
static CPU_SET_CONTEXT( m6502 )
{
m6502_Regs *m6502;
if( src )
{
token = src;
@ -233,7 +233,7 @@ INLINE void m6502_take_irq(m6502_Regs *m6502)
static CPU_EXECUTE( m6502 )
{
m6502_Regs *m6502 = device->token;
m6502->icount = cycles;
change_pc(PCD);
@ -367,7 +367,7 @@ static CPU_INIT( m6510 )
static CPU_RESET( m6510 )
{
m6502_Regs *m6502 = device->token;
CPU_RESET_CALL(m6502);
m6502->port = 0xff;
m6502->ddr = 0x00;
@ -400,7 +400,7 @@ static READ8_HANDLER( m6510_read_0000 )
static WRITE8_HANDLER( m6510_write_0000 )
{
m6502_Regs *m6502 = token;
switch(offset)
{
case 0x0000: /* DDR */
@ -435,7 +435,7 @@ static CPU_INIT( m65c02 )
static CPU_RESET( m65c02 )
{
m6502_Regs *m6502 = device->token;
CPU_RESET_CALL(m6502);
P &=~F_D;
}
@ -463,7 +463,7 @@ INLINE void m65c02_take_irq(m6502_Regs *m6502)
static CPU_EXECUTE( m65c02 )
{
m6502_Regs *m6502 = device->token;
m6502->icount = cycles;
change_pc(PCD);
@ -557,7 +557,7 @@ static CPU_INIT( deco16 )
static CPU_RESET( deco16 )
{
m6502_Regs *m6502 = device->token;
CPU_RESET_CALL(m6502);
m6502->subtype = SUBTYPE_DECO16;
m6502->insn = insndeco16;
@ -638,7 +638,7 @@ static void deco16_set_irq_line(m6502_Regs *m6502, int irqline, int state)
static CPU_EXECUTE( deco16 )
{
m6502_Regs *m6502 = device->token;
m6502->icount = cycles;
change_pc(PCD);
@ -693,7 +693,7 @@ static CPU_EXECUTE( deco16 )
static CPU_SET_INFO( m6502 )
{
m6502_Regs *m6502 = token;
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
@ -727,7 +727,7 @@ static CPU_SET_INFO( m6502 )
CPU_GET_INFO( m6502 )
{
m6502_Regs *m6502 = token;
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
@ -844,7 +844,7 @@ CPU_GET_INFO( n2a03 )
static CPU_SET_INFO( m6510 )
{
m6502_Regs *m6502 = token;
switch (state)
{
/* --- the following bits of info are set as pointers to data or functions --- */
@ -858,7 +858,7 @@ static CPU_SET_INFO( m6510 )
CPU_GET_INFO( m6510 )
{
m6502_Regs *m6502 = token;
switch (state)
{
/* --- the following bits of info are returned as pointers to data or functions --- */
@ -944,7 +944,7 @@ CPU_GET_INFO( m8502 )
static CPU_SET_INFO( m65c02 )
{
m6502_Regs *m6502 = token;
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
@ -1008,7 +1008,7 @@ CPU_GET_INFO( m65sc02 )
static CPU_SET_INFO( deco16 )
{
m6502_Regs *m6502 = token;
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */

24
src/emu/cpu/m6502/m6509.c
View File

@ -97,14 +97,14 @@ static void *token;
static READ8_HANDLER( m6509_read_00000 )
{
m6509_Regs *m6509 = token;
return m6509->pc_bank.b.h2;
}
static READ8_HANDLER( m6509_read_00001 )
{
m6509_Regs *m6509 = token;
return m6509->ind_bank.b.h2;
}
@ -112,7 +112,7 @@ static WRITE8_HANDLER( m6509_write_00000 )
{
m6509_Regs *m6509 = token;
m6509_Regs *m6502 = m6509;
m6509->pc_bank.b.h2=data&0xf;
m6509->pc.w.h=m6509->pc_bank.w.h;
change_pc(PCD);
@ -122,7 +122,7 @@ static WRITE8_HANDLER( m6509_write_00000 )
static WRITE8_HANDLER( m6509_write_00001 )
{
m6509_Regs *m6509 = token;
m6509->ind_bank.b.h2=data&0xf;
}
@ -137,9 +137,9 @@ static WRITE8_HANDLER( default_wdmem_id ) { program_write_byte_8le(offset, data)
static CPU_INIT( m6509 )
{
m6509_Regs *m6509 = device->token;
token = device->token; // temporary
m6509->rdmem_id = default_rdmem_id;
m6509->wrmem_id = default_wdmem_id;
m6509->irq_callback = irqcallback;
@ -150,7 +150,7 @@ static CPU_RESET( m6509 )
{
m6509_Regs *m6509 = device->token;
m6509_Regs *m6502 = m6509;
m6509->insn = insn6509;
m6509->pc_bank.d=m6509->ind_bank.d=0;
@ -182,7 +182,7 @@ static CPU_GET_CONTEXT( m6509 )
static CPU_SET_CONTEXT( m6509 )
{
m6509_Regs *m6502;
if( src )
{
token = src;
@ -219,7 +219,7 @@ static CPU_EXECUTE( m6509 )
{
m6509_Regs *m6502 = device->token;
m6509_Regs *m6509 = m6502;
m6502->icount = cycles;
change_pc(PCD);
@ -265,7 +265,7 @@ static CPU_EXECUTE( m6509 )
static void m6509_set_irq_line(m6509_Regs *m6509, int irqline, int state)
{
m6509_Regs *m6502 = m6509;
if (irqline == INPUT_LINE_NMI)
{
if (m6509->nmi_state == state) return;
@ -315,7 +315,7 @@ static CPU_SET_INFO( m6509 )
{
m6509_Regs *m6509 = token;
m6509_Regs *m6502 = m6509;
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
@ -352,7 +352,7 @@ CPU_GET_INFO( m6509 )
{
m6509_Regs *m6502 = token;
m6509_Regs *m6509 = m6502;
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */

2
src/emu/cpu/m6502/m65ce02.c
View File

@ -55,7 +55,7 @@
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
typedef struct _m65ce02_Regs m65ce02_Regs;
typedef struct _m65ce02_Regs m65ce02_Regs;
struct _m65ce02_Regs {
void (*const *insn)(void); /* pointer to the function pointer table */
PAIR ppc; /* previous program counter */

2
src/emu/cpu/m68000/m68kcpu.c
View File

@ -873,7 +873,7 @@ unsigned int m68k_get_virq(m68ki_cpu_core *m68k, unsigned int level)
void m68k_init(m68ki_cpu_core *m68k)
{
static UINT32 emulation_initialized = 0;
/* The first call to this function initializes the opcode handler jump table */
if(!emulation_initialized)
{

18
src/emu/cpu/m68000/m68kdasm.c
View File

@ -245,10 +245,10 @@ static const char *const g_cpcc[64] =
static UINT32 dasm_read_imm_8(UINT32 advance)
{
UINT32 result;
// if (g_rawop)
// if (g_rawop)
result = g_rawop[g_cpu_pc + 1 - g_rawbasepc];
// else
// result = m68k_read_disassembler_16(g_cpu_pc & g_address_mask) & 0xff;
// else
// result = m68k_read_disassembler_16(g_cpu_pc & g_address_mask) & 0xff;
g_cpu_pc += advance;
return result;
}
@ -256,11 +256,11 @@ static UINT32 dasm_read_imm_8(UINT32 advance)
static UINT32 dasm_read_imm_16(UINT32 advance)
{
UINT32 result;
// if (g_rawop)
// if (g_rawop)
result = (g_rawop[g_cpu_pc + 0 - g_rawbasepc] << 8) |
g_rawop[g_cpu_pc + 1 - g_rawbasepc];
// else
// result = m68k_read_disassembler_16(g_cpu_pc & g_address_mask) & 0xff;
// else
// result = m68k_read_disassembler_16(g_cpu_pc & g_address_mask) & 0xff;
g_cpu_pc += advance;
return result;
}
@ -268,13 +268,13 @@ static UINT32 dasm_read_imm_16(UINT32 advance)
static UINT32 dasm_read_imm_32(UINT32 advance)
{
UINT32 result;
// if (g_rawop)
// if (g_rawop)
result = (g_rawop[g_cpu_pc + 0 - g_rawbasepc] << 24) |
(g_rawop[g_cpu_pc + 1 - g_rawbasepc] << 16) |
(g_rawop[g_cpu_pc + 2 - g_rawbasepc] << 8) |
g_rawop[g_cpu_pc + 3 - g_rawbasepc];
// else
// result = m68k_read_disassembler_32(g_cpu_pc & g_address_mask) & 0xff;
// else
// result = m68k_read_disassembler_32(g_cpu_pc & g_address_mask) & 0xff;
g_cpu_pc += advance;
return result;
}

4
src/emu/cpu/mcs48/mcs48.c
View File

@ -1009,7 +1009,7 @@ static CPU_SET_CONTEXT( mcs48 )
token = src;
mcs48 = token;
update_regptr(mcs48);
change_pc(PC);
change_pc(PC);
}
/*-------------------------------------------------
@ -1020,7 +1020,7 @@ static CPU_SET_CONTEXT( mcs48 )
static CPU_SET_INFO( mcs48 )
{
mcs48_state *mcs48 = token;
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */

28
src/emu/cpu/mcs51/mcs51.c
View File

@ -32,7 +32,7 @@
/*****************************************************************************
* DS5002FP emulator by Manuel Abadia
*
*
* October 2008, couriersud: Merged back in mcs51
*
* What has been added?
@ -74,7 +74,7 @@
/******************************************************************************
* Notes:
*
*
* The term cycles is used here to really refer to clock oscilations, because 1 machine cycle
* actually takes 12 oscilations.
*
@ -267,7 +267,7 @@ struct _mcs51_regs
int cur_irq_prio; /* Holds value of the current IRQ Priority Level; -1 if no irq */
UINT8 irq_active; /* mask which irq levels are serviced */
UINT8 irq_prio[8]; /* interrupt priority */
int icount;
mcs51_uart uart; /* internal uart */
@ -1906,7 +1906,7 @@ static void mcs51_set_irq_line(mcs51_regs *mcs51, int irqline, int state)
/* Execute cycles - returns number of cycles actually run */
static CPU_EXECUTE( mcs51 )
{
mcs51_regs *mcs51 = device->token;
mcs51_regs *mcs51 = device->token;
UINT8 op;
mcs51->icount = cycles;
@ -2058,7 +2058,7 @@ static CPU_INIT( mcs51 )
mcs51_regs *mcs51 = device->token;
token = device->token; // temporary
mcs51->irq_callback = irqcallback;
mcs51->device = device;
@ -2225,7 +2225,7 @@ static CPU_INIT( i8052 )
{
mcs51_regs *mcs51 = device->token;
CPU_INIT_CALL(mcs51);
mcs51->ram_mask = 0xFF; /* 256 bytes of ram */
mcs51->num_interrupts = 6; /* 6 interrupts */
@ -2278,7 +2278,7 @@ static CPU_INIT( i80c52 )
{
mcs51_regs *mcs51 = device->token;
CPU_INIT_CALL(i8052);
mcs51->features |= (FEATURE_I80C52 | FEATURE_CMOS);
mcs51->sfr_read = i80c52_sfr_read;
mcs51->sfr_write = i80c52_sfr_write;
@ -2358,7 +2358,7 @@ static UINT8 ds5002fp_sfr_read(mcs51_regs *mcs51, size_t offset)
case ADDR_RPS: DS5_LOGR(RPS, data); break;
case ADDR_PCON:
SET_PFW(0); /* reset PFW flag */
return mcs51_sfr_read(mcs51, offset);
return mcs51_sfr_read(mcs51, offset);
default:
return mcs51_sfr_read(mcs51, offset);
}
@ -2371,9 +2371,9 @@ static CPU_INIT( ds5002fp )
static const ds5002fp_config default_config = { 0x00, 0x00, 0x00 };
const ds5002fp_config *sconfig = config ? config : &default_config;
mcs51_regs *mcs51 = device->token;
CPU_INIT_CALL( mcs51 );
mcs51->ds5002fp.config = sconfig;
mcs51->features |= (FEATURE_DS5002FP | FEATURE_CMOS);
mcs51->sfr_read = ds5002fp_sfr_read;
@ -2420,10 +2420,10 @@ static CPU_GET_CONTEXT( mcs51 )
static CPU_SET_CONTEXT( mcs51 )
{
mcs51_regs *mcs51;
if( src )
token = src;
mcs51 = token;
change_pc(PC);
update_ptrs(mcs51);
@ -2436,7 +2436,7 @@ static CPU_SET_CONTEXT( mcs51 )
static CPU_SET_INFO( mcs51 )
{
mcs51_regs *mcs51 = token;
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
@ -2502,7 +2502,7 @@ static CPU_GET_INFO( mcs51 )
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 8; break;
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 18; /* 128k for ds5002fp */ break;
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
case CPUINFO_INT_PREVIOUSPC: info->i = PPC; break;
case CPUINFO_INT_PC: info->i = PC; break;
case CPUINFO_INT_SP: info->i = SP; break;

4
src/emu/cpu/mcs51/mcs51.h
View File

@ -122,7 +122,7 @@ CPU_GET_INFO( at89c4051 );
/*
* The DS5002FP has 2 16 bits data address buses (the byte-wide bus and the expanded bus). The exact memory position accessed depends on the
* partition mode, the memory range and the expanded bus select. The partition mode and the expanded bus select can be changed at any time.
*
*
* In order to simplify memory mapping to the data address bus, the following address map is assumed for partitioned mode:
* 0x00000-0x0ffff -> data memory on the expanded bus
@ -131,7 +131,7 @@ CPU_GET_INFO( at89c4051 );
* For non-partitioned mode the following memory map is assumed:
* 0x0000-0xffff -> data memory (the bus used to access it does not matter)
*
*
* Internal ram 128k and security features
*/

74
src/emu/cpu/mcs51/mcs51dasm.c
View File

@ -59,7 +59,7 @@ static struct {
int feature;
int addr;
const char *name;
} mem_name_feature[] =
} mem_name_feature[] =
{
{ FEATURE_NONE, 0x00, "rb0r0" },
{ FEATURE_NONE, 0x01, "rb0r1" },
@ -93,7 +93,7 @@ static struct {
{ FEATURE_NONE, 0x1d, "rb3r5" },
{ FEATURE_NONE, 0x1e, "rb3r6" },
{ FEATURE_NONE, 0x1f, "rb3r7" },
{ FEATURE_NONE, 0x80, "p0" },
{ FEATURE_NONE, 0x81, "sp" },
{ FEATURE_NONE, 0x82, "dpl" },
@ -115,13 +115,13 @@ static struct {
{ FEATURE_NONE, 0xd0, "psw" },
{ FEATURE_NONE, 0xe0, "acc" },
{ FEATURE_NONE, 0xf0, "b" },
{ FEATURE_I8052, 0xc8, "t2con" },
{ FEATURE_I8052, 0xca, "rcap2l" },
{ FEATURE_I8052, 0xcb, "rcap2h" },
{ FEATURE_I8052, 0xcc, "tl2" },
{ FEATURE_I8052, 0xcd, "th2" },
{ FEATURE_I80C52, 0xb7, "iph" },
{ FEATURE_I80C52, 0xa9, "saddr" },
{ FEATURE_I80C52, 0xb9, "saden" },
@ -143,7 +143,7 @@ static struct {
{ FEATURE_I83C751, 0xf8, "i2sta" }, /* read only */
/* bit addresses */
{ FEATURE_NONE, 0x188, "it0" },
{ FEATURE_NONE, 0x189, "ie0" },
{ FEATURE_NONE, 0x18a, "it1" },
@ -184,7 +184,7 @@ static struct {
{ FEATURE_I8052, 0x1ad, "et2" },
/* FIXME: port 3 - depends on external circuits and not really
* implemented in the core. TBD */
* implemented in the core. TBD */
{ FEATURE_NONE, 0x1b0, "rxd" },
{ FEATURE_NONE, 0x1b1, "txd" },
{ FEATURE_NONE, 0x1b2, "int0" },
@ -224,37 +224,37 @@ static struct {
{ FEATURE_NONE, 0x1d6, "ac" },
{ FEATURE_NONE, 0x1d7, "cy" },
{ FEATURE_DS5002FP, 0x1d8, "rg0" },
{ FEATURE_DS5002FP, 0x1d9, "rpc" },
{ FEATURE_DS5002FP, 0x1da, "dma" },
{ FEATURE_DS5002FP, 0x1db, "ibi" },
{ FEATURE_DS5002FP, 0x1dc, "ae" },
{ FEATURE_DS5002FP, 0x1dd, "exbs" },
{ FEATURE_DS5002FP, 0x1de, "d8.6" },
{ FEATURE_DS5002FP, 0x1d8, "rg0" },
{ FEATURE_DS5002FP, 0x1d9, "rpc" },
{ FEATURE_DS5002FP, 0x1da, "dma" },
{ FEATURE_DS5002FP, 0x1db, "ibi" },
{ FEATURE_DS5002FP, 0x1dc, "ae" },
{ FEATURE_DS5002FP, 0x1dd, "exbs" },
{ FEATURE_DS5002FP, 0x1de, "d8.6" },
{ FEATURE_DS5002FP, 0x1df, "rnr" },
{ FEATURE_I83C751, 0x1d8, "ct0" },
{ FEATURE_I83C751, 0x1d9, "ct1" },
{ FEATURE_I83C751, 0x1da, "i2cfg.2" },
{ FEATURE_I83C751, 0x1db, "i2cfg.3" },
{ FEATURE_I83C751, 0x1dc, "tirun" },
{ FEATURE_I83C751, 0x1dd, "clrti" },
{ FEATURE_I83C751, 0x1de, "masterq" },
{ FEATURE_I83C751, 0x1d8, "ct0" },
{ FEATURE_I83C751, 0x1d9, "ct1" },
{ FEATURE_I83C751, 0x1da, "i2cfg.2" },
{ FEATURE_I83C751, 0x1db, "i2cfg.3" },
{ FEATURE_I83C751, 0x1dc, "tirun" },
{ FEATURE_I83C751, 0x1dd, "clrti" },
{ FEATURE_I83C751, 0x1de, "masterq" },
{ FEATURE_I83C751, 0x1df, "slaven" },
{ FEATURE_I83C751, 0x1f8, "xstp" },
{ FEATURE_I83C751, 0x1f9, "xstr" },
{ FEATURE_I83C751, 0x1fa, "makstp" },
{ FEATURE_I83C751, 0x1fb, "makstr" },
{ FEATURE_I83C751, 0x1fc, "xactv" },
{ FEATURE_I83C751, 0x1fd, "xdata" },
{ FEATURE_I83C751, 0x1fe, "idle" },
{ FEATURE_I83C751, 0x1f8, "xstp" },
{ FEATURE_I83C751, 0x1f9, "xstr" },
{ FEATURE_I83C751, 0x1fa, "makstp" },
{ FEATURE_I83C751, 0x1fb, "makstr" },
{ FEATURE_I83C751, 0x1fc, "xactv" },
{ FEATURE_I83C751, 0x1fd, "xdata" },
{ FEATURE_I83C751, 0x1fe, "idle" },
{ FEATURE_I83C751, 0x1ff, "i2sta.7" },
/* unkown
* "ibf", "obf", "idsm", "obfc", e8 - eb
* "ma0", "ma1", "mb0", "mb1", ec - ef
*/
/* unkown
* "ibf", "obf", "idsm", "obfc", e8 - eb
* "ma0", "ma1", "mb0", "mb1", ec - ef
*/
{ -1 }
};
@ -263,7 +263,7 @@ static void init_mem_names(int feature_set, const char **mem_names)
{
int i;
int feature;
/* Set defaults / i8051 */
for (i = 0; feature = mem_name_feature[i].feature, feature >= 0; i++)
{
@ -1158,7 +1158,7 @@ CPU_DISASSEMBLE( i8051 )
{
static const char *mem_names[0x200];
static int mem_names_initialized = 0;
if (!mem_names_initialized)
{
init_mem_names( FEATURE_NONE, mem_names);
@ -1171,7 +1171,7 @@ CPU_DISASSEMBLE( i8052 )
{
static const char *mem_names[0x200];
static int mem_names_initialized = 0;
if (!mem_names_initialized)
{
init_mem_names( FEATURE_I8052, mem_names);
@ -1184,7 +1184,7 @@ CPU_DISASSEMBLE( i80c51 )
{
static const char *mem_names[0x200];
static int mem_names_initialized = 0;
if (!mem_names_initialized)
{
init_mem_names( FEATURE_CMOS, mem_names);
@ -1197,7 +1197,7 @@ CPU_DISASSEMBLE( i80c52 )
{
static const char *mem_names[0x200];
static int mem_names_initialized = 0;
if (!mem_names_initialized)
{
init_mem_names( FEATURE_I8052 | FEATURE_CMOS | FEATURE_I80C52, mem_names);
@ -1210,7 +1210,7 @@ CPU_DISASSEMBLE( ds5002fp )
{
static const char *mem_names[0x200];
static int mem_names_initialized = 0;
if (!mem_names_initialized)
{
init_mem_names( FEATURE_DS5002FP | FEATURE_CMOS, mem_names);

6
src/emu/cpu/mips/r3000.c
View File

@ -322,7 +322,7 @@ static CPU_GET_CONTEXT( r3000 )
static CPU_SET_CONTEXT( r3000 )
{
r3000_state *r3000;
/* copy the context */
if (src)
token = src;
@ -344,7 +344,7 @@ static CPU_INIT( r3000 )
{
const r3000_cpu_core *configdata = config;
r3000_state *r3000 = device->token;
token = device->token; // temporary
/* allocate memory */
@ -736,7 +736,7 @@ INLINE void handle_cop3(r3000_state *r3000, UINT32 op)
static CPU_EXECUTE( r3000 )
{
r3000_state *r3000 = device->token;
/* count cycles and interrupt cycles */
r3000->icount = cycles;
r3000->icount -= r3000->interrupt_cycles;

18
src/emu/cpu/z80/z80.c
View File

@ -18,7 +18,7 @@
* - This entire notice must remain in the source code.
*
* Changes in 3.8 [Miodrag Milanovic]
* - Added MEMPTR register (according to informations provided
* - Added MEMPTR register (according to informations provided
* by Vladimir Kladov
* - BIT n,(HL) now return valid values due to use of MEMPTR
* - Fixed BIT 6,(XY+o) undocumented instructions
@ -805,7 +805,7 @@ INLINE UINT32 ARG16(z80_state *z80)
} \
else \
{ \
MEMPTR = ARG16(z80); /* implicit call PC+=2; */ \
MEMPTR = ARG16(z80); /* implicit call PC+=2; */ \
}
/***************************************************************
@ -882,7 +882,7 @@ INLINE UINT32 ARG16(z80_state *z80)
PUSH( pc ); \
PCD = addr; \
MEMPTR = PC; \
change_pc(PCD);
change_pc(PCD);
/***************************************************************
* INC r8
@ -3429,9 +3429,9 @@ static CPU_INIT( z80 )
{
z80_state *z80 = device->token;
int i, p;
token = device->token; // temporary
/* setup cycle tables */
cc[Z80_TABLE_op] = cc_op;
cc[Z80_TABLE_cb] = cc_cb;
@ -3565,7 +3565,7 @@ static CPU_INIT( z80 )
static CPU_RESET( z80 )
{
z80_state *z80 = device->token;
PC = 0x0000;
I = 0;
R = 0;
@ -3598,7 +3598,7 @@ static CPU_EXIT( z80 )
static CPU_EXECUTE( z80 )
{
z80_state *z80 = device->token;
z80->icount = cycles;
/* check for NMIs on the way in; they can only be set externally */
@ -3641,7 +3641,7 @@ static CPU_EXECUTE( z80 )
static CPU_BURN( z80 )
{
z80_state *z80 = token;
if( cycles > 0 )
{
/* NOP takes 4 cycles per instruction */
@ -3667,7 +3667,7 @@ static CPU_SET_CONTEXT( z80 )
if( src )
token = src;
z80 = token;
change_pc(PCD);
change_pc(PCD);
}
/****************************************************************************

8
src/emu/cpuexec.c
View File

@ -321,7 +321,7 @@ void cpuexec_timeslice(running_machine *machine)
cpudata->localtime = attotime_add_attoseconds(cpudata->localtime, cycles_running * attoseconds_per_cycle[cpunum]);
LOG((" %d skipped, %d total, time = %s\n", cycles_running, (INT32)cpudata->totalcycles, attotime_string(cpudata->localtime, 9)));
}
/* update the suspend state (breaks steeltal if we don't) */
cpudata->suspend = cpudata->nextsuspend;
cpudata->eatcycles = cpudata->nexteatcycles;
@ -429,7 +429,7 @@ int cpunum_is_suspended(int cpunum, int reason)
static void update_clock_information(running_machine *machine, int cpunum)
{
INT64 attos;
/* recompute cps and spc */
cycles_per_second[cpunum] = (double)cpu[cpunum].clock * cpu[cpunum].clockscale;
attoseconds_per_cycle[cpunum] = ATTOSECONDS_PER_SECOND / ((double)cpu[cpunum].clock * cpu[cpunum].clockscale);
@ -443,7 +443,7 @@ static void update_clock_information(running_machine *machine, int cpunum)
attos >>= 1;
}
cpu[cpunum].divisor = attos;
/* re-compute the perfect interleave factor */
compute_perfect_interleave(machine);
}
@ -879,7 +879,7 @@ static void compute_perfect_interleave(running_machine *machine)
if (attoseconds_per_cycle[cpunum] != 0)
{
attoseconds_t curtime = attoseconds_per_cycle[cpunum] * cputype_min_cycles(machine->config->cpu[cpunum].type);
/* find the 2nd smallest cycle interval */
if (curtime < smallest)
{

4
src/emu/inptport.c
View File

@ -3137,8 +3137,8 @@ static void field_config_insert(input_field_config *field, input_port_value *dis
for (scanfieldptr = &field->port->fieldlist; *scanfieldptr != NULL; scanfieldptr = scanfieldnextptr)
{
scanfieldnextptr = &(*scanfieldptr)->next;
if (((*scanfieldptr)->mask & field->mask) != 0 && (field->condition.condition == PORTCOND_ALWAYS ||
(*scanfieldptr)->condition.condition == PORTCOND_ALWAYS ||
if (((*scanfieldptr)->mask & field->mask) != 0 && (field->condition.condition == PORTCOND_ALWAYS ||
(*scanfieldptr)->condition.condition == PORTCOND_ALWAYS ||
condition_equal(&(*scanfieldptr)->condition, &field->condition)))
{
/* reduce the mask of the field we found */

28
src/emu/timer.c
View File

@ -79,7 +79,7 @@ struct _timer_state
/*-------------------------------------------------
quantum_slot - a single minimum quantum
quantum_slot - a single minimum quantum
request
-------------------------------------------------*/
@ -313,7 +313,7 @@ void timer_init(running_machine *machine)
timers[i].next = &timers[i+1];
timers[MAX_TIMERS-1].next = NULL;
timer_free_tail = &timers[MAX_TIMERS-1];
/* reset the quanta */
memset(quantum_list, 0, sizeof(quantum_list));
quantum_list[0].requested = ATTOSECONDS_IN_MSEC(100);
@ -348,12 +348,12 @@ void timer_destructor(void *ptr, size_t size)
attotime timer_next_fire_time(void)
{
attotime quantum_time;
/* if the current quantum has expired, find a new one */
if (attotime_compare(global_basetime, quantum_current->expire) >= 0)
{
int curr;
quantum_current->requested = 0;
quantum_current = &quantum_list[0];
for (curr = 1; curr < ARRAY_LENGTH(quantum_list); curr++)
@ -428,8 +428,8 @@ void timer_set_global_time(running_machine *machine, attotime newbase)
/*-------------------------------------------------
timer_add_scheduling_quantum - add a
scheduling quantum; the smallest active one
timer_add_scheduling_quantum - add a
scheduling quantum; the smallest active one
is the one that is in use
-------------------------------------------------*/
@ -442,19 +442,19 @@ void timer_add_scheduling_quantum(running_machine *machine, attoseconds_t quantu
/* a 0 request (minimum) needs to be non-zero to occupy a slot */
if (quantum == 0)
quantum = 1;
/* find an equal-duration slot or an empty slot */
for (curr = 1; curr < ARRAY_LENGTH(quantum_list); curr++)
{
quantum_slot *slot = &quantum_list[curr];
/* look for a matching quantum and extend it */
if (slot->requested == quantum)
{
slot->expire = attotime_max(slot->expire, expire);
return;
}
/* remember any empty slots in case of no match */
if (slot->requested == 0)
{
@ -466,7 +466,7 @@ void timer_add_scheduling_quantum(running_machine *machine, attoseconds_t quantu
else if (attotime_compare(curtime, slot->expire) >= 0)
slot->requested = 0;
}
/* fatal error if no slots left */
assert_always(blank != -1, "Out of scheduling quantum slots!");
@ -474,7 +474,7 @@ void timer_add_scheduling_quantum(running_machine *machine, attoseconds_t quantu
quantum_list[blank].requested = quantum;
quantum_list[blank].actual = MAX(quantum_list[blank].requested, quantum_minimum);
quantum_list[blank].expire = expire;
/* update the minimum */
if (quantum < quantum_current->requested)
quantum_current = &quantum_list[blank];
@ -482,19 +482,19 @@ void timer_add_scheduling_quantum(running_machine *machine, attoseconds_t quantu
/*-------------------------------------------------
timer_set_minimum_quantum - control the
timer_set_minimum_quantum - control the
minimum useful quantum (used by cpuexec only)
-------------------------------------------------*/
void timer_set_minimum_quantum(running_machine *machine, attoseconds_t quantum)
{
int curr;
/* do nothing if nothing changed */
if (quantum_minimum == quantum)
return;
quantum_minimum = quantum;
/* adjust all the actuals; this doesn't affect the current */
for (curr = 0; curr < ARRAY_LENGTH(quantum_list); curr++)
if (quantum_list[curr].requested != 0)

2
src/mame/audio/cinemat.c
View File

@ -9,7 +9,7 @@
6/27/99 Jim Hernandez -- 1st Attempt at Fixing Drone Star Castle sound and
pitch adjustments.
6/30/99 MLR added Rip Off, Solar Quest, Armor Attack (no samples yet)
11/04/08 Jim Hernandez -- Fixed Drone Star Castle sound again. It was
11/04/08 Jim Hernandez -- Fixed Drone Star Castle sound again. It was
broken for a long time due to some changes.
Bugs: Sometimes the death explosion (small explosion) does not trigger.

2
src/mame/drivers/fortecar.c
View File

@ -56,7 +56,7 @@ static WRITE8_DEVICE_HANDLER( ppi0_portc_w )
static READ8_DEVICE_HANDLER( ppi0_portc_r )
{
// popmessage("%04x",activecpu_get_pc());
// popmessage("%04x",activecpu_get_pc());
return (~(eeprom_read_bit()<<1) & 2);
}

4
src/mame/drivers/halleys.c
View File

@ -1839,7 +1839,7 @@ static INPUT_PORTS_START( halleys )
PORT_DIPUNUSED_DIPLOC( 0x80, IP_ACTIVE_LOW, "SW3:8" )
/* From US manual : "DIP SW 2 is not used and all contacts should be set off."
However, they enable debug features if you press START1 during the boot sequence. */
However, they enable debug features if you press START1 during the boot sequence. */
PORT_START("DSW3") /* 0xff97 */
PORT_DIPUNUSED_DIPLOC( 0x01, IP_ACTIVE_LOW, "SW2:1" )
PORT_DIPNAME( 0x02, 0x02, "Free Play (Cheat)" ) PORT_DIPLOCATION("SW2:2")
@ -1863,7 +1863,7 @@ static INPUT_PORTS_START( halleys )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
/* From US manual : "Coin mechs system can be optioned by setting DIP SW 1.
Position 6 on for single coin selector. Position 6 off for twin coin selector." */
Position 6 on for single coin selector. Position 6 off for twin coin selector." */
PORT_START("DSW4") /* 0xff94 - read by coin_lockout_r */
PORT_DIPUNUSED_DIPLOC( 0x01, IP_ACTIVE_LOW, "SW1:1" )
PORT_DIPUNUSED_DIPLOC( 0x02, IP_ACTIVE_LOW, "SW1:2" )

2
src/mame/drivers/m10.c
View File

@ -832,7 +832,7 @@ static MACHINE_DRIVER_START( m10 )
MDRV_VIDEO_UPDATE(m10)
/* 74LS123 */
MDRV_DEVICE_ADD("ic8j1", TTL74123)
MDRV_DEVICE_CONFIG(ic8j1_intf)
MDRV_DEVICE_ADD("ic8j2", TTL74123)

86
src/mame/drivers/megadriv.c
View File

@ -2685,17 +2685,17 @@ static WRITE16_HANDLER( _32x_68k_a15106_w )
//printf("_32x_68k_a15106_w %04x\n", data);
/*
if (a15106_reg & 0x4)
printf(" --- 68k Write Mode enabled\n");
else
printf(" --- 68k Write Mode disabled\n");
if (a15106_reg & 0x4)
printf(" --- 68k Write Mode enabled\n");
else
printf(" --- 68k Write Mode disabled\n");
if (a15106_reg & 0x1)
printf(" --- DMA Start Allowed \n");
else
printf(" --- DMA Start No Operation\n");
if (a15106_reg & 0x1)
printf(" --- DMA Start Allowed \n");
else
printf(" --- DMA Start No Operation\n");
*/
*/
}
}
@ -2887,7 +2887,7 @@ static READ16_HANDLER( _32x_68k_a15180_r )
static WRITE16_HANDLER( _32x_68k_a15180_w )
{
// printf("_32x_68k_a15180_w (a15180) %04x %04x\n",data,mem_mask);
// printf("_32x_68k_a15180_w (a15180) %04x %04x\n",data,mem_mask);
if (ACCESSING_BITS_0_7)
{
_32x_videopriority = (data & 0x80) >> 7;
@ -6722,46 +6722,46 @@ ROM_START( 32x_bios )
// ROM_LOAD( "32x_3d.bin", 0x000000, 0x006568, CRC(0171743e) SHA1(bbe6fec182baae5e4d47d263fae6b419db5366ae) )
// ROM_LOAD( "32x_h15.bin", 0x000000, 0x024564, CRC(938f4e1d) SHA1(ab7270121be53c6c82c4cb45f8f41dd24eb3a2a5) ) // test demo for 15bpp mode
// ROM_LOAD( "32x_spin.bin", 0x000000, 0x012c28, CRC(3d1d1191) SHA1(221a74408653e18cef8ce2f9b4d33ed93e4218b7) )
// ROM_LOAD( "32x_ecco.bin", 0x000000, 0x300000, CRC(b06178df) SHA1(10409f2245b058e8a32cba51e1ea391ca4480108) ) // fails after sega logo
// ROM_LOAD( "32x_ecco.bin", 0x000000, 0x300000, CRC(b06178df) SHA1(10409f2245b058e8a32cba51e1ea391ca4480108) ) // fails after sega logo
// actual games, for testing
// ROM_LOAD( "32x_knux.rom", 0x000000, 0x300000, CRC(d0b0b842) SHA1(0c2fff7bc79ed26507c08ac47464c3af19f7ced7) )
// ROM_LOAD( "32x_doom.bin", 0x000000, 0x300000, CRC(208332fd) SHA1(b68e9c7af81853b8f05b8696033dfe4c80327e38) ) // works!
// ROM_LOAD( "32x_koli.bin", 0x000000, 0x300000, CRC(20ca53ef) SHA1(191ae0b525ecf32664086d8d748e0b35f776ddfe) ) // works but needs sync ONLY on command writes / reads or game stutters?!
// ROM_LOAD( "32x_doom.bin", 0x000000, 0x300000, CRC(208332fd) SHA1(b68e9c7af81853b8f05b8696033dfe4c80327e38) ) // works!
// ROM_LOAD( "32x_koli.bin", 0x000000, 0x300000, CRC(20ca53ef) SHA1(191ae0b525ecf32664086d8d748e0b35f776ddfe) ) // works but needs sync ONLY on command writes / reads or game stutters?!
// ROM_LOAD( "32x_head.bin", 0x000000, 0x300000, CRC(ef5553ff) SHA1(4e872fbb44ecb2bd730abd8cc8f32f96b10582c0) ) // doesn't boot
// ROM_LOAD( "32x_pit.bin", 0x000000, 0x300000, CRC(f9126f15) SHA1(ee864d1677c6d976d0846eb5f8d8edb839acfb76) ) // ok, needs vram fill on intro screens tho?
// ROM_LOAD( "32x_spid.bin", 0x000000, 0x300000, CRC(29dce257) SHA1(7cc2ea1e10f110338ad880bd3e7ff3bce72e7e9e) ) // needs cmdint status reads, overwrite image support wrong? priority handling wrong??
// ROM_LOAD( "32x_carn.bin", 0x000000, 0x300000, CRC(7c7be6a2) SHA1(9a563ed821b483148339561ebd2b876efa58847b) ) // ?? doesn't boot
// ROM_LOAD( "32x_raw.bin", 0x000000, 0x400000, CRC(8eb7cd2c) SHA1(94b974f2f69f0c10bc18b349fa4ff95ca56fa47b) ) // needs cmdint status reads
// ROM_LOAD( "32x_darx.bin", 0x000000, 0x200000, CRC(22d7c906) SHA1(108b4ffed8643abdefa921cfb58389b119b47f3d) ) // ?? probably abuses the hardware, euro only ;D
// ROM_LOAD( "32x_prim.bin", 0x000000, 0x400000, CRC(e78a4d28) SHA1(5084dcca51d76173c383ab7d04cbc661673545f7) ) // needs tight sync or fails after sega logo - works with tight sync, but VERY slow
// ROM_LOAD( "32x_brut.bin", 0x000000, 0x300000, CRC(7a72c939) SHA1(40aa2c787f37772cdbd7280b8be06b15421fabae) ) // needs *very* heavy sync to work..
// ROM_LOAD( "32x_temp.bin", 0x000000, 0x300000, CRC(14e5c575) SHA1(6673ba83570b4f2c1b4a22415a56594c3cc6c6a9) ) // works (heavy slowdowns) RV emulation - really should hide 68k rom when transfer is off
// ROM_LOAD( "32x_pit.bin", 0x000000, 0x300000, CRC(f9126f15) SHA1(ee864d1677c6d976d0846eb5f8d8edb839acfb76) ) // ok, needs vram fill on intro screens tho?
// ROM_LOAD( "32x_spid.bin", 0x000000, 0x300000, CRC(29dce257) SHA1(7cc2ea1e10f110338ad880bd3e7ff3bce72e7e9e) ) // needs cmdint status reads, overwrite image support wrong? priority handling wrong??
// ROM_LOAD( "32x_carn.bin", 0x000000, 0x300000, CRC(7c7be6a2) SHA1(9a563ed821b483148339561ebd2b876efa58847b) ) // ?? doesn't boot
// ROM_LOAD( "32x_raw.bin", 0x000000, 0x400000, CRC(8eb7cd2c) SHA1(94b974f2f69f0c10bc18b349fa4ff95ca56fa47b) ) // needs cmdint status reads
// ROM_LOAD( "32x_darx.bin", 0x000000, 0x200000, CRC(22d7c906) SHA1(108b4ffed8643abdefa921cfb58389b119b47f3d) ) // ?? probably abuses the hardware, euro only ;D
// ROM_LOAD( "32x_prim.bin", 0x000000, 0x400000, CRC(e78a4d28) SHA1(5084dcca51d76173c383ab7d04cbc661673545f7) ) // needs tight sync or fails after sega logo - works with tight sync, but VERY slow
// ROM_LOAD( "32x_brut.bin", 0x000000, 0x300000, CRC(7a72c939) SHA1(40aa2c787f37772cdbd7280b8be06b15421fabae) ) // needs *very* heavy sync to work..
// ROM_LOAD( "32x_temp.bin", 0x000000, 0x300000, CRC(14e5c575) SHA1(6673ba83570b4f2c1b4a22415a56594c3cc6c6a9) ) // works (heavy slowdowns) RV emulation - really should hide 68k rom when transfer is off
// ROM_LOAD( "32x_vr.bin", 0x000000, 0x300000, CRC(7896b62e) SHA1(18dfdeb50780c2623e60a6587d7ed701a1cf81f1) ) // doesn't work
// ROM_LOAD( "32x_vf.bin", 0x000000, 0x400000, CRC(b5de9626) SHA1(f35754f4bfe3a53722d7a799f88face0fd13c424) ) // locks up when starting game
// ROM_LOAD( "32x_zaxx.bin", 0x000000, 0x200000, CRC(447d44be) SHA1(60c390f76c394bdd221936c21aecbf98aec49a3d) ) // nothing
// ROM_LOAD( "32x_trek.bin", 0x000000, 0x200000, CRC(dd9708b9) SHA1(e5248328b64a1ec4f1079c88ee53ef8d48e99e58) ) // boots, seems to run.. enables hints tho
// ROM_LOAD( "32x_sw.bin", 0x000000, 0x280000, CRC(2f16b44a) SHA1(f4ffaaf1d8330ea971643021be3f3203e1ea065d) ) // gets stuck in impossible (buggy?) 68k loop
// ROM_LOAD( "32x_wwfa.bin", 0x000000, 0x400000, CRC(61833503) SHA1(551eedc963cba0e1410b3d229b332ef9ea061469) ) // 32x game gfx missing, doesn't progress properly into game
// ROM_LOAD( "32x_shar.bin", 0x000000, 0x200000, CRC(86e7f989) SHA1(f32a52a7082761982024e40291dbd962a835b231) ) // doesn't boot
// ROM_LOAD( "32x_golf.bin", 0x000000, 0x300000, CRC(d3d0a2fe) SHA1(dc77b1e5c888c2c4284766915a5020bb14ee681d) ) // works
// ROM_LOAD( "32x_moto.bin", 0x000000, 0x200000, CRC(a21c5761) SHA1(5f1a107991aaf9eff0b3ce864b2e3151f56abe7b) ) // works (with sound!)
// ROM_LOAD( "32x_tmek.bin", 0x000000, 0x300000, CRC(66d2c48f) SHA1(173c8425921d83db3e8d181158e7599364f4c0f6) ) // works?
// ROM_LOAD( "32x_bcr.bin", 0x000000, 0x300000, CRC(936c3d27) SHA1(9b5fd499eaa442d48a2c97fceb1d505dc8e8ddff) ) // overwrite image problems, locks going ingame
// ROM_LOAD( "32x_blak.bin", 0x000000, 0x300000, CRC(d1a60a47) SHA1(4bf120cf056fe1417ca5b02fa0372ef33cb8ec11) ) // works?
// ROM_LOAD( "32x_shad.bin", 0x000000, 0x200000, CRC(60c49e4d) SHA1(561c8c63dbcabc0b1b6f31673ca75a0bde7abc72) ) // works (nasty sound)
// ROM_LOAD( "32x_abur.bin", 0x000000, 0x200000, CRC(204044c4) SHA1(9cf575feb036e2f26e78350154d5eb2fd3825325) ) // doesn't boot
// ROM_LOAD( "32x_darx.bin", 0x000000, 0x200000, CRC(22d7c906) SHA1(108b4ffed8643abdefa921cfb58389b119b47f3d) ) // doesn't boot (PAL only too)
// ROM_LOAD( "32x_fifa.bin", 0x000000, 0x300000, CRC(fb14a7c8) SHA1(131ebb717dee4dd1d8f5ab2b9393c23785d3a359) ) // crash
// ROM_LOAD( "32x_tman.bin", 0x000000, 0x400000, CRC(14eac7a6) SHA1(7588b0b8f4e93d5fdc920d3ab7e464154e423da9) ) // ok, some bad gfx
// ROM_LOAD( "32x_nba.bin", 0x000000, 0x400000, CRC(6b7994aa) SHA1(c8af3e74c49514669ba6652ec0c81bccf77873b6) ) // crash
// ROM_LOAD( "32x_nfl.bin", 0x000000, 0x300000, CRC(0bc7018d) SHA1(a0dc24f2f3a7fc5bfd12791cf25af7f7888843cf) ) // doesn't boot
// ROM_LOAD( "32x_rbi.bin", 0x000000, 0x200000, CRC(ff795fdc) SHA1(4f90433a4403fd74cafeea49272689046de4ae43) ) // doesn't boot
// ROM_LOAD( "32x_vf.bin", 0x000000, 0x400000, CRC(b5de9626) SHA1(f35754f4bfe3a53722d7a799f88face0fd13c424) ) // locks up when starting game
// ROM_LOAD( "32x_zaxx.bin", 0x000000, 0x200000, CRC(447d44be) SHA1(60c390f76c394bdd221936c21aecbf98aec49a3d) ) // nothing
// ROM_LOAD( "32x_trek.bin", 0x000000, 0x200000, CRC(dd9708b9) SHA1(e5248328b64a1ec4f1079c88ee53ef8d48e99e58) ) // boots, seems to run.. enables hints tho
// ROM_LOAD( "32x_sw.bin", 0x000000, 0x280000, CRC(2f16b44a) SHA1(f4ffaaf1d8330ea971643021be3f3203e1ea065d) ) // gets stuck in impossible (buggy?) 68k loop
// ROM_LOAD( "32x_wwfa.bin", 0x000000, 0x400000, CRC(61833503) SHA1(551eedc963cba0e1410b3d229b332ef9ea061469) ) // 32x game gfx missing, doesn't progress properly into game
// ROM_LOAD( "32x_shar.bin", 0x000000, 0x200000, CRC(86e7f989) SHA1(f32a52a7082761982024e40291dbd962a835b231) ) // doesn't boot
// ROM_LOAD( "32x_golf.bin", 0x000000, 0x300000, CRC(d3d0a2fe) SHA1(dc77b1e5c888c2c4284766915a5020bb14ee681d) ) // works
// ROM_LOAD( "32x_moto.bin", 0x000000, 0x200000, CRC(a21c5761) SHA1(5f1a107991aaf9eff0b3ce864b2e3151f56abe7b) ) // works (with sound!)
// ROM_LOAD( "32x_tmek.bin", 0x000000, 0x300000, CRC(66d2c48f) SHA1(173c8425921d83db3e8d181158e7599364f4c0f6) ) // works?
// ROM_LOAD( "32x_bcr.bin", 0x000000, 0x300000, CRC(936c3d27) SHA1(9b5fd499eaa442d48a2c97fceb1d505dc8e8ddff) ) // overwrite image problems, locks going ingame
// ROM_LOAD( "32x_blak.bin", 0x000000, 0x300000, CRC(d1a60a47) SHA1(4bf120cf056fe1417ca5b02fa0372ef33cb8ec11) ) // works?
// ROM_LOAD( "32x_shad.bin", 0x000000, 0x200000, CRC(60c49e4d) SHA1(561c8c63dbcabc0b1b6f31673ca75a0bde7abc72) ) // works (nasty sound)
// ROM_LOAD( "32x_abur.bin", 0x000000, 0x200000, CRC(204044c4) SHA1(9cf575feb036e2f26e78350154d5eb2fd3825325) ) // doesn't boot
// ROM_LOAD( "32x_darx.bin", 0x000000, 0x200000, CRC(22d7c906) SHA1(108b4ffed8643abdefa921cfb58389b119b47f3d) ) // doesn't boot (PAL only too)
// ROM_LOAD( "32x_fifa.bin", 0x000000, 0x300000, CRC(fb14a7c8) SHA1(131ebb717dee4dd1d8f5ab2b9393c23785d3a359) ) // crash
// ROM_LOAD( "32x_tman.bin", 0x000000, 0x400000, CRC(14eac7a6) SHA1(7588b0b8f4e93d5fdc920d3ab7e464154e423da9) ) // ok, some bad gfx
// ROM_LOAD( "32x_nba.bin", 0x000000, 0x400000, CRC(6b7994aa) SHA1(c8af3e74c49514669ba6652ec0c81bccf77873b6) ) // crash
// ROM_LOAD( "32x_nfl.bin", 0x000000, 0x300000, CRC(0bc7018d) SHA1(a0dc24f2f3a7fc5bfd12791cf25af7f7888843cf) ) // doesn't boot
// ROM_LOAD( "32x_rbi.bin", 0x000000, 0x200000, CRC(ff795fdc) SHA1(4f90433a4403fd74cafeea49272689046de4ae43) ) // doesn't boot
ROM_LOAD( "32x_wsb.bin", 0x000000, 0x300000, CRC(6de1bc75) SHA1(ab3026eae46a775adb7eaebc13702699557ddc41) ) // working - overwrite problems
// ROM_LOAD( "32x_mk2.bin", 0x000000, 0x400000, CRC(211085ce) SHA1(f75698de887d0ef980f73e35fc4615887a9ad58f) ) // working
// ROM_LOAD( "32x_sang.bin", 0x000000, 0x400000, CRC(e4de7625) SHA1(74a3ba27c55cff12409bf6c9324ece6247abbad1) ) // hangs after sega logo
// ROM_LOAD( "32x_mk2.bin", 0x000000, 0x400000, CRC(211085ce) SHA1(f75698de887d0ef980f73e35fc4615887a9ad58f) ) // working
// ROM_LOAD( "32x_sang.bin", 0x000000, 0x400000, CRC(e4de7625) SHA1(74a3ba27c55cff12409bf6c9324ece6247abbad1) ) // hangs after sega logo
// ROM_LOAD( "32x_mars.bin", 0x000000, 0x400000, CRC(8f7260fb) SHA1(7654c6d3cf2883c30df51cf38d723ab7902280c4) ) // official hw test program? reports lots of errors seems to get stuck on test 39?
// ROM_LOAD( "32x_mars.bin", 0x000000, 0x400000, CRC(8f7260fb) SHA1(7654c6d3cf2883c30df51cf38d723ab7902280c4) ) // official hw test program? reports lots of errors seems to get stuck on test 39?
ROM_REGION32_BE( 0x400000, "gamecart_sh2", 0 ) /* Copy for the SH2 */
ROM_COPY( "gamecart", 0x0, 0x0, 0x400000)

2
src/mame/drivers/nyny.c
View File

@ -686,7 +686,7 @@ static MACHINE_DRIVER_START( nyny )
MDRV_DEVICE_CONFIG(mc6845_intf)
/* 74LS123 */
MDRV_DEVICE_ADD("ic48_1", TTL74123)
MDRV_DEVICE_CONFIG(ic48_1_config)

2
src/mame/drivers/peplus.c
View File

@ -440,7 +440,7 @@ static READ8_DEVICE_HANDLER( peplus_crtc_display_r )
static READ8_DEVICE_HANDLER( peplus_crtc_lpen1_r )
{
return mc6845_status_r(device, offset);
return mc6845_status_r(device, offset);
//return 0x40;
}

2
src/mame/drivers/r2dtank.c
View File

@ -553,7 +553,7 @@ static MACHINE_DRIVER_START( r2dtank )
MDRV_DEVICE_CONFIG(mc6845_intf)
/* 74LS123 */
MDRV_DEVICE_ADD("74123", TTL74123)
MDRV_DEVICE_CONFIG(ttl74123_intf)

2
src/mame/drivers/spiders.c
View File

@ -707,7 +707,7 @@ static MACHINE_DRIVER_START( spiders )
MDRV_DEVICE_CONFIG(mc6845_intf)
/* 74LS123 */
MDRV_DEVICE_ADD("ic60", TTL74123)
MDRV_DEVICE_CONFIG(ic60_intf)

6
src/mame/drivers/stv.c
View File

@ -871,8 +871,8 @@ static int port_i;
static READ32_HANDLER ( stv_io_r32 )
{
// if(LOG_IOGA) logerror("(PC=%08X): I/O r %08X & %08X\n", activecpu_get_pc(), offset*4, mem_mask);
// popmessage("SEL: %02x MUX: %02x %02x %02x %02x %02x",port_sel,mux_data,ioga[1],ioga[2],ioga[3],ioga[5]);
// if(LOG_IOGA) logerror("(PC=%08X): I/O r %08X & %08X\n", activecpu_get_pc(), offset*4, mem_mask);
// popmessage("SEL: %02x MUX: %02x %02x %02x %02x %02x",port_sel,mux_data,ioga[1],ioga[2],ioga[3],ioga[5]);
switch(offset)
{
@ -987,7 +987,7 @@ static READ32_HANDLER ( stv_io_r32 )
static WRITE32_HANDLER ( stv_io_w32 )
{
// if(LOG_IOGA) logerror("(PC=%08X): I/O w %08X = %08X & %08X\n", activecpu_get_pc(), offset*4, data, mem_mask);
// if(LOG_IOGA) logerror("(PC=%08X): I/O w %08X = %08X & %08X\n", activecpu_get_pc(), offset*4, data, mem_mask);
switch(offset)
{

2
src/mame/includes/m10.h
View File

@ -10,7 +10,7 @@
#define IREMM10_CPU_CLOCK (IREMM10_MASTER_CLOCK/16)
#define IREMM10_PIXEL_CLOCK (IREMM10_MASTER_CLOCK/2)
#define IREMM10_HTOTAL (360) /* (0x100-0xd3)*8 */
#define IREMM10_HBSTART (248)
#define IREMM10_HBSTART (248)
#define IREMM10_HBEND (8)
#define IREMM10_VTOTAL (281) /* (0x200-0xe7) */
#define IREMM10_VBSTART (240)

2
src/mame/video/stvvdp2.c
View File

@ -5146,7 +5146,7 @@ WRITE32_HANDLER ( stv_vdp2_cram_w )
int r,g,b;
COMBINE_DATA(&stv_vdp2_cram[offset]);
// popmessage("%01x\n",STV_VDP2_CRMD);
// popmessage("%01x\n",STV_VDP2_CRMD);
switch( STV_VDP2_CRMD )
{

2
src/mame/video/toobin.c
View File

@ -102,7 +102,7 @@ VIDEO_START( toobin )
/* initialize the alphanumerics */
atarigen_alpha_tilemap = tilemap_create(get_alpha_tile_info, tilemap_scan_rows, 8,8, 64,48);
tilemap_set_transparent_pen(atarigen_alpha_tilemap, 0);
/* allocate a playfield bitmap for rendering */
pfbitmap = auto_bitmap_alloc(video_screen_get_width(machine->primary_screen), video_screen_get_height(machine->primary_screen), BITMAP_FORMAT_INDEXED16);
}

2
src/version.c
View File

@ -9,4 +9,4 @@
***************************************************************************/
const char build_version[] = "0.128u2 ("__DATE__")";
const char build_version[] = "0.128u3 ("__DATE__")";