added shared chessmachine device for Mephisto risc, chessmachine EC, chessmachine DR (nw)

2025-10-04 08:28:39 +03:00 · 2019-06-01 13:16:13 +02:00 · 2019-06-01 13:16:13 +02:00 · 22b7b3f4de
commit 22b7b3f4de
parent a8bdd97c96
16 changed files with 531 additions and 160 deletions
--- a/hash/ibm5170.xml
+++ b/hash/ibm5170.xml
@ -8544,13 +8544,13 @@
 	</software>

 	<software name="chessm">
-		<!-- uses ChessMachine ISA card, not compatible with Final ChessCard -->
+		<!-- uses ChessMachine ISA card(or external module), not compatible with Final ChessCard -->
 		<!-- installer v3.3a, program v3.1, chess engine v2.20(The King) -->
 		<description>The ChessMachine (v3.1, The King v2.20)</description>
 		<year>1993</year>
 		<publisher>Tasc</publisher>
 		<info name="serial" value="WR.887.68.354" />
-		<info name="usage" value="Installer registration number is WR.887.68.354. ChessMachine ISA card required." />
+		<info name="usage" value="Installer registration number is WR.887.68.354. ChessMachine hardware required." />
 		<part name="flop1" interface="floppy_3_5">
 			<dataarea name="flop" size="737280">
 				<rom name="theking22.img" size="737280" crc="88fd76e8" sha1="518d4e662e6d1cba624fb04870eb292a8c44a1c3"/>
@ -8559,13 +8559,13 @@
 	</software>

 	<software name="chessm23">
-		<!-- uses ChessMachine or Final ChessCard(ROM v3.6) ISA card -->
+		<!-- uses ChessMachine SR or Final ChessCard(ROM v3.6) ISA card -->
 		<!-- installer v3.0, program v2.3, chess engine v2.1(Gideon) -->
 		<description>The ChessMachine (v2.3, Gideon v2.1)</description>
 		<year>1991</year>
 		<publisher>Tasc</publisher>
 		<info name="serial" value="WR.887.68.354" />
-		<info name="usage" value="Installer registration number is WR.887.68.354. ChessMachine/Final ChessCard ISA card required." />
+		<info name="usage" value="Installer registration number is WR.887.68.354. ChessMachine SR/Final ChessCard ISA card required." />
 		<part name="flop1" interface="floppy_3_5">
 			<feature name="part_id" value="Disk 1" />
 			<dataarea name="flop" size="737280">
@ -8587,14 +8587,14 @@
 	</software>

 	<software name="chessm21">
-		<!-- uses ChessMachine or Final ChessCard(ROM v3.6) ISA card -->
+		<!-- uses ChessMachine SR or Final ChessCard(ROM v3.6) ISA card -->
 		<!-- installer v2.2, program v2.1, chess engine v2.1(Gideon) -->
 		<!-- also includes optional older chess engine v0.5(The King) -->
 		<description>The ChessMachine (v2.1, Gideon v2.1)</description>
 		<year>1991</year>
 		<publisher>Tasc</publisher>
 		<info name="serial" value="50677" />
-		<info name="usage" value="ChessMachine/Final ChessCard ISA card required" />
+		<info name="usage" value="ChessMachine SR/Final ChessCard ISA card required" />
 		<part name="flop1" interface="floppy_3_5">
 			<feature name="part_id" value="Disk 1" />
 			<dataarea name="flop" size="737280">
--- a/scripts/src/bus.lua
+++ b/scripts/src/bus.lua
@ -1231,8 +1231,10 @@ if (BUSES["ISA"]~=null) then
 		MAME_DIR .. "src/devices/bus/isa/wdxt_gen.h",
 		MAME_DIR .. "src/devices/bus/isa/adlib.cpp",
 		MAME_DIR .. "src/devices/bus/isa/adlib.h",
-		MAME_DIR .. "src/devices/bus/isa/chessm.cpp",
-		MAME_DIR .. "src/devices/bus/isa/chessm.h",
+		MAME_DIR .. "src/devices/bus/isa/chessmdr.cpp",
+		MAME_DIR .. "src/devices/bus/isa/chessmdr.h",
+		MAME_DIR .. "src/devices/bus/isa/chessmsr.cpp",
+		MAME_DIR .. "src/devices/bus/isa/chessmsr.h",
 		MAME_DIR .. "src/devices/bus/isa/com.cpp",
 		MAME_DIR .. "src/devices/bus/isa/com.h",
 		MAME_DIR .. "src/devices/bus/isa/fdc.cpp",
@ -2179,6 +2181,8 @@ if (BUSES["CENTRONICS"]~=null) then
 	files {
 		MAME_DIR .. "src/devices/bus/centronics/ctronics.cpp",
 		MAME_DIR .. "src/devices/bus/centronics/ctronics.h",
+		MAME_DIR .. "src/devices/bus/centronics/chessmec.cpp",
+		MAME_DIR .. "src/devices/bus/centronics/chessmec.h",
 		MAME_DIR .. "src/devices/bus/centronics/comxpl80.cpp",
 		MAME_DIR .. "src/devices/bus/centronics/comxpl80.h",
 		MAME_DIR .. "src/devices/bus/centronics/covox.cpp",
--- a/src/devices/bus/centronics/chessmec.cpp
+++ b/src/devices/bus/centronics/chessmec.cpp
@ -0,0 +1,39 @@
+// license:BSD-3-Clause
+// copyright-holders:hap
+/*
+
+The ChessMachine EC by Tasc
+External module with ARM2 CPU, also sold under the Mephisto brand by H&G
+
+see chessmachine_device for technical notes
+
+*/
+
+#include "emu.h"
+#include "chessmec.h"
+
+
+DEFINE_DEVICE_TYPE(CENTRONICS_CHESSMEC, centronics_chessmec_device, "centronics_chessmec", "The ChessMachine EC")
+
+
+//-------------------------------------------------
+//  constructor
+//-------------------------------------------------
+
+centronics_chessmec_device::centronics_chessmec_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
+	device_t(mconfig, CENTRONICS_CHESSMEC, tag, owner, clock),
+	device_centronics_peripheral_interface(mconfig, *this),
+	m_chessm(*this, "chessm")
+{ }
+
+
+
+//-------------------------------------------------
+//  device_add_mconfig - add device configuration
+//-------------------------------------------------
+
+void centronics_chessmec_device::device_add_mconfig(machine_config &config)
+{
+	CHESSMACHINE(config, m_chessm, 15'000'000);
+	m_chessm->data_out().set(FUNC(centronics_chessmec_device::output_busy));
+}
--- a/src/devices/bus/centronics/chessmec.h
+++ b/src/devices/bus/centronics/chessmec.h
@ -0,0 +1,42 @@
+// license:BSD-3-Clause
+// copyright-holders:hap
+/*
+
+  The ChessMachine EC by Tasc
+
+*/
+
+#ifndef MAME_BUS_CENTRONICS_CHESSMEC_H
+#define MAME_BUS_CENTRONICS_CHESSMEC_H
+
+#pragma once
+
+#include "ctronics.h"
+#include "machine/chessmachine.h"
+
+
+class centronics_chessmec_device : public device_t,
+	public device_centronics_peripheral_interface
+{
+public:
+	// construction/destruction
+	centronics_chessmec_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+protected:
+	// device-level overrides
+	virtual void device_start() override { }
+	virtual void device_add_mconfig(machine_config &config) override;
+
+	virtual DECLARE_WRITE_LINE_MEMBER(input_data0) override { if (started()) m_chessm->data0_w(state); }
+	virtual DECLARE_WRITE_LINE_MEMBER(input_data1) override { if (started()) m_chessm->reset_w(state); }
+	virtual DECLARE_WRITE_LINE_MEMBER(input_data7) override { if (started()) m_chessm->data1_w(state); }
+
+private:
+	required_device<chessmachine_device> m_chessm;
+
+};
+
+
+DECLARE_DEVICE_TYPE(CENTRONICS_CHESSMEC, centronics_chessmec_device)
+
+#endif // MAME_BUS_CENTRONICS_CHESSMEC_H
--- a/src/devices/bus/centronics/ctronics.cpp
+++ b/src/devices/bus/centronics/ctronics.cpp
@ -133,6 +133,7 @@ device_centronics_peripheral_interface::~device_centronics_peripheral_interface(
 #include "nec_p72.h"
 #include "printer.h"
 #include "covox.h"
+#include "chessmec.h"

 void centronics_devices(device_slot_interface &device)
 {
@ -145,4 +146,5 @@ void centronics_devices(device_slot_interface &device)
 	device.option_add("printer", CENTRONICS_PRINTER);
 	device.option_add("covox", CENTRONICS_COVOX);
 	device.option_add("covox_stereo", CENTRONICS_COVOX_STEREO);
+	device.option_add("chessmec", CENTRONICS_CHESSMEC);
 }
--- a/src/devices/bus/isa/chessmdr.cpp
+++ b/src/devices/bus/isa/chessmdr.cpp
@ -0,0 +1,124 @@
+// license:BSD-3-Clause
+// copyright-holders:hap
+/*
+
+The ChessMachine DR by Tasc
+
+8-bit ISA card, 2nd version of The ChessMachine.
+see chessmachine_device for technical notes
+
+*/
+
+#include "emu.h"
+#include "chessmdr.h"
+
+
+DEFINE_DEVICE_TYPE(ISA8_CHESSMDR, isa8_chessmdr_device, "isa_chessmdr", "The ChessMachine DR")
+
+//-------------------------------------------------
+//  constructor
+//-------------------------------------------------
+
+isa8_chessmdr_device::isa8_chessmdr_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
+	device_t(mconfig, ISA8_CHESSMDR, tag, owner, clock),
+	device_isa8_card_interface(mconfig, *this),
+	m_chessm(*this, "chessm")
+{ }
+
+
+
+//-------------------------------------------------
+//  device_start - device-specific startup
+//-------------------------------------------------
+
+void isa8_chessmdr_device::device_start()
+{
+	set_isa_device();
+	m_installed = false;
+}
+
+
+
+//-------------------------------------------------
+//  device_reset - device-specific reset
+//-------------------------------------------------
+
+void isa8_chessmdr_device::device_reset()
+{
+	if (!m_installed)
+	{
+		// MAME doesn't allow reading ioport at device_start
+		u16 port = ioport("DSW")->read() * 0x40 + 0x10;
+		m_isa->install_device(port, port+1, read8_delegate(FUNC(isa8_chessmdr_device::chessmdr_r), this), write8_delegate(FUNC(isa8_chessmdr_device::chessmdr_w), this));
+
+		m_installed = true;
+	}
+}
+
+
+
+//-------------------------------------------------
+//  input_ports - device-specific input ports
+//-------------------------------------------------
+
+static INPUT_PORTS_START( chessmdr )
+	PORT_START("DSW") // DIP switch on the ISA card PCB, installer shows range 0x110-0x3D0
+	PORT_DIPNAME( 0x0f, 0x08, "I/O Port Address" ) PORT_DIPLOCATION("CM_SW1:1,2,3,4")
+	PORT_DIPSETTING(    0x00, "0x010 (Invalid)" )
+	PORT_DIPSETTING(    0x01, "0x050 (Invalid)" )
+	PORT_DIPSETTING(    0x02, "0x090 (Invalid)" )
+	PORT_DIPSETTING(    0x03, "0x0D0 (Invalid)" )
+	PORT_DIPSETTING(    0x04, "0x110" )
+	PORT_DIPSETTING(    0x05, "0x150" )
+	PORT_DIPSETTING(    0x06, "0x190" )
+	PORT_DIPSETTING(    0x07, "0x1D0" )
+	PORT_DIPSETTING(    0x08, "0x210" )
+	PORT_DIPSETTING(    0x09, "0x250" )
+	PORT_DIPSETTING(    0x0a, "0x290" )
+	PORT_DIPSETTING(    0x0b, "0x2D0" )
+	PORT_DIPSETTING(    0x0c, "0x310" )
+	PORT_DIPSETTING(    0x0d, "0x350" )
+	PORT_DIPSETTING(    0x0e, "0x390" )
+	PORT_DIPSETTING(    0x0f, "0x3D0" )
+INPUT_PORTS_END
+
+ioport_constructor isa8_chessmdr_device::device_input_ports() const
+{
+	return INPUT_PORTS_NAME(chessmdr);
+}
+
+
+
+//-------------------------------------------------
+//  device_add_mconfig - add device configuration
+//-------------------------------------------------
+
+void isa8_chessmdr_device::device_add_mconfig(machine_config &config)
+{
+	CHESSMACHINE(config, m_chessm, 15'000'000);
+}
+
+
+
+/******************************************************************************
+    I/O
+******************************************************************************/
+
+READ8_MEMBER(isa8_chessmdr_device::chessmdr_r)
+{
+	if (offset == 1)
+		return m_chessm->data_r() ? 0 : 0x80;
+	else
+		return 0xff;
+}
+
+WRITE8_MEMBER(isa8_chessmdr_device::chessmdr_w)
+{
+	if (offset == 0)
+	{
+		m_chessm->data0_w(data & 1);
+		m_chessm->data1_w(data & 0x80);
+		m_chessm->reset_w(data & 2);
+	}
+}
+
--- a/src/devices/bus/isa/chessmdr.h
+++ b/src/devices/bus/isa/chessmdr.h
@ -0,0 +1,46 @@
+// license:BSD-3-Clause
+// copyright-holders:hap
+/*
+
+  The ChessMachine DR by Tasc
+
+*/
+
+#ifndef MAME_BUS_ISA_CHESSMDR_H
+#define MAME_BUS_ISA_CHESSMDR_H
+
+#pragma once
+
+#include "isa.h"
+#include "machine/chessmachine.h"
+
+
+class isa8_chessmdr_device :
+		public device_t,
+		public device_isa8_card_interface
+{
+public:
+	// construction/destruction
+	isa8_chessmdr_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+protected:
+	// device-level overrides
+	virtual void device_start() override;
+	virtual void device_reset() override;
+	virtual void device_add_mconfig(machine_config &config) override;
+
+	virtual ioport_constructor device_input_ports() const override;
+
+private:
+	required_device<chessmachine_device> m_chessm;
+
+	bool m_installed;
+
+	DECLARE_READ8_MEMBER(chessmdr_r);
+	DECLARE_WRITE8_MEMBER(chessmdr_w);
+};
+
+
+DECLARE_DEVICE_TYPE(ISA8_CHESSMDR, isa8_chessmdr_device)
+
+#endif // MAME_BUS_ISA_CHESSMDR_H
--- a/src/devices/bus/isa/chessmsr.cpp
+++ b/src/devices/bus/isa/chessmsr.cpp
@ -2,36 +2,33 @@
 // copyright-holders:hap
 /*

-The ChessMachine by Tasc
+The ChessMachine SR by Tasc

 8-bit ISA card, successor of The Final ChessCard.
-No ROM on the card this time, the chess program is sent to RAM instead.
+
+I/O is similar to The Final ChessCard, with two 74374 latches, but no ROM.
+There's a 74590 counter chip for writing the initial bootstrap. The rest
+of the program is sent to RAM via the latches.

 VLSI VY86C010-12QC (ARM2), seen with 30MHz XTAL, but XTAL label usually scratched off.
 128KB, 512KB, or 1MB RAM. 512KB version probably the most common.
 It looks like Gideon 2.1 only sees up to 512KB RAM, The King up to 2MB RAM.
-Also seen with VY86C061PSTC (ARM6) @ 32MHz, very rare or prototype.
-
-3 models exist: SR, DR, EC. SR and DR are ISA cards, EC is an external module (serial port).
-It was also released for the Amiga.
-
-TODO:
- add model DR (missing bootstrap ROM dump?)
+Also seen with VY86C061PSTC (ARM6) @ 32MHz, very rare, aka "Madrid" version.

 */

 #include "emu.h"
-#include "chessm.h"
+#include "chessmsr.h"


-DEFINE_DEVICE_TYPE(ISA8_CHESSM, isa8_chessm_device, "isa_chessm", "ChessMachine")
+DEFINE_DEVICE_TYPE(ISA8_CHESSMSR, isa8_chessmsr_device, "isa_chessmsr", "The ChessMachine SR")

 //-------------------------------------------------
 //  constructor
 //-------------------------------------------------

-isa8_chessm_device::isa8_chessm_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
-	device_t(mconfig, ISA8_CHESSM, tag, owner, clock),
+isa8_chessmsr_device::isa8_chessmsr_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
+	device_t(mconfig, ISA8_CHESSMSR, tag, owner, clock),
 	device_isa8_card_interface(mconfig, *this),
 	m_maincpu(*this, "maincpu"),
 	m_mainlatch(*this, "mainlatch"),
@ -45,7 +42,7 @@ isa8_chessm_device::isa8_chessm_device(const machine_config &mconfig, const char
 //  device_start - device-specific startup
 //-------------------------------------------------

-void isa8_chessm_device::device_start()
+void isa8_chessmsr_device::device_start()
 {
 	set_isa_device();
 	m_installed = false;
@ -57,13 +54,13 @@ void isa8_chessm_device::device_start()
 //  device_reset - device-specific reset
 //-------------------------------------------------

-void isa8_chessm_device::device_reset()
+void isa8_chessmsr_device::device_reset()
 {
 	if (!m_installed)
 	{
 		// MAME doesn't allow reading ioport at device_start
 		u16 port = ioport("DSW")->read() * 0x40 + 0x10;
-		m_isa->install_device(port, port+1, read8_delegate(FUNC(isa8_chessm_device::chessm_r), this), write8_delegate(FUNC(isa8_chessm_device::chessm_w), this));
+		m_isa->install_device(port, port+1, read8_delegate(FUNC(isa8_chessmsr_device::chessmsr_r), this), write8_delegate(FUNC(isa8_chessmsr_device::chessmsr_w), this));

 		m_maincpu->set_unscaled_clock(ioport("CPU")->read() ? (32_MHz_XTAL) : (30_MHz_XTAL/2));

@ -76,10 +73,10 @@ void isa8_chessm_device::device_reset()
 	}
 }

-void isa8_chessm_device::device_reset_after_children()
+void isa8_chessmsr_device::device_reset_after_children()
 {
 	// hold ARM CPU in reset state
-	chessm_w(machine().dummy_space(), 1, 0);
+	chessmsr_w(machine().dummy_space(), 1, 0);
 }


@ -88,8 +85,8 @@ void isa8_chessm_device::device_reset_after_children()
 //  input_ports - device-specific input ports
 //-------------------------------------------------

-static INPUT_PORTS_START( chessm )
-	PORT_START("DSW") // DIP switch on the ISA card PCB, installer shows range 0x110-0x390
+static INPUT_PORTS_START( chessmsr )
+	PORT_START("DSW") // DIP switch on the ISA card PCB, installer shows range 0x110-0x3D0
 	PORT_DIPNAME( 0x0f, 0x08, "I/O Port Address" ) PORT_DIPLOCATION("CM_SW1:1,2,3,4")
 	PORT_DIPSETTING(    0x00, "0x010 (Invalid)" )
 	PORT_DIPSETTING(    0x01, "0x050 (Invalid)" )
@ -106,7 +103,7 @@ static INPUT_PORTS_START( chessm )
 	PORT_DIPSETTING(    0x0c, "0x310" )
 	PORT_DIPSETTING(    0x0d, "0x350" )
 	PORT_DIPSETTING(    0x0e, "0x390" )
-	PORT_DIPSETTING(    0x0f, "0x3D0 (Invalid)" )
+	PORT_DIPSETTING(    0x0f, "0x3D0" )

 	PORT_START("CPU")
 	PORT_CONFNAME( 0x01, 0x00, "CPU Type" )
@ -121,9 +118,9 @@ static INPUT_PORTS_START( chessm )
 	PORT_CONFSETTING(    21, "2MB" ) // unofficial
 INPUT_PORTS_END

-ioport_constructor isa8_chessm_device::device_input_ports() const
+ioport_constructor isa8_chessmsr_device::device_input_ports() const
 {
-	return INPUT_PORTS_NAME(chessm);
+	return INPUT_PORTS_NAME(chessmsr);
 }


@ -132,10 +129,10 @@ ioport_constructor isa8_chessm_device::device_input_ports() const
 //  device_add_mconfig - add device configuration
 //-------------------------------------------------

-void isa8_chessm_device::device_add_mconfig(machine_config &config)
+void isa8_chessmsr_device::device_add_mconfig(machine_config &config)
 {
 	ARM(config, m_maincpu, 30_MHz_XTAL/2);
-	m_maincpu->set_addrmap(AS_PROGRAM, &isa8_chessm_device::chessm_mem);
+	m_maincpu->set_addrmap(AS_PROGRAM, &isa8_chessmsr_device::chessmsr_mem);
 	m_maincpu->set_copro_type(arm_cpu_device::copro_type::VL86C020);

 	GENERIC_LATCH_8(config, m_mainlatch);
@ -151,7 +148,7 @@ void isa8_chessm_device::device_add_mconfig(machine_config &config)

 // External handlers

-READ8_MEMBER(isa8_chessm_device::chessm_r)
+READ8_MEMBER(isa8_chessmsr_device::chessmsr_r)
 {
 	if (offset == 0)
 		return m_mainlatch->read();
@ -159,7 +156,7 @@ READ8_MEMBER(isa8_chessm_device::chessm_r)
 		return m_mainlatch->pending_r() ? 0 : 2;
 }

-WRITE8_MEMBER(isa8_chessm_device::chessm_w)
+WRITE8_MEMBER(isa8_chessmsr_device::chessmsr_w)
 {
 	if (offset == 0)
 	{
@ -181,7 +178,7 @@ WRITE8_MEMBER(isa8_chessm_device::chessm_w)

 // Internal (on-card CPU)

-void isa8_chessm_device::chessm_mem(address_map &map)
+void isa8_chessmsr_device::chessmsr_mem(address_map &map)
 {
 	map(0x00380000, 0x00380000).mirror(0x00000008).r(m_sublatch, FUNC(generic_latch_8_device::read)).w(m_mainlatch, FUNC(generic_latch_8_device::write));
 }
--- a/src/devices/bus/isa/chessmsr.h
+++ b/src/devices/bus/isa/chessmsr.h
@ -2,12 +2,12 @@
 // copyright-holders:hap
 /*

-  The ChessMachine by Tasc
+  The ChessMachine SR by Tasc

 */

-#ifndef MAME_BUS_ISA_CHESSM_H
-#define MAME_BUS_ISA_CHESSM_H
+#ifndef MAME_BUS_ISA_CHESSMSR_H
+#define MAME_BUS_ISA_CHESSMSR_H

 #pragma once

@ -16,22 +16,21 @@
 #include "machine/gen_latch.h"


-class isa8_chessm_device :
+class isa8_chessmsr_device :
 		public device_t,
 		public device_isa8_card_interface
 {
 public:
 	// construction/destruction
-	isa8_chessm_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+	isa8_chessmsr_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);

 protected:
 	// device-level overrides
 	virtual void device_start() override;
 	virtual void device_reset() override;
 	virtual void device_reset_after_children() override;
-
-	// optional information overrides
 	virtual void device_add_mconfig(machine_config &config) override;
+
 	virtual ioport_constructor device_input_ports() const override;

 private:
@ -44,14 +43,13 @@ private:
 	bool m_suspended;
 	bool m_installed;

-	DECLARE_READ8_MEMBER(chessm_r);
-	DECLARE_WRITE8_MEMBER(chessm_w);
+	DECLARE_READ8_MEMBER(chessmsr_r);
+	DECLARE_WRITE8_MEMBER(chessmsr_w);

-	void chessm_mem(address_map &map);
+	void chessmsr_mem(address_map &map);
 };


-DECLARE_DEVICE_TYPE(ISA8_CHESSM, isa8_chessm_device)
+DECLARE_DEVICE_TYPE(ISA8_CHESSMSR, isa8_chessmsr_device)

-
-#endif // MAME_BUS_ISA_CHESSM_H
+#endif // MAME_BUS_ISA_CHESSMSR_H
--- a/src/devices/bus/isa/finalchs.cpp
+++ b/src/devices/bus/isa/finalchs.cpp
@ -8,7 +8,7 @@ The Final ChessCard by Tasc
 It is similar to the C64 version, actually not as impressive since a PC from around 1989
 should be able to run a good chess game by itself.

-Tasc later released The ChessMachine ISA card, see chessm.cpp.
+Tasc later released The ChessMachine ISA card, see chessm*.cpp.

 Multiple ROM revisions were made. Version 2.0 is compatible with the initial 1989
 software version. Version 3.6 works with the newer software package, including the
@ -20,7 +20,7 @@ one that came with The ChessMachine.
 #include "finalchs.h"


-DEFINE_DEVICE_TYPE(ISA8_FINALCHS, isa8_finalchs_device, "isa_finalchs", "Final ChessCard")
+DEFINE_DEVICE_TYPE(ISA8_FINALCHS, isa8_finalchs_device, "isa_finalchs", "The Final ChessCard")

 //-------------------------------------------------
 //  constructor
--- a/src/devices/bus/isa/finalchs.h
+++ b/src/devices/bus/isa/finalchs.h
@ -28,9 +28,9 @@ protected:
 	// device-level overrides
 	virtual void device_start() override;
 	virtual void device_reset() override;
+	virtual void device_add_mconfig(machine_config &config) override;

 	// optional information overrides
-	virtual void device_add_mconfig(machine_config &config) override;
 	virtual const tiny_rom_entry *device_rom_region() const override;
 	virtual ioport_constructor device_input_ports() const override;

@ -50,5 +50,4 @@ private:

 DECLARE_DEVICE_TYPE(ISA8_FINALCHS, isa8_finalchs_device)

-
 #endif // MAME_BUS_ISA_FINALCHS_H
--- a/src/devices/bus/isa/isa_cards.cpp
+++ b/src/devices/bus/isa/isa_cards.cpp
@ -73,7 +73,8 @@
 #include "pds.h"

 // other
-#include "chessm.h"
+#include "chessmdr.h"
+#include "chessmsr.h"
 #include "finalchs.h"


@ -122,7 +123,8 @@ void pc_isa8_cards(device_slot_interface &device)
 	device.option_add("pds", ISA8_PDS);
 	device.option_add("lba_enhancer", ISA8_LBA_ENHANCER);
 	device.option_add("asc88", ASC88);
-	device.option_add("chessm", ISA8_CHESSM);
+	device.option_add("chessmdr", ISA8_CHESSMDR);
+	device.option_add("chessmsr", ISA8_CHESSMSR);
 	device.option_add("finalchs", ISA8_FINALCHS);
 }

@ -161,7 +163,8 @@ void pc_isa16_cards(device_slot_interface &device)
 	device.option_add("dectalk", ISA8_DECTALK);
 	device.option_add("pds", ISA8_PDS);
 	device.option_add("lba_enhancer", ISA8_LBA_ENHANCER);
-	device.option_add("chessm", ISA8_CHESSM);
+	device.option_add("chessmdr", ISA8_CHESSMDR);
+	device.option_add("chessmsr", ISA8_CHESSMSR);
 	device.option_add("finalchs", ISA8_FINALCHS);
 	// 16-bit
 	device.option_add("ide", ISA16_IDE);
--- a/src/devices/machine/gen_latch.cpp
+++ b/src/devices/machine/gen_latch.cpp
@ -9,6 +9,11 @@
 #include "emu.h"
 #include "gen_latch.h"

+#define LOG_WARN (1U << 0)
+#define VERBOSE (LOG_WARN)
+
+#include "logmacro.h"
+

 //**************************************************************************
 //  DEVICE TYPE DEFINITIONS
@ -154,7 +159,7 @@ void generic_latch_8_device::sync_callback(void *ptr, s32 param)

 	// if the latch has been written and the value is changed, log a warning
 	if (is_latch_written() && m_latched_value != value)
-		logerror("Warning: latch written before being read. Previous: %02x, new: %02x\n", m_latched_value, value);
+		LOGMASKED(LOG_WARN, "Warning: latch written before being read. Previous: %02x, new: %02x\n", m_latched_value, value);

 	// store the new value and mark it not read
 	m_latched_value = value;
@ -225,7 +230,7 @@ void generic_latch_16_device::sync_callback(void *ptr, s32 param)

 	// if the latch has been written and the value is changed, log a warning
 	if (is_latch_written() && m_latched_value != value)
-		logerror("Warning: latch written before being read. Previous: %02x, new: %02x\n", m_latched_value, value);
+		LOGMASKED(LOG_WARN, "Warning: latch written before being read. Previous: %02x, new: %02x\n", m_latched_value, value);

 	// store the new value and mark it not read
 	m_latched_value = value;
--- a/src/mame/drivers/polgar.cpp
+++ b/src/mame/drivers/polgar.cpp
@ -2,18 +2,21 @@
 // copyright-holders:Sandro Ronco
 /**************************************************************************************************

-    Mephisto Polgar and RISC
+Mephisto Polgar and RISC
+
+TODO:
+- Mephisto Risc maincpu is more likely 5MHz, but LCD doesn't like it

 **************************************************************************************************/


 #include "emu.h"
 #include "cpu/m6502/m65c02.h"
-#include "cpu/arm/arm.h"
+#include "cpu/m6502/m65sc02.h"
 #include "machine/74259.h"
 #include "machine/nvram.h"
 #include "machine/mmboard.h"
-#include "machine/ram.h"
+#include "machine/chessmachine.h"
 #include "video/hd44780.h"
 #include "speaker.h"

@ -44,34 +47,22 @@ class mephisto_risc_state : public mephisto_polgar_state
 public:
 	mephisto_risc_state(const machine_config &mconfig, device_type type, const char *tag)
 		: mephisto_polgar_state(mconfig, type, tag)
-		, m_subcpu(*this, "subcpu")
+		, m_chessm(*this, "chessm")
 		, m_rombank(*this, "rombank")
-		, m_ram(*this, "ram")
 	{ }

-	DECLARE_READ8_MEMBER(latch0_r);
-	DECLARE_WRITE8_MEMBER(latch0_w);
-	DECLARE_WRITE8_MEMBER(latch1_w);
-	DECLARE_READ8_MEMBER(latch1_r);
-	DECLARE_READ32_MEMBER(disable_boot_rom_r);
+	DECLARE_READ8_MEMBER(chessm_r);
+	DECLARE_WRITE8_MEMBER(chessm_w);

 	void mrisc(machine_config &config);
-	void mrisc_arm_mem(address_map &map);
 	void mrisc_mem(address_map &map);
 protected:
 	virtual void machine_start() override;
-	virtual void machine_reset() override;
-	void remove_boot_rom();
-	TIMER_CALLBACK_MEMBER(disable_boot_rom);

 private:
-	required_device<arm_cpu_device> m_subcpu;
+	required_device<chessmachine_device> m_chessm;
 	required_memory_bank m_rombank;
-	required_device<ram_device> m_ram;
 	uint8_t m_bank;
-	uint8_t m_com_latch0;
-	uint8_t m_com_latch1;
-	emu_timer* m_disable_boot_rom_timer;
 };

 class mephisto_milano_state : public mephisto_polgar_state
@ -146,47 +137,16 @@ void mephisto_polgar_state::polgar_mem(address_map &map)
 }


-WRITE8_MEMBER(mephisto_risc_state::latch1_w)
+READ8_MEMBER(mephisto_risc_state::chessm_r)
 {
-	m_com_latch1 = data;
-	m_subcpu->set_input_line(ARM_FIRQ_LINE, ASSERT_LINE);
-	m_subcpu->set_input_line(INPUT_LINE_RESET, (data & 0x02) ? ASSERT_LINE : CLEAR_LINE);
-	if (data & 0x02)
-		m_subcpu->space(AS_PROGRAM).install_rom(0x00000000, 0x0000007f, memregion("arm_bootstrap")->base());
+	return m_chessm->data_r();
 }

-
-READ8_MEMBER(mephisto_risc_state::latch1_r)
+WRITE8_MEMBER(mephisto_risc_state::chessm_w)
 {
-	return m_com_latch1;
-}
-
-WRITE8_MEMBER(mephisto_risc_state::latch0_w)
-{
-	m_subcpu->set_input_line(ARM_FIRQ_LINE, CLEAR_LINE);
-	m_com_latch0 = data;
-}
-
-READ8_MEMBER(mephisto_risc_state::latch0_r)
-{
-	return m_com_latch0;
-}
-
-READ32_MEMBER(mephisto_risc_state::disable_boot_rom_r)
-{
-	m_disable_boot_rom_timer->adjust(m_subcpu->cycles_to_attotime(10));
-	return space.unmap();
-}
-
-void mephisto_risc_state::remove_boot_rom()
-{
-	m_subcpu->space(AS_PROGRAM).install_ram(0x00000000, m_ram->size() - 1, m_ram->pointer());
-}
-
-
-TIMER_CALLBACK_MEMBER(mephisto_risc_state::disable_boot_rom)
-{
-	remove_boot_rom();
+	m_chessm->data0_w(data & 1);
+	m_chessm->data1_w(data & 0x80);
+	m_chessm->reset_w(data & 2);
 }

 void mephisto_risc_state::mrisc_mem(address_map &map)
@ -199,22 +159,14 @@ void mephisto_risc_state::mrisc_mem(address_map &map)
 	map(0x2400, 0x2400).w("board", FUNC(mephisto_board_device::led_w));
 	map(0x2800, 0x2800).w("board", FUNC(mephisto_board_device::mux_w));
 	map(0x3000, 0x3000).r("board", FUNC(mephisto_board_device::input_r));
-	map(0x3400, 0x3407).w("outlatch", FUNC(hc259_device::write_d7));
-	map(0x3800, 0x3800).w(FUNC(mephisto_risc_state::latch1_w));
-	map(0x3c00, 0x3c00).r(FUNC(mephisto_risc_state::latch0_r));
+	map(0x3400, 0x3407).w("outlatch", FUNC(hc259_device::write_d7)).nopr();
+	map(0x3800, 0x3800).w(FUNC(mephisto_risc_state::chessm_w));
+	map(0x3c00, 0x3c00).r(FUNC(mephisto_risc_state::chessm_r));
 	map(0x4000, 0x7fff).rom();
 	map(0x8000, 0xffff).bankr("rombank");
 }


-void mephisto_risc_state::mrisc_arm_mem(address_map &map)
-{
-	map(0x00000000, 0x000fffff).ram();
-	map(0x00400000, 0x007fffff).rw(FUNC(mephisto_risc_state::latch1_r), FUNC(mephisto_risc_state::latch0_w)).umask32(0x000000ff);
-	map(0x01800000, 0x01800003).r(FUNC(mephisto_risc_state::disable_boot_rom_r));
-}
-
-
 READ8_MEMBER(mephisto_milano_state::milano_input_r)
 {
 	return m_board->input_r(space, offset) ^ 0xff;
@ -316,24 +268,8 @@ INPUT_PORTS_END

 void mephisto_risc_state::machine_start()
 {
-	m_disable_boot_rom_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mephisto_risc_state::disable_boot_rom), this));
 	m_rombank->configure_entries(0, 4, memregion("maincpu")->base(), 0x8000);
-
 	save_item(NAME(m_bank));
-	save_item(NAME(m_com_latch0));
-	save_item(NAME(m_com_latch1));
-
-	machine().save().register_postload(save_prepost_delegate(FUNC(mephisto_risc_state::remove_boot_rom), this));
-}
-
-void mephisto_risc_state::machine_reset()
-{
-	m_com_latch0 = 0;
-	m_com_latch1 = 0;
-	m_subcpu->space(AS_PROGRAM).install_ram(0x00, m_ram->size() - 1, m_ram->pointer());
-
-	// ARM bootstrap code
-	m_subcpu->space(AS_PROGRAM).install_rom(0x00000000, 0x0000007f, memregion("arm_bootstrap")->base());
 }

 void mephisto_milano_state::machine_start()
@ -386,14 +322,11 @@ void mephisto_polgar_state::polgar10(machine_config &config)

 void mephisto_risc_state::mrisc(machine_config &config)
 {
-	m65c02_device &maincpu(M65C02(config, "maincpu", XTAL(10'000'000) / 4)); // G65SC02
+	m65sc02_device &maincpu(M65SC02(config, "maincpu", XTAL(10'000'000) / 4)); // G65SC02P-4
 	maincpu.set_addrmap(AS_PROGRAM, &mephisto_risc_state::mrisc_mem);
 	maincpu.set_periodic_int(FUNC(mephisto_risc_state::irq0_line_hold), attotime::from_hz(XTAL(10'000'000) / (1 << 14)));

-	ARM(config, m_subcpu, XTAL(14'000'000)); // VY86C010
-	m_subcpu->set_addrmap(AS_PROGRAM, &mephisto_risc_state::mrisc_arm_mem);
-	m_subcpu->set_copro_type(arm_cpu_device::copro_type::VL86C020);
-
+	CHESSMACHINE(config, m_chessm, 14'000'000); // Tasc ChessMachine EC PCB, Mephisto manual says 14MHz (no XTAL)
 	config.m_perfect_cpu_quantum = subtag("maincpu");

 	NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
@ -407,8 +340,6 @@ void mephisto_risc_state::mrisc(machine_config &config)
 	outlatch.q_out_cb<5>().set_output("led105");
 	outlatch.parallel_out_cb().set_membank("rombank").rshift(6).mask(0x03).exor(0x01);

-	RAM(config, "ram").set_default_size("1M");
-
 	MEPHISTO_SENSORS_BOARD(config, "board", 0);
 	MEPHISTO_DISPLAY_MODUL(config, "display", 0);
 	config.set_default_layout(layout_mephisto_lcd);
@ -453,23 +384,11 @@ ROM_END
 ROM_START(mrisc)
 	ROM_REGION(0x20000, "maincpu", 0)
 	ROM_LOAD("meph-risci-v1-2.bin", 0x00000, 0x20000, CRC(19c6ab83) SHA1(0baab84e5aa6999c24250938d207145144945fd5))
-
-	ROM_REGION32_LE(0x80, "arm_bootstrap", 0)
-	ROM_LOAD32_BYTE( "74s288.1", 0x00, 0x20, CRC(284114e2) SHA1(df4037536d505d7240bb1d70dc58f59a34ab77b4) )
-	ROM_LOAD32_BYTE( "74s288.2", 0x01, 0x20, CRC(9f239c75) SHA1(aafaf30dac90f36b01f9ee89903649fc4ea0480d) )
-	ROM_LOAD32_BYTE( "74s288.3", 0x02, 0x20, CRC(0455360b) SHA1(f1486142330f2c39a4d6c479646030d31443d1c8) )
-	ROM_LOAD32_BYTE( "74s288.4", 0x03, 0x20, CRC(c7c9aba8) SHA1(cbb5b12b5917e36679d45bcbc36ea9285223a75d) )
 ROM_END

 ROM_START(mrisc2)
 	ROM_REGION(0x20000, "maincpu", 0)
 	ROM_LOAD("meph-riscii-v2.bin", 0x00000, 0x20000, CRC(9ecf9cd3) SHA1(7bfc628183037a172242c9589f15aca218d8fb12))
-
-	ROM_REGION32_LE(0x80, "arm_bootstrap", 0)
-	ROM_LOAD32_BYTE( "74s288.1", 0x00, 0x20, CRC(284114e2) SHA1(df4037536d505d7240bb1d70dc58f59a34ab77b4) )
-	ROM_LOAD32_BYTE( "74s288.2", 0x01, 0x20, CRC(9f239c75) SHA1(aafaf30dac90f36b01f9ee89903649fc4ea0480d) )
-	ROM_LOAD32_BYTE( "74s288.3", 0x02, 0x20, CRC(0455360b) SHA1(f1486142330f2c39a4d6c479646030d31443d1c8) )
-	ROM_LOAD32_BYTE( "74s288.4", 0x03, 0x20, CRC(c7c9aba8) SHA1(cbb5b12b5917e36679d45bcbc36ea9285223a75d) )
 ROM_END

 ROM_START(academy)
--- a/src/mame/machine/chessmachine.cpp
+++ b/src/mame/machine/chessmachine.cpp
@ -0,0 +1,137 @@
+// license:BSD-3-Clause
+// copyright-holders:hap, Sandro Ronco
+/*
+
+The ChessMachine by Tasc
+
+This is the 2nd (1992) version of The ChessMachine, it is used in:
+- The ChessMachine DR, PC ISA card
+- The ChessMachine EC, PC external module (printer port)
+- The ChessMachine EC2, Amiga external module
+- Mephisto Risc 1MB/II, chess computer
+
+Unlike the SR model (devices/bus/isa/chessmsr.*), RAM size and CPU type
+are the same on every known device.
+
+- VLSI-ARM VY86C010-12QC (ARM2 CPU)
+- 1MB RAM (8*Siemens HYB514256B-60)
+- 128 bytes PROM (4*DM74S288AN)
+- 2 GALs for I/O handling
+
+Only 4 lines for I/O, so that part is much slower than the SR model.
+
+There is no XTAL, it looks like there's a variable resistor for tweaking
+CPU speed. It should be around 14-16MHz. The ARM CPU is rated 12MHz, they
+probably went for this solution to get optimum possible speed for each module.
+
+TODO:
+- DR/EC sometimes gives "Risc communication error 21 (Put byte error)" at boot,
+  the game will retry and succeed. The problem goes away with perfect quantum.
+  But mrisc/mrisc2 is even worse, even with sync points(eg. using gen_latch), so
+  that one was given perfect quantum to fix it.
+- is interrupt handling correct?
+
+*/
+
+#include "emu.h"
+#include "machine/chessmachine.h"
+
+
+DEFINE_DEVICE_TYPE(CHESSMACHINE, chessmachine_device, "chessmachine", "Tasc ChessMachine")
+
+//-------------------------------------------------
+//  constructor
+//-------------------------------------------------
+
+chessmachine_device::chessmachine_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
+	device_t(mconfig, CHESSMACHINE, tag, owner, clock),
+	m_maincpu(*this, "maincpu"),
+	m_bootstrap(*this, "bootstrap"),
+	m_data_out(*this)
+{ }
+
+
+
+//-------------------------------------------------
+//  device_start - device-specific startup
+//-------------------------------------------------
+
+void chessmachine_device::device_start()
+{
+	// resolve callbacks
+	m_data_out.resolve_safe();
+
+	// zerofill, register for savestates
+	m_latch[0] = m_latch[1] = 0;
+	save_item(NAME(m_latch));
+}
+
+
+
+//-------------------------------------------------
+//  external handlers
+//-------------------------------------------------
+
+void chessmachine_device::data0_w(int state)
+{
+	m_latch[0] = (m_latch[0] & 0x80) | (state ? 1 : 0);
+}
+
+void chessmachine_device::data1_w(int state)
+{
+	m_latch[0] = (m_latch[0] & 1) | (state ? 0x80 : 0);
+
+	// cause interrupt?
+	m_maincpu->set_input_line(ARM_FIRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
+}
+
+void chessmachine_device::reset_w(int state)
+{
+	m_maincpu->set_input_line(INPUT_LINE_RESET, state ? ASSERT_LINE : CLEAR_LINE);
+
+	if (state)
+	{
+		// send bootstrap
+		for (int i = 0; i < 0x80; i++)
+			m_maincpu->space(AS_PROGRAM).write_byte(i, m_bootstrap[i]);
+	}
+}
+
+
+
+//-------------------------------------------------
+//  internal
+//-------------------------------------------------
+
+void chessmachine_device::main_map(address_map &map)
+{
+	map(0x00000000, 0x000fffff).ram();
+	map(0x00400000, 0x00400000).mirror(0x003ffffc).rw(FUNC(chessmachine_device::internal_r), FUNC(chessmachine_device::internal_w));
+	//map(0x01800000, 0x01800003).nopr(); // disconnect bootstrap?
+}
+
+void chessmachine_device::device_add_mconfig(machine_config &config)
+{
+	ARM(config, m_maincpu, DERIVED_CLOCK(1,1));
+	m_maincpu->set_addrmap(AS_PROGRAM, &chessmachine_device::main_map);
+	m_maincpu->set_copro_type(arm_cpu_device::copro_type::VL86C020);
+}
+
+
+
+//-------------------------------------------------
+//  rom_region - device-specific ROM region
+//-------------------------------------------------
+
+ROM_START( chessmachine )
+	ROM_REGION( 0x80, "bootstrap", 0 )
+	ROM_LOAD32_BYTE( "74s288.1", 0x00, 0x20, CRC(284114e2) SHA1(df4037536d505d7240bb1d70dc58f59a34ab77b4) )
+	ROM_LOAD32_BYTE( "74s288.2", 0x01, 0x20, CRC(9f239c75) SHA1(aafaf30dac90f36b01f9ee89903649fc4ea0480d) )
+	ROM_LOAD32_BYTE( "74s288.3", 0x02, 0x20, CRC(0455360b) SHA1(f1486142330f2c39a4d6c479646030d31443d1c8) )
+	ROM_LOAD32_BYTE( "74s288.4", 0x03, 0x20, CRC(c7c9aba8) SHA1(cbb5b12b5917e36679d45bcbc36ea9285223a75d) )
+ROM_END
+
+const tiny_rom_entry *chessmachine_device::device_rom_region() const
+{
+	return ROM_NAME(chessmachine);
+}
--- a/src/mame/machine/chessmachine.h
+++ b/src/mame/machine/chessmachine.h
@ -0,0 +1,56 @@
+// license:BSD-3-Clause
+// copyright-holders:hap, Sandro Ronco
+/*
+
+  The ChessMachine by Tasc
+
+*/
+
+#ifndef MAME_MACHINE_CHESSM_H
+#define MAME_MACHINE_CHESSM_H
+
+#pragma once
+
+#include "cpu/arm/arm.h"
+
+
+class chessmachine_device : public device_t
+{
+public:
+	chessmachine_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
+
+	// configuration helpers
+	auto data_out() { return m_data_out.bind(); } // data_r
+
+	// external read/write lines
+	int data_r() { return m_latch[1]; }
+	void data0_w(int state);
+	void data1_w(int state);
+	void reset_w(int state);
+
+protected:
+	// device-level overrides
+	virtual void device_start() override;
+	virtual void device_reset_after_children() override { m_maincpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE); }
+	virtual void device_add_mconfig(machine_config &config) override;
+
+	virtual const tiny_rom_entry *device_rom_region() const override;
+
+private:
+	required_device<arm_cpu_device> m_maincpu;
+	required_region_ptr<u8> m_bootstrap;
+
+	devcb_write_line m_data_out;
+
+	u8 m_latch[2];
+
+	DECLARE_READ8_MEMBER(internal_r) { return m_latch[0]; }
+	DECLARE_WRITE8_MEMBER(internal_w) { m_latch[1] = data & 1; m_data_out(m_latch[1]); }
+
+	void main_map(address_map &map);
+};
+
+
+DECLARE_DEVICE_TYPE(CHESSMACHINE, chessmachine_device)
+
+#endif // MAME_MACHINE_CHESSM_H