mirror of
https://github.com/holub/mame
synced 2025-05-19 12:18:56 +03:00
pointerified the psx cpu core & switched it to the new memory functions. Changed some MIPS_* to PSXCPU_*
This commit is contained in:
smf-
parent
2cd2454c39
commit
24022b72ca
2
.gitattributes
vendored
2
.gitattributes
vendored
@ -291,9 +291,9 @@ src/emu/cpu/mips/mips3drc.c svneol=native#text/plain
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src/emu/cpu/mips/mips3dsm.c svneol=native#text/plain
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src/emu/cpu/mips/mips3fe.c svneol=native#text/plain
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src/emu/cpu/mips/mips3fe.h svneol=native#text/plain
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src/emu/cpu/mips/mipsdasm.c svneol=native#text/plain
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src/emu/cpu/mips/psx.c svneol=native#text/plain
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src/emu/cpu/mips/psx.h svneol=native#text/plain
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src/emu/cpu/mips/psxdasm.c svneol=native#text/plain
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src/emu/cpu/mips/r3000.c svneol=native#text/plain
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src/emu/cpu/mips/r3000.h svneol=native#text/plain
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src/emu/cpu/mips/r3kdasm.c svneol=native#text/plain
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@ -1500,7 +1500,7 @@ CPUDEFS += -DHAS_CXD8661R=$(if $(filter CXD8661R,$(CPUS)),1,0)
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ifneq ($(filter PSXCPU CXD8661R,$(CPUS)),)
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OBJDIRS += $(CPUOBJ)/mips
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CPUOBJS += $(CPUOBJ)/mips/psx.o
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DBGOBJS += $(CPUOBJ)/mips/mipsdasm.o
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DBGOBJS += $(CPUOBJ)/mips/psxdasm.o
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endif
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$(CPUOBJ)/mips/psx.o: $(CPUSRC)/mips/psx.c \
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@ -290,7 +290,7 @@ int main( int argc, char *argv[] )
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switch( cpu )
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{
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case CPU_PSX:
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i = DasmMIPS( buf, pc + offset, filebuf + pc );
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i = DasmPSXCPU( NULL, buf, pc + offset, filebuf + pc );
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break;
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case CPU_R3000:
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{
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@ -1,2 +1,2 @@
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..\..\..\..\dismips.exe: dismips.c mipsdasm.c r3kdasm.c mips3dsm.c ../../../lib/util/corestr.c
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gcc -O3 -Wall -I../../../emu -I../../../osd -I../../../lib/util -DINLINE="static __inline__" -DSTANDALONE -DLSB_FIRST dismips.c mipsdasm.c r3kdasm.c mips3dsm.c ../../../lib/util/corestr.c -o../../../../dismips
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..\..\..\..\dismips.exe: dismips.c psxdasm.c r3kdasm.c mips3dsm.c ../../../lib/util/corestr.c
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gcc -O3 -Wall -I../../../emu -I../../../osd -I../../../lib/util -DINLINE="static __inline__" -DSTANDALONE -DLSB_FIRST dismips.c psxdasm.c r3kdasm.c mips3dsm.c ../../../lib/util/corestr.c -o../../../../dismips
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File diff suppressed because it is too large
Load Diff
@ -5,84 +5,82 @@
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#include "cpuintrf.h"
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#define MIPS_DELAYR_PC ( 32 )
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#define MIPS_DELAYR_NOTPC ( 33 )
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#define PSXCPU_DELAYR_PC ( 32 )
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#define PSXCPU_DELAYR_NOTPC ( 33 )
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enum
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{
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MIPS_PC = 1,
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MIPS_DELAYV, MIPS_DELAYR,
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MIPS_HI, MIPS_LO,
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MIPS_BIU,
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MIPS_R0, MIPS_R1,
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MIPS_R2, MIPS_R3,
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MIPS_R4, MIPS_R5,
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MIPS_R6, MIPS_R7,
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MIPS_R8, MIPS_R9,
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MIPS_R10, MIPS_R11,
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MIPS_R12, MIPS_R13,
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MIPS_R14, MIPS_R15,
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MIPS_R16, MIPS_R17,
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MIPS_R18, MIPS_R19,
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MIPS_R20, MIPS_R21,
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MIPS_R22, MIPS_R23,
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MIPS_R24, MIPS_R25,
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MIPS_R26, MIPS_R27,
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MIPS_R28, MIPS_R29,
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MIPS_R30, MIPS_R31,
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MIPS_CP0R0, MIPS_CP0R1,
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MIPS_CP0R2, MIPS_CP0R3,
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MIPS_CP0R4, MIPS_CP0R5,
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MIPS_CP0R6, MIPS_CP0R7,
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MIPS_CP0R8, MIPS_CP0R9,
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MIPS_CP0R10, MIPS_CP0R11,
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MIPS_CP0R12, MIPS_CP0R13,
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MIPS_CP0R14, MIPS_CP0R15,
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MIPS_CP2DR0, MIPS_CP2DR1,
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MIPS_CP2DR2, MIPS_CP2DR3,
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MIPS_CP2DR4, MIPS_CP2DR5,
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MIPS_CP2DR6, MIPS_CP2DR7,
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MIPS_CP2DR8, MIPS_CP2DR9,
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MIPS_CP2DR10, MIPS_CP2DR11,
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MIPS_CP2DR12, MIPS_CP2DR13,
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MIPS_CP2DR14, MIPS_CP2DR15,
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MIPS_CP2DR16, MIPS_CP2DR17,
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MIPS_CP2DR18, MIPS_CP2DR19,
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MIPS_CP2DR20, MIPS_CP2DR21,
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MIPS_CP2DR22, MIPS_CP2DR23,
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MIPS_CP2DR24, MIPS_CP2DR25,
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MIPS_CP2DR26, MIPS_CP2DR27,
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MIPS_CP2DR28, MIPS_CP2DR29,
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MIPS_CP2DR30, MIPS_CP2DR31,
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MIPS_CP2CR0, MIPS_CP2CR1,
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MIPS_CP2CR2, MIPS_CP2CR3,
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MIPS_CP2CR4, MIPS_CP2CR5,
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MIPS_CP2CR6, MIPS_CP2CR7,
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MIPS_CP2CR8, MIPS_CP2CR9,
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MIPS_CP2CR10, MIPS_CP2CR11,
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MIPS_CP2CR12, MIPS_CP2CR13,
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MIPS_CP2CR14, MIPS_CP2CR15,
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MIPS_CP2CR16, MIPS_CP2CR17,
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MIPS_CP2CR18, MIPS_CP2CR19,
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MIPS_CP2CR20, MIPS_CP2CR21,
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MIPS_CP2CR22, MIPS_CP2CR23,
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MIPS_CP2CR24, MIPS_CP2CR25,
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MIPS_CP2CR26, MIPS_CP2CR27,
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MIPS_CP2CR28, MIPS_CP2CR29,
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MIPS_CP2CR30, MIPS_CP2CR31
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PSXCPU_PC = 1,
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PSXCPU_DELAYV, PSXCPU_DELAYR,
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PSXCPU_HI, PSXCPU_LO,
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PSXCPU_BIU,
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PSXCPU_R0, PSXCPU_R1,
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PSXCPU_R2, PSXCPU_R3,
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PSXCPU_R4, PSXCPU_R5,
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PSXCPU_R6, PSXCPU_R7,
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PSXCPU_R8, PSXCPU_R9,
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PSXCPU_R10, PSXCPU_R11,
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PSXCPU_R12, PSXCPU_R13,
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PSXCPU_R14, PSXCPU_R15,
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PSXCPU_R16, PSXCPU_R17,
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PSXCPU_R18, PSXCPU_R19,
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PSXCPU_R20, PSXCPU_R21,
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PSXCPU_R22, PSXCPU_R23,
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PSXCPU_R24, PSXCPU_R25,
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PSXCPU_R26, PSXCPU_R27,
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PSXCPU_R28, PSXCPU_R29,
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PSXCPU_R30, PSXCPU_R31,
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PSXCPU_CP0R0, PSXCPU_CP0R1,
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PSXCPU_CP0R2, PSXCPU_CP0R3,
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PSXCPU_CP0R4, PSXCPU_CP0R5,
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PSXCPU_CP0R6, PSXCPU_CP0R7,
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PSXCPU_CP0R8, PSXCPU_CP0R9,
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PSXCPU_CP0R10, PSXCPU_CP0R11,
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PSXCPU_CP0R12, PSXCPU_CP0R13,
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PSXCPU_CP0R14, PSXCPU_CP0R15,
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PSXCPU_CP2DR0, PSXCPU_CP2DR1,
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PSXCPU_CP2DR2, PSXCPU_CP2DR3,
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PSXCPU_CP2DR4, PSXCPU_CP2DR5,
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PSXCPU_CP2DR6, PSXCPU_CP2DR7,
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PSXCPU_CP2DR8, PSXCPU_CP2DR9,
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PSXCPU_CP2DR10, PSXCPU_CP2DR11,
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PSXCPU_CP2DR12, PSXCPU_CP2DR13,
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PSXCPU_CP2DR14, PSXCPU_CP2DR15,
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PSXCPU_CP2DR16, PSXCPU_CP2DR17,
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PSXCPU_CP2DR18, PSXCPU_CP2DR19,
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PSXCPU_CP2DR20, PSXCPU_CP2DR21,
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PSXCPU_CP2DR22, PSXCPU_CP2DR23,
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PSXCPU_CP2DR24, PSXCPU_CP2DR25,
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PSXCPU_CP2DR26, PSXCPU_CP2DR27,
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PSXCPU_CP2DR28, PSXCPU_CP2DR29,
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PSXCPU_CP2DR30, PSXCPU_CP2DR31,
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PSXCPU_CP2CR0, PSXCPU_CP2CR1,
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PSXCPU_CP2CR2, PSXCPU_CP2CR3,
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PSXCPU_CP2CR4, PSXCPU_CP2CR5,
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PSXCPU_CP2CR6, PSXCPU_CP2CR7,
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PSXCPU_CP2CR8, PSXCPU_CP2CR9,
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PSXCPU_CP2CR10, PSXCPU_CP2CR11,
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PSXCPU_CP2CR12, PSXCPU_CP2CR13,
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PSXCPU_CP2CR14, PSXCPU_CP2CR15,
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PSXCPU_CP2CR16, PSXCPU_CP2CR17,
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PSXCPU_CP2CR18, PSXCPU_CP2CR19,
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PSXCPU_CP2CR20, PSXCPU_CP2CR21,
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PSXCPU_CP2CR22, PSXCPU_CP2CR23,
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PSXCPU_CP2CR24, PSXCPU_CP2CR25,
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PSXCPU_CP2CR26, PSXCPU_CP2CR27,
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PSXCPU_CP2CR28, PSXCPU_CP2CR29,
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PSXCPU_CP2CR30, PSXCPU_CP2CR31
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};
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#define MIPS_INT_NONE ( -1 )
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#define PSXCPU_IRQ0 ( 0 )
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#define PSXCPU_IRQ1 ( 1 )
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#define PSXCPU_IRQ2 ( 2 )
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#define PSXCPU_IRQ3 ( 3 )
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#define PSXCPU_IRQ4 ( 4 )
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#define PSXCPU_IRQ5 ( 5 )
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#define MIPS_IRQ0 ( 0 )
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#define MIPS_IRQ1 ( 1 )
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#define MIPS_IRQ2 ( 2 )
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#define MIPS_IRQ3 ( 3 )
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#define MIPS_IRQ4 ( 4 )
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#define MIPS_IRQ5 ( 5 )
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#define MIPS_BYTE_EXTEND( a ) ( (INT32)(INT8)a )
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#define MIPS_WORD_EXTEND( a ) ( (INT32)(INT16)a )
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#define PSXCPU_BYTE_EXTEND( a ) ( (INT32)(INT8)a )
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#define PSXCPU_WORD_EXTEND( a ) ( (INT32)(INT16)a )
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#define INS_OP( op ) ( ( op >> 26 ) & 63 )
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#define INS_RS( op ) ( ( op >> 21 ) & 31 )
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@ -205,10 +203,16 @@ enum
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#define CF_TLBP ( 8 )
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#define CF_RFE ( 16 )
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extern unsigned DasmMIPS( char *buffer, UINT32 pc, const UINT8 *opram );
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typedef struct _DasmPSXCPU_state DasmPSXCPU_state;
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#if (HAS_PSXCPU)
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extern CPU_GET_INFO( psxcpu );
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#endif
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struct _DasmPSXCPU_state
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{
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UINT32 pc;
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int delayr;
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UINT32 delayv;
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UINT32 r[ 32 ];
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};
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extern unsigned DasmPSXCPU( DasmPSXCPU_state *state, char *buffer, UINT32 pc, const UINT8 *opram );
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#endif /* __PSX_H__ */
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@ -1,5 +1,5 @@
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/*
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* MIPS disassembler for the MAME project written by smf
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* PSXCPU disassembler for the MAME project written by smf
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*
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*/
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@ -120,42 +120,38 @@ static const char *const s_gtelm[] =
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"0", "1"
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};
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static char *effective_address( UINT32 pc, UINT32 op )
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static char *effective_address( DasmPSXCPU_state *state, UINT32 pc, UINT32 op )
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{
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static char s_address[ 20 ];
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#ifndef STANDALONE
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if( pc == cpu_get_pc(Machine->activecpu) )
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if( state != NULL && state->pc == pc )
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{
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sprintf( s_address, "%s(%s) ; 0x%08x", make_signed_hex_str_16( INS_IMMEDIATE( op ) ), s_cpugenreg[ INS_RS( op ) ],
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(UINT32)( cpu_get_reg( Machine->activecpu, MIPS_R0 + INS_RS( op ) ) + (INT16)INS_IMMEDIATE( op ) ) );
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(UINT32)( state->r[ INS_RS( op ) ] + (INT16)INS_IMMEDIATE( op ) ) );
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return s_address;
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}
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#endif
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sprintf( s_address, "%s(%s)", make_signed_hex_str_16( INS_IMMEDIATE( op ) ), s_cpugenreg[ INS_RS( op ) ] );
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return s_address;
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}
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static UINT32 relative_address( UINT32 pc, UINT32 op )
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static UINT32 relative_address( DasmPSXCPU_state *state, UINT32 pc, UINT32 op )
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{
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UINT32 nextpc = pc + 4;
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#ifndef STANDALONE
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if( pc == cpu_get_pc(Machine->activecpu) && cpu_get_reg( Machine->activecpu, MIPS_DELAYR ) == 32 )
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if( state != NULL && state->pc == pc && state->delayr == PSXCPU_DELAYR_PC )
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{
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nextpc = cpu_get_reg( Machine->activecpu, MIPS_DELAYV );
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nextpc = state->delayv;
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}
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#endif
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return nextpc + ( MIPS_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 );
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return nextpc + ( PSXCPU_WORD_EXTEND( INS_IMMEDIATE( op ) ) << 2 );
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}
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static UINT32 jump_address( UINT32 pc, UINT32 op )
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static UINT32 jump_address( DasmPSXCPU_state *state, UINT32 pc, UINT32 op )
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{
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UINT32 nextpc = pc + 4;
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#ifndef STANDALONE
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if( pc == cpu_get_pc(Machine->activecpu) && cpu_get_reg( Machine->activecpu, MIPS_DELAYR ) == 32 )
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if( state != NULL && state->pc == pc && state->delayr == PSXCPU_DELAYR_PC )
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{
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nextpc = cpu_get_reg( Machine->activecpu, MIPS_DELAYV );
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nextpc = state->delayv;
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}
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#endif
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return ( nextpc & 0xf0000000 ) + ( INS_TARGET( op ) << 2 );
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}
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@ -185,7 +181,7 @@ static char *upper_address( UINT32 op, const UINT8 *opram )
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return s_address;
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}
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unsigned DasmMIPS( char *buffer, UINT32 pc, const UINT8 *opram )
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unsigned DasmPSXCPU( DasmPSXCPU_state *state, char *buffer, UINT32 pc, const UINT8 *opram )
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{
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UINT32 op;
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const UINT8 *oldopram;
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@ -309,45 +305,45 @@ unsigned DasmMIPS( char *buffer, UINT32 pc, const UINT8 *opram )
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case RT_BLTZ:
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if( INS_RT( op ) == RT_BLTZAL )
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{
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sprintf( buffer, "bltzal %s,$%08x", s_cpugenreg[ INS_RS( op ) ], relative_address( pc, op ) );
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sprintf( buffer, "bltzal %s,$%08x", s_cpugenreg[ INS_RS( op ) ], relative_address( state, pc, op ) );
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flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA( 1 );
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}
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else
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{
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sprintf( buffer, "bltz %s,$%08x", s_cpugenreg[ INS_RS( op ) ], relative_address( pc, op ) );
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sprintf( buffer, "bltz %s,$%08x", s_cpugenreg[ INS_RS( op ) ], relative_address( state, pc, op ) );
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}
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break;
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case RT_BGEZ:
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if( INS_RT( op ) == RT_BGEZAL )
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{
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sprintf( buffer, "bgezal %s,$%08x", s_cpugenreg[ INS_RS( op ) ], relative_address( pc, op ) );
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sprintf( buffer, "bgezal %s,$%08x", s_cpugenreg[ INS_RS( op ) ], relative_address( state, pc, op ) );
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flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA( 1 );
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}
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else
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{
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sprintf( buffer, "bgez %s,$%08x", s_cpugenreg[ INS_RS( op ) ], relative_address( pc, op ) );
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sprintf( buffer, "bgez %s,$%08x", s_cpugenreg[ INS_RS( op ) ], relative_address( state, pc, op ) );
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}
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break;
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}
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break;
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case OP_J:
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sprintf( buffer, "j $%08x", jump_address( pc, op ) );
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sprintf( buffer, "j $%08x", jump_address( state, pc, op ) );
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break;
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case OP_JAL:
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sprintf( buffer, "jal $%08x", jump_address( pc, op ) );
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sprintf( buffer, "jal $%08x", jump_address( state, pc, op ) );
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flags = DASMFLAG_STEP_OVER | DASMFLAG_STEP_OVER_EXTRA( 1 );
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break;
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case OP_BEQ:
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sprintf( buffer, "beq %s,%s,$%08x", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ], relative_address( pc, op ) );
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sprintf( buffer, "beq %s,%s,$%08x", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ], relative_address( state, pc, op ) );
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break;
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case OP_BNE:
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sprintf( buffer, "bne %s,%s,$%08x", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ], relative_address( pc, op ) );
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sprintf( buffer, "bne %s,%s,$%08x", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ], relative_address( state, pc, op ) );
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break;
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case OP_BLEZ:
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sprintf( buffer, "blez %s,%s,$%08x", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ], relative_address( pc, op ) );
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sprintf( buffer, "blez %s,%s,$%08x", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ], relative_address( state, pc, op ) );
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break;
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case OP_BGTZ:
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sprintf( buffer, "bgtz %s,%s,$%08x", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ], relative_address( pc, op ) );
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sprintf( buffer, "bgtz %s,%s,$%08x", s_cpugenreg[ INS_RS( op ) ], s_cpugenreg[ INS_RT( op ) ], relative_address( state, pc, op ) );
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break;
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case OP_ADDI:
|
||||
sprintf( buffer, "addi %s,%s,%s", s_cpugenreg[ INS_RT( op ) ], s_cpugenreg[ INS_RS( op ) ], make_signed_hex_str_16( INS_IMMEDIATE( op ) ) );
|
||||
@ -393,10 +389,10 @@ unsigned DasmMIPS( char *buffer, UINT32 pc, const UINT8 *opram )
|
||||
switch( INS_BC( op ) )
|
||||
{
|
||||
case BC_BCF:
|
||||
sprintf( buffer, "bc0f $%08x", relative_address( pc, op ) );
|
||||
sprintf( buffer, "bc0f $%08x", relative_address( state, pc, op ) );
|
||||
break;
|
||||
case BC_BCT:
|
||||
sprintf( buffer, "bc0t $%08x", relative_address( pc, op ) );
|
||||
sprintf( buffer, "bc0t $%08x", relative_address( state, pc, op ) );
|
||||
break;
|
||||
}
|
||||
break;
|
||||
@ -449,10 +445,10 @@ unsigned DasmMIPS( char *buffer, UINT32 pc, const UINT8 *opram )
|
||||
switch( INS_BC( op ) )
|
||||
{
|
||||
case BC_BCF:
|
||||
sprintf( buffer, "bc1f $%08x", relative_address( pc, op ) );
|
||||
sprintf( buffer, "bc1f $%08x", relative_address( state, pc, op ) );
|
||||
break;
|
||||
case BC_BCT:
|
||||
sprintf( buffer, "bc1t $%08x", relative_address( pc, op ) );
|
||||
sprintf( buffer, "bc1t $%08x", relative_address( state, pc, op ) );
|
||||
break;
|
||||
}
|
||||
break;
|
||||
@ -486,10 +482,10 @@ unsigned DasmMIPS( char *buffer, UINT32 pc, const UINT8 *opram )
|
||||
switch( INS_BC( op ) )
|
||||
{
|
||||
case BC_BCF:
|
||||
sprintf( buffer, "bc2f $%08x", relative_address( pc, op ) );
|
||||
sprintf( buffer, "bc2f $%08x", relative_address( state, pc, op ) );
|
||||
break;
|
||||
case BC_BCT:
|
||||
sprintf( buffer, "bc2t $%08x", relative_address( pc, op ) );
|
||||
sprintf( buffer, "bc2t $%08x", relative_address( state, pc, op ) );
|
||||
break;
|
||||
}
|
||||
break;
|
||||
@ -664,10 +660,10 @@ unsigned DasmMIPS( char *buffer, UINT32 pc, const UINT8 *opram )
|
||||
switch( INS_BC( op ) )
|
||||
{
|
||||
case BC_BCF:
|
||||
sprintf( buffer, "bc3f $%08x", relative_address( pc, op ) );
|
||||
sprintf( buffer, "bc3f $%08x", relative_address( state, pc, op ) );
|
||||
break;
|
||||
case BC_BCT:
|
||||
sprintf( buffer, "bc3t $%08x", relative_address( pc, op ) );
|
||||
sprintf( buffer, "bc3t $%08x", relative_address( state, pc, op ) );
|
||||
break;
|
||||
}
|
||||
break;
|
||||
@ -682,64 +678,64 @@ unsigned DasmMIPS( char *buffer, UINT32 pc, const UINT8 *opram )
|
||||
}
|
||||
break;
|
||||
case OP_LB:
|
||||
sprintf( buffer, "lb %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( pc, op ) );
|
||||
sprintf( buffer, "lb %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
|
||||
break;
|
||||
case OP_LH:
|
||||
sprintf( buffer, "lh %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( pc, op ) );
|
||||
sprintf( buffer, "lh %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
|
||||
break;
|
||||
case OP_LWL:
|
||||
sprintf( buffer, "lwl %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( pc, op ) );
|
||||
sprintf( buffer, "lwl %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
|
||||
break;
|
||||
case OP_LW:
|
||||
sprintf( buffer, "lw %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( pc, op ) );
|
||||
sprintf( buffer, "lw %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
|
||||
break;
|
||||
case OP_LBU:
|
||||
sprintf( buffer, "lbu %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( pc, op ) );
|
||||
sprintf( buffer, "lbu %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
|
||||
break;
|
||||
case OP_LHU:
|
||||
sprintf( buffer, "lhu %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( pc, op ) );
|
||||
sprintf( buffer, "lhu %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
|
||||
break;
|
||||
case OP_LWR:
|
||||
sprintf( buffer, "lwr %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( pc, op ) );
|
||||
sprintf( buffer, "lwr %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
|
||||
break;
|
||||
case OP_SB:
|
||||
sprintf( buffer, "sb %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( pc, op ) );
|
||||
sprintf( buffer, "sb %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
|
||||
break;
|
||||
case OP_SH:
|
||||
sprintf( buffer, "sh %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( pc, op ) );
|
||||
sprintf( buffer, "sh %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
|
||||
break;
|
||||
case OP_SWL:
|
||||
sprintf( buffer, "swl %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( pc, op ) );
|
||||
sprintf( buffer, "swl %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
|
||||
break;
|
||||
case OP_SW:
|
||||
sprintf( buffer, "sw %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( pc, op ) );
|
||||
sprintf( buffer, "sw %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
|
||||
break;
|
||||
case OP_SWR:
|
||||
sprintf( buffer, "swr %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( pc, op ) );
|
||||
sprintf( buffer, "swr %s,%s", s_cpugenreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
|
||||
break;
|
||||
case OP_LWC0:
|
||||
sprintf( buffer, "lwc0 %s,%s", s_cp0genreg[ INS_RT( op ) ], effective_address( pc, op ) );
|
||||
sprintf( buffer, "lwc0 %s,%s", s_cp0genreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
|
||||
break;
|
||||
case OP_LWC1:
|
||||
sprintf( buffer, "lwc1 %s,%s", s_cp1genreg[ INS_RT( op ) ], effective_address( pc, op ) );
|
||||
sprintf( buffer, "lwc1 %s,%s", s_cp1genreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
|
||||
break;
|
||||
case OP_LWC2:
|
||||
sprintf( buffer, "lwc2 %s,%s", s_cp2genreg[ INS_RT( op ) ], effective_address( pc, op ) );
|
||||
sprintf( buffer, "lwc2 %s,%s", s_cp2genreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
|
||||
break;
|
||||
case OP_LWC3:
|
||||
sprintf( buffer, "lwc3 %s,%s", s_cp2genreg[ INS_RT( op ) ], effective_address( pc, op ) );
|
||||
sprintf( buffer, "lwc3 %s,%s", s_cp2genreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
|
||||
break;
|
||||
case OP_SWC0:
|
||||
sprintf( buffer, "swc0 %s,%s", s_cp0genreg[ INS_RT( op ) ], effective_address( pc, op ) );
|
||||
sprintf( buffer, "swc0 %s,%s", s_cp0genreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
|
||||
break;
|
||||
case OP_SWC1:
|
||||
sprintf( buffer, "swc1 %s,%s", s_cp1genreg[ INS_RT( op ) ], effective_address( pc, op ) );
|
||||
sprintf( buffer, "swc1 %s,%s", s_cp1genreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
|
||||
break;
|
||||
case OP_SWC2:
|
||||
sprintf( buffer, "swc2 %s,%s", s_cp2genreg[ INS_RT( op ) ], effective_address( pc, op ) );
|
||||
sprintf( buffer, "swc2 %s,%s", s_cp2genreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
|
||||
break;
|
||||
case OP_SWC3:
|
||||
sprintf( buffer, "swc3 %s,%s", s_cp2genreg[ INS_RT( op ) ], effective_address( pc, op ) );
|
||||
sprintf( buffer, "swc3 %s,%s", s_cp2genreg[ INS_RT( op ) ], effective_address( state, pc, op ) );
|
||||
break;
|
||||
}
|
||||
return ( opram - oldopram ) | flags | DASMFLAG_SUPPORTED;
|
||||
@ -72,12 +72,12 @@ static void psx_irq_update( running_machine *machine )
|
||||
if( ( m_n_irqdata & m_n_irqmask ) != 0 )
|
||||
{
|
||||
verboselog( 2, "psx irq assert\n" );
|
||||
cpu_set_input_line(machine->cpu[0], MIPS_IRQ0, ASSERT_LINE );
|
||||
cpu_set_input_line(machine->cpu[0], PSXCPU_IRQ0, ASSERT_LINE );
|
||||
}
|
||||
else
|
||||
{
|
||||
verboselog( 2, "psx irq clear\n" );
|
||||
cpu_set_input_line(machine->cpu[0], MIPS_IRQ0, CLEAR_LINE );
|
||||
cpu_set_input_line(machine->cpu[0], PSXCPU_IRQ0, CLEAR_LINE );
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user