Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-04-22 16:31:49 +03:00
Code Issues Actions Packages Projects Releases Wiki Activity

tmp95c061, tmp95c063: Break up the register blocks (nw)

Browse Source
This commit is contained in:
AJR 2020-06-18 21:32:26 -04:00
parent 9c36794ded
commit 2507aea082
6 changed files with 2259 additions and 979 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/devices/cpu/tlcs900/tlcs900.cpp
View File

@ -108,7 +108,6 @@ void tlcs900h_device::device_start()
save_item( NAME(m_dmad) );
save_item( NAME(m_dmac) );
save_item( NAME(m_dmam) );
save_item( NAME(m_reg) );
save_item( NAME(m_timer_pre) );
save_item( NAME(m_timer) );
save_item( NAME(m_timer_change) );
@ -166,6 +165,21 @@ void tlcs900h_device::device_start()
set_icountptr(m_icount);
}
void tlcs900h_device::device_reset()
{
m_pc.b.l = RDMEM( 0xFFFF00 );
m_pc.b.h = RDMEM( 0xFFFF01 );
m_pc.b.h2 = RDMEM( 0xFFFF02 );
m_pc.b.h3 = 0;
/* system mode, iff set to 111, max mode, register bank 0 */
m_sr.d = 0xF800;
m_regbank = 0;
m_xssp.d = 0x0100;
m_halted = 0;
m_check_irqs = 0;
m_prefetch_clear = true;
}
void tlcs900h_device::state_string_export(const device_state_entry &entry, std::string &str) const
{

2
src/devices/cpu/tlcs900/tlcs900.h
View File

@ -52,6 +52,7 @@ protected:
// device-level overrides
virtual void device_start() override;
virtual void device_reset() override;
// device_execute_interface overrides
virtual uint32_t execute_min_cycles() const noexcept override { return 1; } /* FIXME */
@ -100,7 +101,6 @@ protected:
PAIR m_dmam[4];
/* Internal timers, irqs, etc */
uint8_t m_reg[0xa0];
uint32_t m_timer_pre;
uint8_t m_timer[6];
int m_timer_change[4];

1211
src/devices/cpu/tlcs900/tmp95c061.cpp
View File

File diff suppressed because it is too large Load Diff

152
src/devices/cpu/tlcs900/tmp95c061.h
View File

@ -50,14 +50,105 @@ protected:
void update_porta();
private:
uint8_t internal_r(offs_t offset);
void internal_w(offs_t offset, uint8_t data);
uint8_t p1_r();
void p1_w(uint8_t data);
void p1cr_w(uint8_t data);
uint8_t p2_r();
void p2_w(uint8_t data);
void p2fc_w(uint8_t data);
uint8_t p5_r();
void p5_w(uint8_t data);
void p5cr_w(uint8_t data);
void p5fc_w(uint8_t data);
uint8_t p6_r();
void p6_w(uint8_t data);
void p6fc_w(uint8_t data);
uint8_t p7_r();
void p7_w(uint8_t data);
void p7cr_w(uint8_t data);
void p7fc_w(uint8_t data);
uint8_t p8_r();
void p8_w(uint8_t data);
void p8cr_w(uint8_t data);
void p8fc_w(uint8_t data);
uint8_t p9_r();
uint8_t pa_r();
void pa_w(uint8_t data);
void pacr_w(uint8_t data);
void pafc_w(uint8_t data);
uint8_t pb_r();
void pb_w(uint8_t data);
void pbcr_w(uint8_t data);
void pbfc_w(uint8_t data);
uint8_t trun_r();
void trun_w(uint8_t data);
void treg01_w(offs_t offset, uint8_t data);
void t01mod_w(uint8_t data);
uint8_t tffcr_r();
void tffcr_w(uint8_t data);
void treg23_w(offs_t offset, uint8_t data);
void t23mod_w(uint8_t data);
uint8_t trdc_r();
void trdc_w(uint8_t data);
void treg45_w(offs_t offset, uint8_t data);
uint8_t cap12_r(offs_t offset);
uint8_t t4mod_r();
void t4mod_w(uint8_t data);
uint8_t t4ffcr_r();
void t4ffcr_w(uint8_t data);
uint8_t t45cr_r();
void t45cr_w(uint8_t data);
void treg67_w(offs_t offset, uint8_t data);
uint8_t cap34_r(offs_t offset);
uint8_t t5mod_r();
void t5mod_w(uint8_t data);
uint8_t t5ffcr_r();
void t5ffcr_w(uint8_t data);
uint8_t pgreg_r(offs_t offset);
void pgreg_w(offs_t offset, uint8_t data);
uint8_t pg01cr_r();
void pg01cr_w(uint8_t data);
uint8_t wdmod_r();
void wdmod_w(uint8_t data);
void wdcr_w(uint8_t data);
uint8_t sc0buf_r();
void sc0buf_w(uint8_t data);
uint8_t sc0cr_r();
void sc0cr_w(uint8_t data);
uint8_t sc0mod_r();
void sc0mod_w(uint8_t data);
uint8_t br0cr_r();
void br0cr_w(uint8_t data);
uint8_t sc1buf_r();
void sc1buf_w(uint8_t data);
uint8_t sc1cr_r();
void sc1cr_w(uint8_t data);
uint8_t sc1mod_r();
void sc1mod_w(uint8_t data);
uint8_t br1cr_r();
void br1cr_w(uint8_t data);
uint8_t ode_r();
void ode_w(uint8_t data);
uint8_t adreg_r(offs_t offset);
uint8_t admod_r();
void admod_w(uint8_t data);
uint8_t inte_r(offs_t offset);
void inte_w(offs_t offset, uint8_t data);
void iimc_w(uint8_t data);
void dmav_w(offs_t offset, uint8_t data);
void bcs_w(offs_t offset, uint8_t data);
void bexcs_w(uint8_t data);
uint8_t msar01_r(offs_t offset);
void msar01_w(offs_t offset, uint8_t data);
uint8_t msar23_r(offs_t offset);
void msar23_w(offs_t offset, uint8_t data);
uint8_t drefcr_r();
void drefcr_w(uint8_t data);
uint8_t dmemcr_r();
void dmemcr_w(uint8_t data);
void internal_mem(address_map &map);
uint8_t m_to1;
uint8_t m_to3;
// Port 1: 8 bit I/O. Shared with D8-D15
devcb_read8 m_port1_read;
devcb_write8 m_port1_write;
@ -91,6 +182,57 @@ private:
// Port B: 8 bit I/O. Shared with TI4/INT4, TI5/INT5, TI6/INT6, TI7/INT7, TO4, TO5, TO6
devcb_read8 m_portb_read;
devcb_write8 m_portb_write;
// I/O Port Control
uint8_t m_port_latch[0xc];
uint8_t m_port_control[0xc];
uint8_t m_port_function[0xc];
// Timer Control
uint8_t m_trun;
uint8_t m_t8_reg[4];
uint8_t m_t8_mode[2];
uint8_t m_t8_invert;
uint8_t m_trdc;
uint8_t m_to1;
uint8_t m_to3;
uint16_t m_t16_reg[4];
uint16_t m_t16_cap[4];
uint8_t m_t16_mode[2];
uint8_t m_t16_invert[2];
uint8_t m_t45cr;
// Pattern Generator
uint8_t m_pgreg[2];
uint8_t m_pg01cr;
// Watchdog Timer
uint8_t m_watchdog_mode;
// Serial Channel
uint8_t m_serial_control[2];
uint8_t m_serial_mode[2];
uint8_t m_baud_rate[2];
uint8_t m_od_enable;
// A/D Converter Control
uint16_t m_ad_result[4];
uint8_t m_ad_mode;
// Interrupt Control
uint8_t m_int_reg[0xb];
uint8_t m_iimc;
uint8_t m_dma_vector[4];
// Chip Select/Wait Control
uint8_t m_block_cs[4];
uint8_t m_external_cs;
uint8_t m_mem_start_reg[4];
uint8_t m_mem_start_mask[4];
// DRAM Control
uint8_t m_dram_refresh;
uint8_t m_dram_access;
};
#endif // MAME_CPU_TLCS900_TMP95C061_H

1676
src/devices/cpu/tlcs900/tmp95c063.cpp
View File

File diff suppressed because it is too large Load Diff

181
src/devices/cpu/tlcs900/tmp95c063.h
View File

@ -54,8 +54,131 @@ protected:
virtual void tlcs900_handle_timers() override;
private:
uint8_t internal_r(offs_t offset);
void internal_w(offs_t offset, uint8_t data);
uint8_t p1_r();
void p1_w(uint8_t data);
void p1cr_w(uint8_t data);
uint8_t p2_r();
void p2_w(uint8_t data);
void p2fc_w(uint8_t data);
uint8_t p5_r();
void p5_w(uint8_t data);
void p5cr_w(uint8_t data);
void p5fc_w(uint8_t data);
uint8_t p6_r();
void p6_w(uint8_t data);
void p6fc_w(uint8_t data);
uint8_t p7_r();
void p7_w(uint8_t data);
void p7cr_w(uint8_t data);
void p7fc_w(uint8_t data);
uint8_t p8_r();
void p8_w(uint8_t data);
void p8cr_w(uint8_t data);
void p8fc_w(uint8_t data);
uint8_t p9_r();
void p9_w(uint8_t data);
void p9cr_w(uint8_t data);
void p9fc_w(uint8_t data);
uint8_t pa_r();
void pa_w(uint8_t data);
void pacr_w(uint8_t data);
void pafc_w(uint8_t data);
uint8_t pb_r();
void pb_w(uint8_t data);
void pbcr_w(uint8_t data);
void pbfc_w(uint8_t data);
uint8_t pc_r();
uint8_t pd_r();
void pd_w(uint8_t data);
void pdcr_w(uint8_t data);
uint8_t pe_r();
void pe_w(uint8_t data);
void pecr_w(uint8_t data);
uint8_t t8run_r();
void t8run_w(uint8_t data);
void treg01_w(offs_t offset, uint8_t data);
uint8_t t01mod_r();
void t01mod_w(uint8_t data);
uint8_t t02ffcr_r();
void t02ffcr_w(uint8_t data);
void treg23_w(offs_t offset, uint8_t data);
uint8_t t23mod_r();
void t23mod_w(uint8_t data);
uint8_t trdc_r();
void trdc_w(uint8_t data);
void treg45_w(offs_t offset, uint8_t data);
uint8_t t45mod_r();
void t45mod_w(uint8_t data);
uint8_t t46ffcr_r();
void t46ffcr_w(uint8_t data);
void treg67_w(offs_t offset, uint8_t data);
uint8_t t67mod_r();
void t67mod_w(uint8_t data);
void treg89_w(offs_t offset, uint8_t data);
uint8_t cap12_r(offs_t offset);
uint8_t t8mod_r();
void t8mod_w(uint8_t data);
uint8_t t8ffcr_r();
void t8ffcr_w(uint8_t data);
uint8_t t89cr_r();
void t89cr_w(uint8_t data);
uint8_t t16run_r();
void t16run_w(uint8_t data);
void tregab_w(offs_t offset, uint8_t data);
uint8_t cap34_r(offs_t offset);
uint8_t t9mod_r();
void t9mod_w(uint8_t data);
uint8_t t9ffcr_r();
void t9ffcr_w(uint8_t data);
uint8_t pgreg_r(offs_t offset);
void pgreg_w(offs_t offset, uint8_t data);
uint8_t pg01cr_r();
void pg01cr_w(uint8_t data);
uint8_t wdmod_r();
void wdmod_w(uint8_t data);
void wdcr_w(uint8_t data);
uint8_t sc0buf_r();
void sc0buf_w(uint8_t data);
uint8_t sc0cr_r();
void sc0cr_w(uint8_t data);
uint8_t sc0mod_r();
void sc0mod_w(uint8_t data);
uint8_t br0cr_r();
void br0cr_w(uint8_t data);
uint8_t sc1buf_r();
void sc1buf_w(uint8_t data);
uint8_t sc1cr_r();
void sc1cr_w(uint8_t data);
uint8_t sc1mod_r();
void sc1mod_w(uint8_t data);
uint8_t br1cr_r();
void br1cr_w(uint8_t data);
uint8_t ode_r();
void ode_w(uint8_t data);
uint8_t admod1_r();
void admod1_w(uint8_t data);
uint8_t admod2_r();
void admod2_w(uint8_t data);
uint8_t adreg_r(offs_t offset);
uint8_t inte_r(offs_t offset);
void inte_w(offs_t offset, uint8_t data);
void iimc_w(uint8_t data);
void dmav_w(offs_t offset, uint8_t data);
void bcs_w(offs_t offset, uint8_t data);
void bexcs_w(uint8_t data);
uint8_t msar_r(offs_t offset);
void msar_w(offs_t offset, uint8_t data);
uint8_t drefcr1_r();
void drefcr1_w(uint8_t data);
uint8_t dmemcr1_r();
void dmemcr1_w(uint8_t data);
uint8_t drefcr3_r();
void drefcr3_w(uint8_t data);
uint8_t dmemcr3_r();
void dmemcr3_w(uint8_t data);
uint8_t dadrv_r();
void dadrv_w(uint8_t data);
void dareg_w(offs_t offset, uint8_t data);
void internal_mem(address_map &map);
@ -107,6 +230,60 @@ private:
// analogue inputs, sampled at 10 bits
devcb_read16::array<8> m_an_read;
// I/O Port Control
uint8_t m_port_latch[0xf];
uint8_t m_port_control[0xf];
uint8_t m_port_function[0xf];
// Timer Control
uint8_t m_t8run;
uint8_t m_t8_reg[8];
uint8_t m_t8_mode[4];
uint8_t m_t8_invert[2];
uint8_t m_trdc;
uint16_t m_t16_reg[4];
uint16_t m_t16_cap[4];
uint8_t m_t16_mode[2];
uint8_t m_t16_invert[2];
uint8_t m_t89cr;
uint8_t m_t16run;
// Pattern Generator
uint8_t m_pgreg[2];
uint8_t m_pg01cr;
// Watchdog Timer
uint8_t m_watchdog_mode;
// Serial Channel
uint8_t m_serial_control[2];
uint8_t m_serial_mode[2];
uint8_t m_baud_rate[2];
uint8_t m_od_enable;
// A/D Converter Control
uint8_t m_ad_mode1;
uint8_t m_ad_mode2;
uint16_t m_ad_result[4];
// Interrupt Control
uint8_t m_int_reg[0xf];
uint8_t m_iimc;
uint8_t m_dma_vector[4];
// Chip Select/Wait Control
uint8_t m_block_cs[4];
uint8_t m_external_cs;
uint8_t m_mem_start_reg[4];
uint8_t m_mem_start_mask[4];
// DRAM Control
uint8_t m_dram_refresh[2];
uint8_t m_dram_access[2];
// D/A Converter Control
uint8_t m_da_drive;
};
#endif // MAME_CPU_TLCS900_TMP95C063_H