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mcs48.c: Write p1 and p2 on reset

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These ports are actually ports which sink current on logical 0. With a logical 1, they are in high impedance mode and may be read. The high impedance is treated as logical 1 by TTL gates connected to them.
This commit is contained in:
Couriersud 2008-08-29 22:52:26 +00:00
parent bd39d9e8c9
commit 299fc7ec1a
1 changed files with 2 additions and 0 deletions
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src/emu/cpu/mcs48/mcs48.c
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@ -772,6 +772,8 @@ static void mcs48_reset(void)
bus_w(0xff);
mcs48.p1 = 0xff;
mcs48.p2 = 0xff;
port_w(1, mcs48.p1);
port_w(2, mcs48.p2);
mcs48.tirq_enabled = FALSE;
mcs48.xirq_enabled = FALSE;
mcs48.timecount_enabled = 0;