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https://github.com/holub/mame
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s3virge: made a start at fixing up some of the VESA video modes (no whatsnew)
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mahlemiut
parent
0a2e7efba4
commit
29e1ba5bd9
@ -1294,16 +1294,16 @@ void vga_device::recompute_params_clock(int divisor, int xtal)
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refresh = HZ_TO_ATTOSECONDS(pixel_clock) * (hblank_period) * vblank_period;
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machine().primary_screen->configure((hblank_period), (vblank_period), visarea, refresh );
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// popmessage("%d %d\n",vga.crtc.horz_total * 8,vga.crtc.vert_total);
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//popmessage("%d %d\n",vga.crtc.horz_total * 8,vga.crtc.vert_total);
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m_vblank_timer->adjust( machine().primary_screen->time_until_pos(vga.crtc.vert_blank_start) );
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}
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void vga_device::recompute_params()
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{
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recompute_params_clock(1, (vga.miscellaneous_output & 0xc) ? XTAL_28_63636MHz : XTAL_25_1748MHz);
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if(vga.miscellaneous_output & 8)
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logerror("Warning: VGA external clock latch selected\n");
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else
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recompute_params_clock(1, (vga.miscellaneous_output & 0xc) ? XTAL_28_63636MHz : XTAL_25_1748MHz);
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}
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void vga_device::crtc_reg_write(UINT8 index, UINT8 data)
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@ -1311,7 +1311,6 @@ void vga_device::crtc_reg_write(UINT8 index, UINT8 data)
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/* Doom does this */
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// if(vga.crtc.protect_enable && index <= 0x07)
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// printf("write to protected address %02x\n",index);
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switch(index)
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{
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case 0x00:
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@ -1488,16 +1487,16 @@ UINT8 vga_device::vga_vblank()
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if(vblank_end > vga.crtc.vert_total)
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{
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vblank_end -= vga.crtc.vert_total;
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if(vpos >= vblank_start || vpos < vblank_end)
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if(vpos >= vblank_start || vpos <= vblank_end)
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res = 1;
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}
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else
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{
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if(vpos >= vblank_start && vpos < vblank_end)
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if(vpos >= vblank_start && vpos <= vblank_end)
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res = 1;
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}
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// popmessage("%d %d %d",vblank_start,vblank_end,vga.crtc.vert_total);
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//popmessage("%d %d %d - SR1=%02x",vblank_start,vblank_end,vga.crtc.vert_total,vga.sequencer.data[1]);
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return res;
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}
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@ -5443,7 +5442,7 @@ void cirrus_vga_device::cirrus_define_video_mode()
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}
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}
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UINT8 cirrus_vga_device::cirrus_seq_reg_read(UINT8 index)
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UINT8 cirrus_vga_device::cirrus_seq_reg_read(UINT8 index)
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{
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UINT8 res;
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@ -5541,7 +5540,7 @@ void s3virge_vga_device::device_start()
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// copy over interfaces
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vga.read_dipswitch = read8_delegate(); //read_dipswitch;
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vga.svga_intf.seq_regcount = 0x08;
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vga.svga_intf.seq_regcount = 0x1c;
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vga.svga_intf.crtc_regcount = 0x19;
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vga.svga_intf.vram_size = 0x400000;
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vga.memory = auto_alloc_array_clear(machine(), UINT8, vga.svga_intf.vram_size);
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@ -5599,6 +5598,9 @@ UINT8 s3virge_vga_device::s3_crtc_reg_read(UINT8 index)
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case 0x42: // CR42 Mode Control
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res = s3.cr42 & 0x0f; // bit 5 set if interlaced, leave it unset for now.
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break;
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case 0x43:
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res = s3.cr43;
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break;
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case 0x45:
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res = s3.cursor_mode;
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break;
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@ -5672,62 +5674,17 @@ void s3virge_vga_device::s3_define_video_mode()
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{
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int divisor = 1;
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int xtal = (vga.miscellaneous_output & 0xc) ? XTAL_28_63636MHz : XTAL_25_1748MHz;
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double m,n;
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int r;
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if((vga.miscellaneous_output & 0xc) == 0x0c)
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{
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switch(s3.cr42 & 0x0f) // TODO: confirm clock settings
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{
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case 0:
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xtal = XTAL_25_1748MHz;
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break;
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case 1:
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xtal = XTAL_28_63636MHz;
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break;
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case 2:
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xtal = 40000000;
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break;
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case 3:
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xtal = 3000000;
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break;
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case 4:
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xtal = 50000000;
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break;
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case 5:
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xtal = 77000000;
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break;
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case 6:
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xtal = 36000000;
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break;
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case 7:
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xtal = 45000000;
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break;
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case 8:
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xtal = 1000000;
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break;
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case 9:
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xtal = 1000000;
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break;
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case 10:
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xtal = 79000000;
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break;
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case 11:
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xtal = 31000000;
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break;
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case 12:
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xtal = 94000000;
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break;
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case 13:
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xtal = 65000000;
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break;
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case 14:
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xtal = 75000000;
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break;
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case 15:
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xtal = 71000000;
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break;
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default:
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xtal = 1000000;
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}
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// Dot clock is set via SR12 and SR13
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m = vga.sequencer.data[0x13] & 0x7f;
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n = vga.sequencer.data[0x12] & 0x1f;
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r = (vga.sequencer.data[0x12] & 0x60) >> 5;
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xtal = (double)((m+2.0f) / ((n+2.0f)*(double)(1<<r))) * 16000000;
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//printf("DCLK set to %dHz M=%f N=%f R=%i\n",xtal,m,n,r);
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}
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if((s3.ext_misc_ctrl_2) >> 4)
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@ -5738,6 +5695,7 @@ void s3virge_vga_device::s3_define_video_mode()
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svga.rgb32_en = 0;
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switch((s3.ext_misc_ctrl_2) >> 4)
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{
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case 0x01: svga.rgb8_en = 1; divisor = 2; break;
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case 0x03: svga.rgb15_en = 1; divisor = 2; break;
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case 0x05: svga.rgb16_en = 1; divisor = 2; break;
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case 0x0d: svga.rgb32_en = 1; divisor = 2; break;
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@ -5746,18 +5704,23 @@ void s3virge_vga_device::s3_define_video_mode()
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}
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else
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{
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svga.rgb8_en = (s3.memory_config & 8) >> 3;
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svga.rgb8_en = (s3.cr3a & 0x10) >> 4;
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svga.rgb15_en = 0;
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svga.rgb16_en = 0;
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svga.rgb32_en = 0;
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}
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if(s3.cr43 & 0x80) // Horizontal clock doubling (techincally, doubles horizontal CRT parameters)
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divisor *= 2;
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recompute_params_clock(divisor, xtal);
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}
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void s3virge_vga_device::s3_crtc_reg_write(UINT8 index, UINT8 data)
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{
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if(index <= 0x18)
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{
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crtc_reg_write(index,data);
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s3_define_video_mode();
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}
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else
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{
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switch(index)
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@ -5782,12 +5745,18 @@ void s3virge_vga_device::s3_crtc_reg_write(UINT8 index, UINT8 data)
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/* TODO: reg lock mechanism */
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s3.reg_lock2 = data;
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break;
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case 0x3a:
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s3.cr3a = data;
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break;
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case 0x40:
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s3.enable_s3d = data & 0x01; // enable S3D registers at 0x100A
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s3.enable_s3d = data & 0x01; // enable S3D registers
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break;
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case 0x42:
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s3.cr42 = data; // bit 5 = interlace, bits 0-3 = dot clock (seems to be undocumented)
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break;
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case 0x43:
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s3.cr43 = data;
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break;
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/*
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3d4h index 45h (R/W): CR45 Hardware Graphics Cursor Mode
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bit 0 HWGC ENB. Hardware Graphics Cursor Enable. Set to enable the
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@ -6015,7 +5984,7 @@ bit 0 Vertical Total bit 10. Bit 10 of the Vertical Total register (3d4h
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svga.bank_r = svga.bank_w;
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break;
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default:
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if(LOG_8514) logerror("S3: 3D4 index %02x write %02x\n",index,data);
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if(LOG_8514) logerror("S3: CR%02X write %02x\n",index,data);
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break;
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}
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}
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@ -547,7 +547,9 @@ protected:
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UINT8 reg_lock2;
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UINT8 enable_8514;
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UINT8 enable_s3d;
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UINT8 cr3a;
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UINT8 cr42;
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UINT8 cr43;
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UINT8 cr53;
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UINT8 id_high;
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UINT8 id_low;
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