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https://github.com/holub/mame
synced 2025-04-22 00:11:58 +03:00
mips1: handle exceptions in delay slot instructions (nw)
I introduced this error when adding tlb support and modifying the exception code previously. This resolves the error, cleans up delayed branch handling and fixes a panic in the mips rx2030 and rx3230 driver.
This commit is contained in:
Patrick Mackinlay
parent
f74ad668aa
commit
2af742e9d1
@ -39,12 +39,12 @@
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#define UIMMVAL u16(op)
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#define LIMMVAL (op & 0x03ffffff)
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#define ADDPC(x) do { m_nextpc = m_pc + ((x) << 2); } while (0)
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#define ADDPCL(x,l) do { m_nextpc = m_pc + ((x) << 2); m_r[l] = m_pc + 4; } while (0)
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#define ABSPC(x) do { m_nextpc = (m_pc & 0xf0000000) | ((x) << 2); } while (0)
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#define ABSPCL(x,l) do { m_nextpc = (m_pc & 0xf0000000) | ((x) << 2); m_r[l] = m_pc + 4; } while (0)
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#define SETPC(x) do { m_nextpc = (x); } while (0)
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#define SETPCL(x,l) do { m_nextpc = (x); m_r[l] = m_pc + 4; } while (0)
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#define ADDPC(x) do { m_branch_state = BRANCH; m_branch_target = m_pc + 4 + ((x) << 2); } while (0)
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#define ADDPCL(x,l) do { m_branch_state = BRANCH; m_branch_target = m_pc + 4 + ((x) << 2); m_r[l] = m_pc + 8; } while (0)
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#define ABSPC(x) do { m_branch_state = BRANCH; m_branch_target = ((m_pc + 4) & 0xf0000000) | ((x) << 2); } while (0)
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#define ABSPCL(x,l) do { m_branch_state = BRANCH; m_branch_target = ((m_pc + 4) & 0xf0000000) | ((x) << 2); m_r[l] = m_pc + 8; } while (0)
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#define SETPC(x) do { m_branch_state = BRANCH; m_branch_target = (x); } while (0)
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#define SETPCL(x,l) do { m_branch_state = BRANCH; m_branch_target = (x); m_r[l] = m_pc + 8; } while (0)
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#define SR m_cpr[0][COP0_Status]
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#define CAUSE m_cpr[0][COP0_Cause]
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@ -61,6 +61,8 @@ DEFINE_DEVICE_TYPE(R3071, r3071_device, "r3071", "IDT R3071")
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DEFINE_DEVICE_TYPE(R3081, r3081_device, "r3081", "IDT R3081")
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DEFINE_DEVICE_TYPE(SONYPS2_IOP, iop_device, "sonyiop", "Sony Playstation 2 IOP")
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ALLOW_SAVE_TYPE(mips1core_device_base::branch_state_t);
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mips1core_device_base::mips1core_device_base(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, u32 cpurev, size_t icache_size, size_t dcache_size)
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: cpu_device(mconfig, type, tag, owner, clock)
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, m_program_config_be("program", ENDIANNESS_BIG, 32, 32)
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@ -71,9 +73,6 @@ mips1core_device_base::mips1core_device_base(const machine_config &mconfig, devi
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, m_hasfpu(false)
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, m_fpurev(0)
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, m_endianness(ENDIANNESS_BIG)
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, m_pc(0)
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, m_nextpc(0)
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, m_ppc(0)
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, m_icount(0)
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, m_icache_size(icache_size)
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, m_dcache_size(dcache_size)
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@ -177,7 +176,7 @@ void mips1core_device_base::device_start()
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// register our state for the debugger
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state_add(STATE_GENPC, "GENPC", m_pc).noshow();
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state_add(STATE_GENPCBASE, "CURPC", m_ppc).noshow();
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state_add(STATE_GENPCBASE, "CURPC", m_pc).noshow();
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state_add(STATE_GENSP, "GENSP", m_r[31]).noshow();
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state_add(STATE_GENFLAGS, "GENFLAGS", m_cpr[0][COP0_Status]).noshow();
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@ -195,13 +194,13 @@ void mips1core_device_base::device_start()
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// register our state for saving
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save_item(NAME(m_pc));
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save_item(NAME(m_nextpc));
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save_item(NAME(m_hi));
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save_item(NAME(m_lo));
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save_item(NAME(m_r));
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save_item(NAME(m_cpr));
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save_item(NAME(m_ccr));
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save_item(NAME(m_ppc));
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save_item(NAME(m_branch_state));
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save_item(NAME(m_branch_target));
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// initialise cpu and fpu id registers
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m_cpr[0][COP0_PRId] = m_cpurev;
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@ -239,7 +238,7 @@ void mips1core_device_base::device_reset()
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{
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// initialize the state
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m_pc = 0xbfc00000;
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m_nextpc = ~0;
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m_branch_state = NONE;
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// non-tlb devices have tlb shut down
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m_cpr[0][COP0_Status] = SR_BEV | SR_TS;
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@ -274,18 +273,18 @@ std::unique_ptr<util::disasm_interface> mips1core_device_base::create_disassembl
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void mips1core_device_base::generate_exception(int exception)
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{
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// set the exception PC
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m_cpr[0][COP0_EPC] = (exception == EXCEPTION_INTERRUPT) ? m_pc : m_ppc;
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m_cpr[0][COP0_EPC] = m_pc;
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// put the cause in the low 8 bits and clear the branch delay flag
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CAUSE = (CAUSE & ~0x800000ff) | (exception << 2);
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// if we were in a branch delay slot, adjust
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if (m_nextpc != ~0)
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// if in a branch delay slot, restart the branch
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if (m_branch_state == DELAY)
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{
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m_nextpc = ~0;
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m_cpr[0][COP0_EPC] -= 4;
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CAUSE |= 0x80000000;
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}
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m_branch_state = NONE;
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// shift the exception bits
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SR = (SR & 0xffffffc0) | ((SR << 2) & 0x3c);
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@ -552,7 +551,6 @@ void mips1core_device_base::execute_run()
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do
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{
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// debugging
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m_ppc = m_pc;
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debugger_instruction_hook(m_pc);
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#if ENABLE_IOP_KPUTS
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@ -575,16 +573,6 @@ void mips1core_device_base::execute_run()
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// fetch and execute instruction
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fetch(m_pc, [this](u32 const op)
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{
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{
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// adjust for next PC
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if (m_nextpc != ~0)
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{
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m_pc = m_nextpc;
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m_nextpc = ~0;
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}
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else
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m_pc += 4;
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// parse the instruction
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switch (op >> 26)
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{
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@ -784,11 +772,28 @@ void mips1core_device_base::execute_run()
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case 0x3f: /* SDC3 */ generate_exception(EXCEPTION_INVALIDOP); break;
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default: /* ??? */ generate_exception(EXCEPTION_INVALIDOP); break;
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}
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// update pc and branch state
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switch (m_branch_state)
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{
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case NONE:
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m_pc += 4;
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break;
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case DELAY:
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m_branch_state = NONE;
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m_pc = m_branch_target;
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break;
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case BRANCH:
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m_branch_state = DELAY;
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m_pc += 4;
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break;
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}
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});
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m_icount--;
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} while (m_icount > 0 || m_nextpc != ~0);
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} while (m_icount > 0 || m_branch_state);
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}
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void mips1core_device_base::lwl(u32 const op)
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@ -995,7 +1000,8 @@ bool mips1_device_base::memory_translate(int spacenum, int intention, offs_t &ad
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if (!(intention & TRANSLATE_DEBUG_MASK))
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{
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if ((VERBOSE & LOG_TLB) && !dirty)
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LOGMASKED(LOG_TLB, "tlb miss address 0x%08x\n", address);
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LOGMASKED(LOG_TLB, "tlb miss %s address 0x%08x (%s)\n",
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(intention & TRANSLATE_WRITE) ? "store" : "load", address, machine().describe_context());
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// exception
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m_cpr[0][COP0_BadVAddr] = address;
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@ -101,32 +101,32 @@ protected:
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enum sr_mask : u32
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{
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SR_IEc = 0x00000001,
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SR_KUc = 0x00000002,
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SR_IEp = 0x00000004,
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SR_KUp = 0x00000008,
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SR_IEo = 0x00000010,
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SR_KUo = 0x00000020,
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SR_IMSW0 = 0x00000100,
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SR_IMSW1 = 0x00000200,
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SR_IMEX0 = 0x00000400,
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SR_IMEX1 = 0x00000800,
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SR_IMEX2 = 0x00001000,
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SR_IMEX3 = 0x00002000,
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SR_IMEX4 = 0x00004000,
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SR_IMEX5 = 0x00008000,
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SR_IsC = 0x00010000,
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SR_SwC = 0x00020000,
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SR_PZ = 0x00040000,
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SR_CM = 0x00080000,
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SR_PE = 0x00100000,
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SR_TS = 0x00200000,
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SR_BEV = 0x00400000,
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SR_RE = 0x02000000,
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SR_COP0 = 0x10000000,
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SR_COP1 = 0x20000000,
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SR_COP2 = 0x40000000,
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SR_COP3 = 0x80000000,
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SR_IEc = 0x00000001, // interrupt enable
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SR_KUc = 0x00000002, // kernel mode
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SR_IEp = 0x00000004, // interrupt enable (previous)
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SR_KUp = 0x00000008, // kernel mode (previous)
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SR_IEo = 0x00000010, // interrupt enable (old)
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SR_KUo = 0x00000020, // kernel mode (old)
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SR_IMSW0 = 0x00000100, // software interrupt 0 enable
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SR_IMSW1 = 0x00000200, // software interrupt 1 enable
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SR_IMEX0 = 0x00000400, // external interrupt 0 enable
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SR_IMEX1 = 0x00000800, // external interrupt 1 enable
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SR_IMEX2 = 0x00001000, // external interrupt 2 enable
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SR_IMEX3 = 0x00002000, // external interrupt 3 enable
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SR_IMEX4 = 0x00004000, // external interrupt 4 enable
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SR_IMEX5 = 0x00008000, // external interrupt 5 enable
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SR_IsC = 0x00010000, // isolate (data) cache
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SR_SwC = 0x00020000, // swap caches
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SR_PZ = 0x00040000, // cache parity zero
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SR_CM = 0x00080000, // cache match
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SR_PE = 0x00100000, // cache parity error
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SR_TS = 0x00200000, // tlb shutdown
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SR_BEV = 0x00400000, // boot exception vectors
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SR_RE = 0x02000000, // reverse endianness in user mode
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SR_COP0 = 0x10000000, // coprocessor 0 usable
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SR_COP1 = 0x20000000, // coprocessor 1 usable
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SR_COP2 = 0x40000000, // coprocessor 2 usable
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SR_COP3 = 0x80000000, // coprocessor 3 usable
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};
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enum entryhi_mask : u32
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@ -213,7 +213,6 @@ protected:
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// core registers
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u32 m_pc;
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u32 m_nextpc;
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u32 m_hi;
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u32 m_lo;
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u32 m_r[32];
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@ -223,8 +222,15 @@ protected:
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u32 m_ccr[4][32];
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// internal stuff
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u32 m_ppc;
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int m_icount;
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enum branch_state_t : unsigned
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{
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NONE = 0,
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DELAY = 1, // delay slot instruction active
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BRANCH = 2, // branch instruction active
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}
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m_branch_state;
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u32 m_branch_target;
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// cache memory
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size_t const m_icache_size;
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