mirror of
https://github.com/holub/mame
synced 2025-04-19 15:11:37 +03:00
Convert avigo.cpp, mstation.cpp and rex6000.cpp to use bankdev. (nw)
This commit is contained in:
Sandro Ronco
parent
1b243d240f
commit
2e6abeccfa
@ -77,43 +77,6 @@
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#define LOG(x) do { if (AVIGO_LOG) logerror x; } while (0)
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/* memory 0x0000-0x03fff */
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READ8_MEMBER(avigo_state::flash_0x0000_read_handler)
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{
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return m_flashes[0]->read(offset);
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}
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/* memory 0x0000-0x03fff */
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WRITE8_MEMBER(avigo_state::flash_0x0000_write_handler)
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{
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m_flashes[0]->write(offset, data);
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}
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/* memory 0x04000-0x07fff */
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READ8_MEMBER(avigo_state::flash_0x4000_read_handler)
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{
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return m_flashes[m_flash_at_0x4000]->read((m_bank1_l<<14) | offset);
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}
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/* memory 0x04000-0x07fff */
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WRITE8_MEMBER(avigo_state::flash_0x4000_write_handler)
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{
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m_flashes[m_flash_at_0x4000]->write((m_bank1_l<<14) | offset, data);
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}
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/* memory 0x08000-0x0bfff */
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READ8_MEMBER(avigo_state::flash_0x8000_read_handler)
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{
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return m_flashes[m_flash_at_0x8000]->read((m_bank2_l<<14) | offset);
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}
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/* memory 0x08000-0x0bfff */
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WRITE8_MEMBER(avigo_state::flash_0x8000_write_handler)
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{
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m_flashes[m_flash_at_0x8000]->write((m_bank2_l<<14) | offset, data);
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}
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/*
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IRQ bits (port 3) ordered by priority:
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@ -150,58 +113,6 @@ WRITE_LINE_MEMBER( avigo_state::tc8521_alarm_int )
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//#endif
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}
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void avigo_state::refresh_memory(UINT8 bank, UINT8 chip_select)
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{
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address_space& space = m_maincpu->space(AS_PROGRAM);
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int &active_flash = (bank == 1 ? m_flash_at_0x4000 : m_flash_at_0x8000);
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char bank_tag[6];
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LOG(("Chip %02x mapped at %04x - %04x\n", chip_select, bank * 0x4000, bank * 0x4000 + 0x3fff));
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switch (chip_select)
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{
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case 0x06: // videoram
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space.install_readwrite_handler(bank * 0x4000, bank * 0x4000 + 0x3fff, read8_delegate(FUNC(avigo_state::vid_memory_r), this), write8_delegate(FUNC(avigo_state::vid_memory_w), this));
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active_flash = -1;
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break;
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case 0x01: // banked RAM
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sprintf(bank_tag,"bank%d", bank);
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membank(bank_tag)->set_base(m_ram_base + (((bank == 1 ? m_bank1_l : m_bank2_l) & 0x07)<<14));
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space.install_readwrite_bank (bank * 0x4000, bank * 0x4000 + 0x3fff, bank_tag);
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active_flash = -1;
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break;
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case 0x00: // flash 0
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case 0x03: // flash 1
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case 0x05: // flash 2
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case 0x07: // flash 0
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if (active_flash < 0) // to avoid useless calls to install_readwrite_handler that cause slowdowns
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{
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if (bank == 1)
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space.install_readwrite_handler(0x4000, 0x7fff, read8_delegate(FUNC(avigo_state::flash_0x4000_read_handler), this), write8_delegate(FUNC(avigo_state::flash_0x4000_write_handler), this));
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else
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space.install_readwrite_handler(0x8000, 0xbfff, read8_delegate(FUNC(avigo_state::flash_0x8000_read_handler), this), write8_delegate(FUNC(avigo_state::flash_0x8000_write_handler), this));
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}
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switch (chip_select)
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{
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case 0x00:
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case 0x07: active_flash = 0; break;
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case 0x03: active_flash = 1; break;
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case 0x05: active_flash = 2; break;
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}
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break;
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default:
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logerror("Unknown chip %02x mapped at %04x - %04x\n", chip_select, bank * 0x4000, bank * 0x4000 + 0x3fff);
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space.unmap_readwrite(bank * 0x4000, bank * 0x4000 + 0x3fff);
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active_flash = -1;
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break;
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}
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}
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WRITE_LINE_MEMBER( avigo_state::com_interrupt )
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{
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LOG(("com int\r\n"));
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@ -218,38 +129,21 @@ WRITE_LINE_MEMBER( avigo_state::com_interrupt )
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void avigo_state::machine_reset()
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{
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/* if is a cold start initialize flash contents */
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if (!m_warm_start)
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{
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memcpy(m_flashes[0]->space().get_read_ptr(0), memregion("bios")->base() + 0x000000, 0x100000);
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memcpy(m_flashes[1]->space().get_read_ptr(0), memregion("bios")->base() + 0x100000, 0x100000);
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}
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m_irq = 0;
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m_bank1_l = 0;
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m_bank1_h = 0;
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m_bank2_l = 0;
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m_bank2_h = 0;
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m_flash_at_0x4000 = -1;
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m_flash_at_0x8000 = -1;
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refresh_memory(1, m_bank1_h & 0x07);
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refresh_memory(2, m_bank2_h & 0x07);
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m_bankdev1->set_bank(0);
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m_bankdev2->set_bank(0);
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}
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void avigo_state::machine_start()
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{
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m_ram_base = (UINT8*)m_ram->pointer();
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// bank3 always first ram bank
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membank("bank3")->set_base(m_ram_base);
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membank("bank2")->set_base(m_nvram);
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/* keep machine pointers to flash devices */
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m_flashes[0] = machine().device<intelfsh8_device>("flash0");
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m_flashes[1] = machine().device<intelfsh8_device>("flash1");
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m_flashes[2] = machine().device<intelfsh8_device>("flash2");
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machine().device<nvram_device>("nvram")->set_base(m_ram_base, m_ram->size());
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m_warm_start = 1;
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// register for state saving
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@ -261,33 +155,27 @@ void avigo_state::machine_start()
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save_item(NAME(m_bank1_l));
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save_item(NAME(m_bank1_h));
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save_item(NAME(m_ad_control_status));
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save_item(NAME(m_flash_at_0x4000));
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save_item(NAME(m_flash_at_0x8000));
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save_item(NAME(m_ad_value));
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save_item(NAME(m_screen_column));
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save_item(NAME(m_warm_start));
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// save all flash contents
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save_pointer(NAME((UINT8*)m_flashes[0]->space().get_read_ptr(0)), 0x100000);
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save_pointer(NAME((UINT8*)m_flashes[1]->space().get_read_ptr(0)), 0x100000);
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save_pointer(NAME((UINT8*)m_flashes[2]->space().get_read_ptr(0)), 0x100000);
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// register postload callback
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machine().save().register_postload(save_prepost_delegate(FUNC(avigo_state::postload), this));
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}
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void avigo_state::postload()
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{
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// refresh the bankswitch
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refresh_memory(1, m_bank1_h & 0x07);
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refresh_memory(2, m_bank2_h & 0x07);
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}
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static ADDRESS_MAP_START(avigo_banked_map, AS_PROGRAM, 8, avigo_state)
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AM_RANGE(0x0000000, 0x00fffff) AM_MIRROR(0x0300000) AM_DEVREADWRITE("flash0", intelfsh8_device, read, write)
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AM_RANGE(0x0400000, 0x041ffff) AM_MIRROR(0x03e0000) AM_RAM AM_SHARE("nvram")
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AM_RANGE(0x0c00000, 0x0cfffff) AM_MIRROR(0x0300000) AM_DEVREADWRITE("flash1", intelfsh8_device, read, write)
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AM_RANGE(0x1400000, 0x14fffff) AM_MIRROR(0x0300000) AM_DEVREADWRITE("flash2", intelfsh8_device, read, write)
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AM_RANGE(0x1c00000, 0x1cfffff) AM_MIRROR(0x0300000) AM_DEVREADWRITE("flash0", intelfsh8_device, read, write)
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AM_RANGE(0x1800000, 0x1803fff) AM_MIRROR(0x03fc000) AM_READWRITE(vid_memory_r, vid_memory_w)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( avigo_mem , AS_PROGRAM, 8, avigo_state)
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AM_RANGE(0x0000, 0x3fff) AM_READWRITE(flash_0x0000_read_handler, flash_0x0000_write_handler)
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AM_RANGE(0x4000, 0x7fff) AM_READWRITE_BANK("bank1")
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AM_RANGE(0x8000, 0xbfff) AM_READWRITE_BANK("bank2")
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AM_RANGE(0xc000, 0xffff) AM_READWRITE_BANK("bank3")
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AM_RANGE(0x0000, 0x3fff) AM_DEVREADWRITE("flash0", intelfsh8_device, read, write)
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AM_RANGE(0x4000, 0x7fff) AM_DEVREADWRITE("bank0", address_map_bank_device, read8, write8)
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AM_RANGE(0x8000, 0xbfff) AM_DEVREADWRITE("bank1", address_map_bank_device, read8, write8)
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AM_RANGE(0xc000, 0xffff) AM_RAMBANK("bank2")
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ADDRESS_MAP_END
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@ -378,7 +266,7 @@ WRITE8_MEMBER(avigo_state::bank1_w)
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m_bank1_l = data & 0x3f;
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}
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refresh_memory(1, m_bank1_h & 0x07);
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m_bankdev1->set_bank(((m_bank1_h & 0x07) << 8) | m_bank1_l);
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}
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WRITE8_MEMBER(avigo_state::bank2_w)
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@ -394,7 +282,7 @@ WRITE8_MEMBER(avigo_state::bank2_w)
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m_bank2_l = data & 0x3f;
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}
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refresh_memory(2, m_bank2_h & 0x07);
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m_bankdev2->set_bank(((m_bank2_h & 0x07) << 8) | m_bank2_l);
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}
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READ8_MEMBER(avigo_state::ad_control_status_r)
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@ -775,12 +663,12 @@ static const gfx_layout avigo_6_by_8 =
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};
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static GFXDECODE_START( avigo )
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GFXDECODE_ENTRY( "bios", 0x08992, avigo_charlayout, 0, 1 )
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GFXDECODE_ENTRY( "bios", 0x0c020, avigo_8_by_14, 0, 1 )
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GFXDECODE_ENTRY( "bios", 0x0c020, avigo_16_by_15, 0, 1 )
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GFXDECODE_ENTRY( "bios", 0x14020, avigo_15_by_16, 0, 1 )
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GFXDECODE_ENTRY( "bios", 0x1c020, avigo_8_by_8, 0, 1 )
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GFXDECODE_ENTRY( "bios", 0x1e020, avigo_6_by_8, 0, 1 )
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GFXDECODE_ENTRY( "flash0", 0x08992, avigo_charlayout, 0, 1 )
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GFXDECODE_ENTRY( "flash0", 0x0c020, avigo_8_by_14, 0, 1 )
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GFXDECODE_ENTRY( "flash0", 0x0c020, avigo_16_by_15, 0, 1 )
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GFXDECODE_ENTRY( "flash0", 0x14020, avigo_15_by_16, 0, 1 )
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GFXDECODE_ENTRY( "flash0", 0x1c020, avigo_8_by_8, 0, 1 )
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GFXDECODE_ENTRY( "flash0", 0x1e020, avigo_6_by_8, 0, 1 )
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GFXDECODE_END
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@ -800,7 +688,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(avigo_state::avigo_1hz_timer)
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QUICKLOAD_LOAD_MEMBER( avigo_state,avigo)
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{
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address_space& flash1 = m_flashes[1]->space(0);
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address_space& flash1 = m_flash1->space(0);
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const char *systemname = machine().system().name;
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UINT32 first_app_page = (0x50000>>14);
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int app_page;
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@ -833,7 +721,7 @@ QUICKLOAD_LOAD_MEMBER( avigo_state,avigo)
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logerror("Application loaded at 0x%05x-0x%05x\n", app_page<<14, (app_page<<14) + (UINT32)image.length());
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// copy app file into flash memory
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image.fread((UINT8*)m_flashes[1]->space().get_read_ptr(app_page<<14), image.length());
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image.fread((UINT8*)flash1.get_read_ptr(app_page<<14), image.length());
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// update the application ID
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flash1.write_byte((app_page<<14) + 0x1a5, 0x80 + (app_page - (first_app_page>>14)));
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@ -907,6 +795,18 @@ static MACHINE_CONFIG_START( avigo, avigo_state )
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MCFG_RAM_ADD(RAM_TAG)
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MCFG_RAM_DEFAULT_SIZE("128K")
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MCFG_DEVICE_ADD("bank0", ADDRESS_MAP_BANK, 0)
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MCFG_DEVICE_PROGRAM_MAP(avigo_banked_map)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
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MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
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MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
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MCFG_DEVICE_PROGRAM_MAP(avigo_banked_map)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
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MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
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MCFG_NVRAM_ADD_CUSTOM_DRIVER("nvram", avigo_state, nvram_init)
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// IRQ 1 is used for scan the pen and for cursor blinking
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@ -926,87 +826,78 @@ MACHINE_CONFIG_END
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***************************************************************************/
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ROM_START(avigo)
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ROM_REGION(0x200000, "bios", ROMREGION_ERASEFF)
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ROM_REGION(0x100000, "flash0", ROMREGION_ERASEFF)
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ROM_SYSTEM_BIOS( 0, "v1004", "v1.004" )
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ROMX_LOAD("os_1004.rom", 0x000000, 0x0100000, CRC(62acd55c) SHA1(b2be12f5cc1053b6026bff2a265146ba831a7ffa), ROM_BIOS(1))
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ROMX_LOAD("english_1004.rom", 0x100000, 0x050000, CRC(c9c3a225) SHA1(7939993a5615ca59ff2047e69b6d85122d437dca), ROM_BIOS(1))
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ROM_SYSTEM_BIOS( 1, "v1002", "v1.002" )
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ROMX_LOAD("os_1002.rom", 0x000000, 0x0100000, CRC(484bb95c) SHA1(ddc28f22f8cbc99f60f91c58ee0e2d15170024fb), ROM_BIOS(2))
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ROMX_LOAD("english_1002.rom", 0x100000, 0x050000, CRC(31cab0ac) SHA1(87d337830506a12514a4beb9a8502a0de94816f2), ROM_BIOS(2))
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ROM_SYSTEM_BIOS( 2, "v100", "v1.00" )
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ROMX_LOAD("os_100.rom", 0x000000, 0x0100000, CRC(13ea7b38) SHA1(85566ff142d86d504ac72613f169d8758e2daa09), ROM_BIOS(3))
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ROMX_LOAD("english_100.rom", 0x100000, 0x050000, CRC(e2824b44) SHA1(3252454b05c3d3a4d7df1cb48dc3441ae82f2b1c), ROM_BIOS(3))
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ROM_REGION(0x100000, "flash1", ROMREGION_ERASEFF)
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ROMX_LOAD("english_1004.rom", 0x000000, 0x050000, CRC(c9c3a225) SHA1(7939993a5615ca59ff2047e69b6d85122d437dca), ROM_BIOS(1))
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ROMX_LOAD("english_1002.rom", 0x000000, 0x050000, CRC(31cab0ac) SHA1(87d337830506a12514a4beb9a8502a0de94816f2), ROM_BIOS(2))
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ROMX_LOAD("english_100.rom", 0x000000, 0x050000, CRC(e2824b44) SHA1(3252454b05c3d3a4d7df1cb48dc3441ae82f2b1c), ROM_BIOS(3))
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ROM_END
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ROM_START(avigo_de)
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ROM_REGION(0x200000, "bios", ROMREGION_ERASEFF)
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ROM_REGION(0x100000, "flash0", ROMREGION_ERASEFF)
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ROM_SYSTEM_BIOS( 0, "v1004", "v1.004" )
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ROMX_LOAD("os_1004.rom", 0x000000, 0x0100000, CRC(62acd55c) SHA1(b2be12f5cc1053b6026bff2a265146ba831a7ffa), ROM_BIOS(1))
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ROMX_LOAD("german_1004.rom", 0x100000, 0x060000, CRC(0fa437b3) SHA1(e9352aa8fee6d93b898412bd129452b82baa9a21), ROM_BIOS(1))
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ROM_SYSTEM_BIOS( 1, "v1002", "v1.002" )
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ROMX_LOAD("os_1002.rom", 0x000000, 0x0100000, CRC(484bb95c) SHA1(ddc28f22f8cbc99f60f91c58ee0e2d15170024fb), ROM_BIOS(2))
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ROMX_LOAD("german_1002.rom", 0x100000, 0x060000, CRC(c6bf07ba) SHA1(d3185687aa510f6c3b3ab3baaabe7e8ce1a79e3b), ROM_BIOS(2))
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ROM_SYSTEM_BIOS( 2, "v100", "v1.00" )
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ROMX_LOAD("os_100.rom", 0x000000, 0x0100000, CRC(13ea7b38) SHA1(85566ff142d86d504ac72613f169d8758e2daa09), ROM_BIOS(3))
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ROMX_LOAD("german_100.rom", 0x100000, 0x060000, CRC(117d9189) SHA1(7e959ab1381ba831821fcf87973b25d87f12d34e), ROM_BIOS(3))
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ROM_REGION(0x100000, "flash1", ROMREGION_ERASEFF)
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ROMX_LOAD("german_1004.rom", 0x000000, 0x060000, CRC(0fa437b3) SHA1(e9352aa8fee6d93b898412bd129452b82baa9a21), ROM_BIOS(1))
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ROMX_LOAD("german_1002.rom", 0x000000, 0x060000, CRC(c6bf07ba) SHA1(d3185687aa510f6c3b3ab3baaabe7e8ce1a79e3b), ROM_BIOS(2))
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ROMX_LOAD("german_100.rom", 0x000000, 0x060000, CRC(117d9189) SHA1(7e959ab1381ba831821fcf87973b25d87f12d34e), ROM_BIOS(3))
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ROM_END
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ROM_START(avigo_fr)
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ROM_REGION(0x200000, "bios", ROMREGION_ERASEFF)
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ROM_REGION(0x100000, "flash0", ROMREGION_ERASEFF)
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ROM_SYSTEM_BIOS( 0, "v1004", "v1.004" )
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ROMX_LOAD("os_1004.rom", 0x000000, 0x0100000, CRC(62acd55c) SHA1(b2be12f5cc1053b6026bff2a265146ba831a7ffa), ROM_BIOS(1))
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ROMX_LOAD("french_1004.rom", 0x100000, 0x050000, CRC(5e4d90f7) SHA1(07df3af8a431ba65e079d6c987fb5d544f6541d8), ROM_BIOS(1))
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ROM_SYSTEM_BIOS( 1, "v1002", "v1.002" )
|
||||
ROMX_LOAD("os_1002.rom", 0x000000, 0x0100000, CRC(484bb95c) SHA1(ddc28f22f8cbc99f60f91c58ee0e2d15170024fb), ROM_BIOS(2))
|
||||
ROMX_LOAD("french_1002.rom", 0x100000, 0x050000,CRC(caa3eb91) SHA1(ab199986de301d933f069a5e1f5150967e1d7f59), ROM_BIOS(2))
|
||||
|
||||
ROM_SYSTEM_BIOS( 2, "v100", "v1.00" )
|
||||
ROMX_LOAD("os_100.rom", 0x000000, 0x0100000, CRC(13ea7b38) SHA1(85566ff142d86d504ac72613f169d8758e2daa09), ROM_BIOS(3))
|
||||
ROMX_LOAD("french_100.rom", 0x100000, 0x050000, CRC(fffa2345) SHA1(399447cede3cdd0be768952cb24f7e4431147e3d), ROM_BIOS(3))
|
||||
|
||||
ROM_REGION(0x100000, "flash1", ROMREGION_ERASEFF)
|
||||
ROMX_LOAD("french_1004.rom", 0x000000, 0x050000, CRC(5e4d90f7) SHA1(07df3af8a431ba65e079d6c987fb5d544f6541d8), ROM_BIOS(1))
|
||||
ROMX_LOAD("french_1002.rom", 0x000000, 0x050000,CRC(caa3eb91) SHA1(ab199986de301d933f069a5e1f5150967e1d7f59), ROM_BIOS(2))
|
||||
ROMX_LOAD("french_100.rom", 0x000000, 0x050000, CRC(fffa2345) SHA1(399447cede3cdd0be768952cb24f7e4431147e3d), ROM_BIOS(3))
|
||||
ROM_END
|
||||
|
||||
ROM_START(avigo_es)
|
||||
ROM_REGION(0x200000, "bios", ROMREGION_ERASEFF)
|
||||
|
||||
ROM_REGION(0x100000, "flash0", ROMREGION_ERASEFF)
|
||||
ROM_SYSTEM_BIOS( 0, "v1004", "v1.004" )
|
||||
ROMX_LOAD("os_1004.rom", 0x000000, 0x0100000, CRC(62acd55c) SHA1(b2be12f5cc1053b6026bff2a265146ba831a7ffa), ROM_BIOS(1))
|
||||
ROMX_LOAD("spanish_1004.rom", 0x100000, 0x060000, CRC(235a7f8d) SHA1(94da4ecafb54dcd5d80bc5063cb4024e66e6a21f), ROM_BIOS(1))
|
||||
|
||||
ROM_SYSTEM_BIOS( 1, "v1002", "v1.002" )
|
||||
ROMX_LOAD("os_1002.rom", 0x000000, 0x0100000, CRC(484bb95c) SHA1(ddc28f22f8cbc99f60f91c58ee0e2d15170024fb), ROM_BIOS(2))
|
||||
ROMX_LOAD("spanish_1002.rom", 0x100000, 0x060000, CRC(a6e80cc4) SHA1(e741657558c11f7bce646ba3d7b5f845bfa275b7), ROM_BIOS(2))
|
||||
|
||||
ROM_SYSTEM_BIOS( 2, "v100", "v1.00" )
|
||||
ROMX_LOAD("os_100.rom", 0x000000, 0x0100000, CRC(13ea7b38) SHA1(85566ff142d86d504ac72613f169d8758e2daa09), ROM_BIOS(3))
|
||||
ROMX_LOAD("spanish_100.rom", 0x100000, 0x060000, CRC(953a5276) SHA1(b9ba1dbdc2127b1ef419c911ef66313024a7351a), ROM_BIOS(3))
|
||||
|
||||
ROM_REGION(0x100000, "flash1", ROMREGION_ERASEFF)
|
||||
ROMX_LOAD("spanish_1004.rom", 0x000000, 0x060000, CRC(235a7f8d) SHA1(94da4ecafb54dcd5d80bc5063cb4024e66e6a21f), ROM_BIOS(1))
|
||||
ROMX_LOAD("spanish_1002.rom", 0x000000, 0x060000, CRC(a6e80cc4) SHA1(e741657558c11f7bce646ba3d7b5f845bfa275b7), ROM_BIOS(2))
|
||||
ROMX_LOAD("spanish_100.rom", 0x000000, 0x060000, CRC(953a5276) SHA1(b9ba1dbdc2127b1ef419c911ef66313024a7351a), ROM_BIOS(3))
|
||||
ROM_END
|
||||
|
||||
ROM_START(avigo_it)
|
||||
ROM_REGION(0x200000, "bios", ROMREGION_ERASEFF)
|
||||
|
||||
ROM_REGION(0x100000, "flash0", ROMREGION_ERASEFF)
|
||||
ROM_SYSTEM_BIOS( 0, "v1004", "v1.004" )
|
||||
ROMX_LOAD("os_1004.rom", 0x000000, 0x0100000, CRC(62acd55c) SHA1(b2be12f5cc1053b6026bff2a265146ba831a7ffa), ROM_BIOS(1))
|
||||
ROMX_LOAD("italian_1004.rom", 0x100000, 0x050000, CRC(fb7941ec) SHA1(230e8346a3b0da1ee24568ec090ce6860ebfe995), ROM_BIOS(1))
|
||||
|
||||
ROM_SYSTEM_BIOS( 1, "v1002", "v1.002" )
|
||||
ROMX_LOAD("os_1002.rom", 0x000000, 0x0100000, CRC(484bb95c) SHA1(ddc28f22f8cbc99f60f91c58ee0e2d15170024fb), ROM_BIOS(2))
|
||||
ROMX_LOAD("italian_1002.rom", 0x100000, 0x050000, CRC(093bc032) SHA1(2c75d950d356a7fd1d058808e5f0be8e15b8ea2a), ROM_BIOS(2))
|
||||
|
||||
ROM_SYSTEM_BIOS( 2, "v100", "v1.00" )
|
||||
ROMX_LOAD("os_100.rom", 0x000000, 0x0100000, CRC(13ea7b38) SHA1(85566ff142d86d504ac72613f169d8758e2daa09), ROM_BIOS(3))
|
||||
ROMX_LOAD("italian_100.rom", 0x100000, 0x050000, CRC(de359218) SHA1(6185727aba8ffc98723f2df74dda388fd0d70cc9), ROM_BIOS(3))
|
||||
|
||||
ROM_REGION(0x100000, "flash1", ROMREGION_ERASEFF)
|
||||
ROMX_LOAD("italian_1004.rom", 0x000000, 0x050000, CRC(fb7941ec) SHA1(230e8346a3b0da1ee24568ec090ce6860ebfe995), ROM_BIOS(1))
|
||||
ROMX_LOAD("italian_1002.rom", 0x000000, 0x050000, CRC(093bc032) SHA1(2c75d950d356a7fd1d058808e5f0be8e15b8ea2a), ROM_BIOS(2))
|
||||
ROMX_LOAD("italian_100.rom", 0x000000, 0x050000, CRC(de359218) SHA1(6185727aba8ffc98723f2df74dda388fd0d70cc9), ROM_BIOS(3))
|
||||
ROM_END
|
||||
|
||||
/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME */
|
||||
|
||||
@ -28,6 +28,7 @@
|
||||
|
||||
#include "emu.h"
|
||||
#include "cpu/z80/z80.h"
|
||||
#include "machine/bankdev.h"
|
||||
#include "machine/intelfsh.h"
|
||||
#include "machine/rp5c01.h"
|
||||
#include "machine/ram.h"
|
||||
@ -39,30 +40,28 @@ public:
|
||||
mstation_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: driver_device(mconfig, type, tag),
|
||||
m_maincpu(*this, "maincpu"),
|
||||
m_ram(*this, RAM_TAG)
|
||||
m_ram(*this, RAM_TAG),
|
||||
m_bankdev1(*this, "bank0"),
|
||||
m_bankdev2(*this, "bank1"),
|
||||
m_keyboard(*this, "LINE"),
|
||||
m_nvram(*this, "nvram")
|
||||
{ }
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<ram_device> m_ram;
|
||||
required_device<address_map_bank_device> m_bankdev1;
|
||||
required_device<address_map_bank_device> m_bankdev2;
|
||||
required_ioport_array<10> m_keyboard;
|
||||
required_shared_ptr<UINT8> m_nvram;
|
||||
|
||||
intelfsh8_device *m_flashes[2];
|
||||
UINT8 m_bank1[2];
|
||||
UINT8 m_bank2[2];
|
||||
UINT8 *m_ram_base;
|
||||
int m_flash_at_0x4000;
|
||||
int m_flash_at_0x8000;
|
||||
UINT8 *m_vram;
|
||||
UINT8 m_screen_column;
|
||||
UINT8 m_port2;
|
||||
UINT8 m_irq;
|
||||
UINT16 m_kb_matrix;
|
||||
|
||||
DECLARE_READ8_MEMBER( flash_0x0000_read_handler );
|
||||
DECLARE_WRITE8_MEMBER( flash_0x0000_write_handler );
|
||||
DECLARE_READ8_MEMBER( flash_0x4000_read_handler );
|
||||
DECLARE_WRITE8_MEMBER( flash_0x4000_write_handler );
|
||||
DECLARE_READ8_MEMBER( flash_0x8000_read_handler );
|
||||
DECLARE_WRITE8_MEMBER( flash_0x8000_write_handler );
|
||||
DECLARE_READ8_MEMBER( modem_r );
|
||||
DECLARE_WRITE8_MEMBER( modem_w );
|
||||
|
||||
@ -73,7 +72,6 @@ public:
|
||||
DECLARE_READ8_MEMBER( lcd_left_r );
|
||||
DECLARE_WRITE8_MEMBER( lcd_left_w );
|
||||
|
||||
void refresh_memory(UINT8 bank, UINT8 chip_select);
|
||||
DECLARE_READ8_MEMBER( bank1_r );
|
||||
DECLARE_WRITE8_MEMBER( bank1_w );
|
||||
DECLARE_READ8_MEMBER( bank2_r );
|
||||
@ -97,35 +95,6 @@ public:
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(mstation_kb_timer);
|
||||
};
|
||||
|
||||
READ8_MEMBER( mstation_state::flash_0x0000_read_handler )
|
||||
{
|
||||
return m_flashes[0]->read(offset);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( mstation_state::flash_0x0000_write_handler )
|
||||
{
|
||||
m_flashes[0]->write(offset, data);
|
||||
}
|
||||
|
||||
READ8_MEMBER( mstation_state::flash_0x4000_read_handler )
|
||||
{
|
||||
return m_flashes[m_flash_at_0x4000]->read(((m_bank1[0] & 0x3f)<<14) | offset);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( mstation_state::flash_0x4000_write_handler )
|
||||
{
|
||||
m_flashes[m_flash_at_0x4000]->write(((m_bank1[0] & 0x3f)<<14) | offset, data);
|
||||
}
|
||||
|
||||
READ8_MEMBER( mstation_state::flash_0x8000_read_handler )
|
||||
{
|
||||
return m_flashes[m_flash_at_0x8000]->read(((m_bank2[0] & 0x3f)<<14) | offset);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( mstation_state::flash_0x8000_write_handler )
|
||||
{
|
||||
m_flashes[m_flash_at_0x8000]->write(((m_bank2[0] & 0x3f)<<14) | offset, data);
|
||||
}
|
||||
|
||||
READ8_MEMBER( mstation_state::modem_r )
|
||||
{
|
||||
@ -185,53 +154,6 @@ UINT32 mstation_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap
|
||||
// Bankswitch
|
||||
//***************************************************************************/
|
||||
|
||||
void mstation_state::refresh_memory(UINT8 bank, UINT8 chip_select)
|
||||
{
|
||||
address_space& program = m_maincpu->space(AS_PROGRAM);
|
||||
int &active_flash = (bank == 1 ? m_flash_at_0x4000 : m_flash_at_0x8000);
|
||||
char bank_tag[6];
|
||||
|
||||
switch (chip_select)
|
||||
{
|
||||
case 0: // flash 0
|
||||
case 3: // flash 1
|
||||
if (active_flash < 0)
|
||||
{
|
||||
if (bank == 1)
|
||||
program.install_readwrite_handler(0x4000, 0x7fff, 0, 0, read8_delegate(FUNC(mstation_state::flash_0x4000_read_handler), this), write8_delegate(FUNC(mstation_state::flash_0x4000_write_handler), this));
|
||||
else
|
||||
program.install_readwrite_handler(0x8000, 0xbfff, 0, 0, read8_delegate(FUNC(mstation_state::flash_0x8000_read_handler), this), write8_delegate(FUNC(mstation_state::flash_0x8000_write_handler), this));
|
||||
}
|
||||
|
||||
active_flash = chip_select ? 1 : 0;
|
||||
break;
|
||||
case 1: // banked RAM
|
||||
sprintf(bank_tag,"bank%d", bank);
|
||||
membank(bank_tag)->set_base(m_ram_base + (((bank == 1 ? m_bank1[0] : m_bank2[0]) & 0x07)<<14));
|
||||
program.install_readwrite_bank (bank * 0x4000, bank * 0x4000 + 0x3fff, bank_tag);
|
||||
active_flash = -1;
|
||||
break;
|
||||
case 2: // left LCD panel
|
||||
program.install_readwrite_handler(bank * 0x4000, bank * 0x4000 + 0x3fff, 0, 0, read8_delegate(FUNC(mstation_state::lcd_left_r), this), write8_delegate(FUNC(mstation_state::lcd_left_w), this));
|
||||
active_flash = -1;
|
||||
break;
|
||||
case 4: // right LCD panel
|
||||
program.install_readwrite_handler(bank * 0x4000, bank * 0x4000 + 0x3fff, 0, 0, read8_delegate(FUNC(mstation_state::lcd_right_r), this), write8_delegate(FUNC(mstation_state::lcd_right_w), this));
|
||||
active_flash = -1;
|
||||
break;
|
||||
case 5: // modem
|
||||
program.install_readwrite_handler(bank * 0x4000, bank * 0x4000 + 0x3fff, 0x07, 0, read8_delegate(FUNC(mstation_state::modem_r), this), write8_delegate(FUNC(mstation_state::modem_w), this));
|
||||
active_flash = -1;
|
||||
break;
|
||||
|
||||
default:
|
||||
logerror("Unknown chip %02x mapped at %04x - %04x\n", chip_select, bank * 0x4000, bank * 0x4000 + 0x3fff);
|
||||
program.unmap_readwrite(bank * 0x4000, bank * 0x4000 + 0x3fff);
|
||||
active_flash = -1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER( mstation_state::bank1_r )
|
||||
{
|
||||
return m_bank1[offset];
|
||||
@ -246,14 +168,14 @@ WRITE8_MEMBER( mstation_state::bank1_w )
|
||||
{
|
||||
m_bank1[offset] = data;
|
||||
|
||||
refresh_memory(1, m_bank1[1] & 0x07);
|
||||
m_bankdev1->set_bank(((m_bank1[1] & 0x07) << 8) | m_bank1[0]);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( mstation_state::bank2_w )
|
||||
{
|
||||
m_bank2[offset] = data;
|
||||
|
||||
refresh_memory(2, m_bank2[1] & 0x07);
|
||||
m_bankdev2->set_bank(((m_bank2[1] & 0x07) << 8) | m_bank2[0]);
|
||||
}
|
||||
|
||||
|
||||
@ -314,25 +236,32 @@ WRITE8_MEMBER( mstation_state::kb_w )
|
||||
|
||||
READ8_MEMBER( mstation_state::kb_r )
|
||||
{
|
||||
static const char *const bitnames[] = { "LINE0", "LINE1", "LINE2", "LINE3", "LINE4",
|
||||
"LINE5", "LINE6", "LINE7", "LINE8", "LINE9" };
|
||||
UINT8 data = 0xff;
|
||||
|
||||
for (int i=0; i<10; i++)
|
||||
{
|
||||
if (!(m_kb_matrix & (1<<i)))
|
||||
data &= ioport(bitnames[i])->read();
|
||||
data &= m_keyboard[i]->read();
|
||||
}
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
|
||||
static ADDRESS_MAP_START(mstation_banked_map, AS_PROGRAM, 8, mstation_state)
|
||||
AM_RANGE(0x0000000, 0x00fffff) AM_MIRROR(0x0300000) AM_DEVREADWRITE("flash0", intelfsh8_device, read, write)
|
||||
AM_RANGE(0x0400000, 0x041ffff) AM_MIRROR(0x03e0000) AM_RAM AM_SHARE("nvram")
|
||||
AM_RANGE(0x0c00000, 0x0c7ffff) AM_MIRROR(0x0380000) AM_DEVREADWRITE("flash1", intelfsh8_device, read, write)
|
||||
AM_RANGE(0x0800000, 0x0803fff) AM_MIRROR(0x03fc000) AM_READWRITE(lcd_left_r, lcd_left_w)
|
||||
AM_RANGE(0x1000000, 0x1003fff) AM_MIRROR(0x03fc000) AM_READWRITE(lcd_right_r, lcd_right_w)
|
||||
AM_RANGE(0x1400000, 0x1403fff) AM_MIRROR(0x03fc000) AM_READWRITE(modem_r, modem_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START(mstation_mem, AS_PROGRAM, 8, mstation_state)
|
||||
AM_RANGE(0x0000, 0x3fff) AM_READWRITE(flash_0x0000_read_handler, flash_0x0000_write_handler)
|
||||
AM_RANGE(0x4000, 0x7fff) AM_READWRITE_BANK("bank1") // bank 1
|
||||
AM_RANGE(0x8000, 0xbfff) AM_READWRITE_BANK("bank2") // bank 2
|
||||
AM_RANGE(0xc000, 0xffff) AM_READWRITE_BANK("sysram") // system ram always first RAM bank
|
||||
AM_RANGE(0x0000, 0x3fff) AM_DEVREADWRITE("flash0", intelfsh8_device, read, write)
|
||||
AM_RANGE(0x4000, 0x7fff) AM_DEVREADWRITE("bank0", address_map_bank_device, read8, write8)
|
||||
AM_RANGE(0x8000, 0xbfff) AM_DEVREADWRITE("bank1", address_map_bank_device, read8, write8)
|
||||
AM_RANGE(0xc000, 0xffff) AM_RAMBANK("sysram") // system ram always first RAM bank
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START(mstation_io , AS_IO, 8, mstation_state)
|
||||
@ -350,7 +279,7 @@ ADDRESS_MAP_END
|
||||
|
||||
/* Input ports */
|
||||
static INPUT_PORTS_START( mstation )
|
||||
PORT_START( "LINE0" )
|
||||
PORT_START( "LINE.0" )
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Main Menu") PORT_CODE( KEYCODE_HOME ) PORT_CHAR(UCHAR_MAMEKEY(HOME))
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Back") PORT_CODE( KEYCODE_DEL ) PORT_CHAR(UCHAR_MAMEKEY(END))
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Print") PORT_CODE( KEYCODE_F6 )
|
||||
@ -360,7 +289,7 @@ static INPUT_PORTS_START( mstation )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F4") PORT_CODE( KEYCODE_F4 ) PORT_CHAR(UCHAR_MAMEKEY(F4))
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("F5") PORT_CODE( KEYCODE_F5 ) PORT_CHAR(UCHAR_MAMEKEY(F5))
|
||||
|
||||
PORT_START( "LINE1" )
|
||||
PORT_START( "LINE.1" )
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
@ -370,7 +299,7 @@ static INPUT_PORTS_START( mstation )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Get E-Mail") PORT_CODE( KEYCODE_F9 )
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("PG Up") PORT_CODE( KEYCODE_PGUP ) PORT_CHAR(UCHAR_MAMEKEY(PGUP))
|
||||
|
||||
PORT_START( "LINE2" )
|
||||
PORT_START( "LINE.2" )
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("\xc2\xb4") PORT_CODE( KEYCODE_0_PAD )
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_1 ) PORT_CHAR('1') PORT_CHAR('!')
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_2 ) PORT_CHAR('2') PORT_CHAR('@')
|
||||
@ -380,7 +309,7 @@ static INPUT_PORTS_START( mstation )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_6 ) PORT_CHAR('6') PORT_CHAR('^')
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_7 ) PORT_CHAR('7') PORT_CHAR('&')
|
||||
|
||||
PORT_START( "LINE3" )
|
||||
PORT_START( "LINE.3" )
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_8 ) PORT_CHAR('8') PORT_CHAR('*')
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_9 ) PORT_CHAR('9') PORT_CHAR('(')
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_0 ) PORT_CHAR('0') PORT_CHAR(')')
|
||||
@ -390,7 +319,7 @@ static INPUT_PORTS_START( mstation )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_BACKSLASH ) PORT_CHAR('\\') PORT_CHAR('|')
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("PG Down") PORT_CODE( KEYCODE_PGDN ) PORT_CHAR(UCHAR_MAMEKEY(PGDN))
|
||||
|
||||
PORT_START( "LINE4" )
|
||||
PORT_START( "LINE.4" )
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Tab") PORT_CODE( KEYCODE_TAB ) PORT_CHAR(9)
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_Q ) PORT_CHAR('q') PORT_CHAR('Q')
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_W ) PORT_CHAR('w') PORT_CHAR('W')
|
||||
@ -400,7 +329,7 @@ static INPUT_PORTS_START( mstation )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_Y ) PORT_CHAR('y') PORT_CHAR('Y')
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_U ) PORT_CHAR('u') PORT_CHAR('U')
|
||||
|
||||
PORT_START( "LINE5" )
|
||||
PORT_START( "LINE.5" )
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_I ) PORT_CHAR('i') PORT_CHAR('I')
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_O ) PORT_CHAR('o') PORT_CHAR('O')
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_P ) PORT_CHAR('p') PORT_CHAR('P')
|
||||
@ -410,7 +339,7 @@ static INPUT_PORTS_START( mstation )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_QUOTE ) PORT_CHAR('\'') PORT_CHAR('\"')
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Enter") PORT_CODE( KEYCODE_ENTER ) PORT_CHAR(UCHAR_MAMEKEY(ENTER))
|
||||
|
||||
PORT_START( "LINE6" )
|
||||
PORT_START( "LINE.6" )
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("CapsLock") PORT_CODE( KEYCODE_CAPSLOCK ) PORT_CHAR(UCHAR_MAMEKEY(CAPSLOCK))
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_A ) PORT_CHAR('a') PORT_CHAR('A')
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_S ) PORT_CHAR('s') PORT_CHAR('S')
|
||||
@ -420,7 +349,7 @@ static INPUT_PORTS_START( mstation )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_H ) PORT_CHAR('h') PORT_CHAR('H')
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_J ) PORT_CHAR('j') PORT_CHAR('J')
|
||||
|
||||
PORT_START( "LINE7" )
|
||||
PORT_START( "LINE.7" )
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_K ) PORT_CHAR('K') PORT_CHAR('K')
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_L ) PORT_CHAR('l') PORT_CHAR('L')
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_COMMA ) PORT_CHAR(',') PORT_CHAR('<')
|
||||
@ -430,7 +359,7 @@ static INPUT_PORTS_START( mstation )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Down") PORT_CODE( KEYCODE_DOWN ) PORT_CHAR(UCHAR_MAMEKEY(DOWN))
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Right") PORT_CODE( KEYCODE_RIGHT ) PORT_CHAR(UCHAR_MAMEKEY(RIGHT))
|
||||
|
||||
PORT_START( "LINE8" )
|
||||
PORT_START( "LINE.8" )
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Left Shift") PORT_CODE( KEYCODE_LSHIFT ) PORT_CHAR(UCHAR_MAMEKEY(LSHIFT))
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_Z ) PORT_CHAR('z') PORT_CHAR('Z')
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_X ) PORT_CHAR('x') PORT_CHAR('X')
|
||||
@ -440,7 +369,7 @@ static INPUT_PORTS_START( mstation )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_N ) PORT_CHAR('n') PORT_CHAR('N')
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_CODE( KEYCODE_M ) PORT_CHAR('m') PORT_CHAR('M')
|
||||
|
||||
PORT_START( "LINE9" )
|
||||
PORT_START( "LINE.9" )
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_KEYBOARD ) PORT_NAME("Function") PORT_CODE( KEYCODE_LCONTROL ) PORT_CHAR(UCHAR_MAMEKEY(LCONTROL))
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
@ -453,29 +382,23 @@ INPUT_PORTS_END
|
||||
|
||||
void mstation_state::machine_start()
|
||||
{
|
||||
m_flashes[0] = machine().device<intelfsh8_device>("flash0");
|
||||
m_flashes[1] = machine().device<intelfsh8_device>("flash1");
|
||||
|
||||
// allocate the videoram
|
||||
m_vram = (UINT8*)machine().memory().region_alloc( "vram", 9600, 1, ENDIANNESS_LITTLE )->base();
|
||||
m_ram_base = (UINT8*)m_ram->pointer();
|
||||
|
||||
// map firsh RAM bank at 0xc000-0xffff
|
||||
membank("sysram")->set_base(m_ram_base);
|
||||
membank("sysram")->set_base(m_nvram);
|
||||
}
|
||||
|
||||
|
||||
void mstation_state::machine_reset()
|
||||
{
|
||||
m_flash_at_0x4000 = 0;
|
||||
m_flash_at_0x8000 = 0;
|
||||
m_bank1[0] = m_bank1[1] = 0;
|
||||
m_bank2[0] = m_bank2[1] = 0;
|
||||
memset(m_vram, 0, 9600);
|
||||
|
||||
// reset banks
|
||||
refresh_memory(1, m_bank1[1]);
|
||||
refresh_memory(2, m_bank2[1]);
|
||||
m_bankdev1->set_bank(0);
|
||||
m_bankdev2->set_bank(0);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER( mstation_state::rtc_irq )
|
||||
@ -540,6 +463,18 @@ static MACHINE_CONFIG_START( mstation, mstation_state )
|
||||
MCFG_DEVICE_ADD("rtc", RP5C01, XTAL_32_768kHz)
|
||||
MCFG_RP5C01_OUT_ALARM_CB(WRITELINE(mstation_state, rtc_irq))
|
||||
|
||||
MCFG_DEVICE_ADD("bank0", ADDRESS_MAP_BANK, 0)
|
||||
MCFG_DEVICE_PROGRAM_MAP(mstation_banked_map)
|
||||
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
|
||||
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
|
||||
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
|
||||
|
||||
MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
|
||||
MCFG_DEVICE_PROGRAM_MAP(mstation_banked_map)
|
||||
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
|
||||
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
|
||||
MCFG_ADDRESS_MAP_BANK_STRIDE(0x4000)
|
||||
|
||||
/* internal ram */
|
||||
MCFG_RAM_ADD(RAM_TAG)
|
||||
MCFG_RAM_DEFAULT_SIZE("128K")
|
||||
|
||||
@ -29,6 +29,7 @@
|
||||
#include "emu.h"
|
||||
#include "cpu/z80/z80.h"
|
||||
#include "machine/rp5c01.h"
|
||||
#include "machine/bankdev.h"
|
||||
#include "machine/ram.h"
|
||||
#include "machine/intelfsh.h"
|
||||
#include "imagedev/snapquik.h"
|
||||
@ -46,14 +47,6 @@
|
||||
#define IRQ_FLAG_IRQ1 0x40
|
||||
#define IRQ_FLAG_EVENT 0x80
|
||||
|
||||
//memory bank types
|
||||
#define BANK_FLASH0_B0 0x00
|
||||
#define BANK_FLASH0_B1 0x01
|
||||
#define BANK_FLASH1_B0 0x02
|
||||
#define BANK_FLASH1_B1 0x03
|
||||
#define BANK_RAM 0x10
|
||||
#define BANK_UNKNOWN 0xff
|
||||
|
||||
#define TC8521_TAG "rtc"
|
||||
|
||||
class rex6000_state : public driver_device
|
||||
@ -63,13 +56,20 @@ public:
|
||||
: driver_device(mconfig, type, tag),
|
||||
m_maincpu(*this, "maincpu"),
|
||||
m_ram(*this, RAM_TAG),
|
||||
m_beep(*this, "beeper")
|
||||
m_beep(*this, "beeper"),
|
||||
m_bankdev0(*this, "bank0"),
|
||||
m_bankdev1(*this, "bank1"),
|
||||
m_flash0b(*this, "flash0b"),
|
||||
m_nvram(*this, "nvram")
|
||||
{ }
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<ram_device> m_ram;
|
||||
required_device<beep_device> m_beep;
|
||||
fujitsu_29dl16x_device *m_flash[4];
|
||||
required_device<address_map_bank_device> m_bankdev0;
|
||||
required_device<address_map_bank_device> m_bankdev1;
|
||||
optional_device<intelfsh8_device> m_flash0b;
|
||||
required_shared_ptr<UINT8> m_nvram;
|
||||
|
||||
UINT8 m_bank[4];
|
||||
UINT8 m_beep_io[5];
|
||||
@ -77,19 +77,12 @@ public:
|
||||
UINT8 m_touchscreen[0x10];
|
||||
UINT8 m_lcd_enabled;
|
||||
UINT8 m_lcd_cmd;
|
||||
UINT8 *m_ram_base;
|
||||
|
||||
UINT8 m_irq_mask;
|
||||
UINT8 m_irq_flag;
|
||||
UINT8 m_port6;
|
||||
UINT8 m_beep_mode;
|
||||
|
||||
struct
|
||||
{
|
||||
UINT8 type;
|
||||
UINT16 page;
|
||||
} m_banks[2];
|
||||
|
||||
virtual void machine_start() override;
|
||||
virtual void machine_reset() override;
|
||||
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
|
||||
@ -108,14 +101,6 @@ public:
|
||||
DECLARE_WRITE8_MEMBER( touchscreen_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( alarm_irq );
|
||||
|
||||
DECLARE_READ8_MEMBER( flash_0x0000_r );
|
||||
DECLARE_WRITE8_MEMBER( flash_0x0000_w );
|
||||
DECLARE_READ8_MEMBER( flash_0x8000_r );
|
||||
DECLARE_WRITE8_MEMBER( flash_0x8000_w );
|
||||
DECLARE_READ8_MEMBER( flash_0xa000_r );
|
||||
DECLARE_WRITE8_MEMBER( flash_0xa000_w );
|
||||
|
||||
UINT8 identify_bank_type(UINT32 bank);
|
||||
DECLARE_PALETTE_INIT(rex6000);
|
||||
DECLARE_INPUT_CHANGED_MEMBER(trigger_irq);
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(irq_timer1);
|
||||
@ -125,34 +110,6 @@ public:
|
||||
};
|
||||
|
||||
|
||||
UINT8 rex6000_state::identify_bank_type(UINT32 bank)
|
||||
{
|
||||
if (bank < 0x080)
|
||||
{
|
||||
return BANK_FLASH0_B0;
|
||||
}
|
||||
else if (bank >= 0x080 && bank < 0x100)
|
||||
{
|
||||
return BANK_FLASH0_B1;
|
||||
}
|
||||
else if ((bank >= 0xb00 && bank < 0xb80) || (bank >= 0x600 && bank < 0x680))
|
||||
{
|
||||
return BANK_FLASH1_B0;
|
||||
}
|
||||
else if ((bank >= 0xb80 && bank < 0xc00) || (bank >= 0x680 && bank < 0x700))
|
||||
{
|
||||
return BANK_FLASH1_B1;
|
||||
}
|
||||
else if (bank >= 0x1000 && bank < 0x1004)
|
||||
{
|
||||
return BANK_RAM;
|
||||
}
|
||||
else
|
||||
{
|
||||
//logerror("%04x: unkonwn memory bank %x\n", m_maincpu->pc(), bank);
|
||||
return BANK_UNKNOWN;
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER( rex6000_state::bankswitch_r )
|
||||
{
|
||||
@ -161,8 +118,6 @@ READ8_MEMBER( rex6000_state::bankswitch_r )
|
||||
|
||||
WRITE8_MEMBER( rex6000_state::bankswitch_w )
|
||||
{
|
||||
address_space& program = m_maincpu->space(AS_PROGRAM);
|
||||
|
||||
m_bank[offset&3] = data;
|
||||
|
||||
switch (offset)
|
||||
@ -171,39 +126,13 @@ WRITE8_MEMBER( rex6000_state::bankswitch_w )
|
||||
case 1: //bank 1 high
|
||||
{
|
||||
//bank 1 start at 0x8000
|
||||
m_banks[0].page = (MAKE_BANK(m_bank[0], m_bank[1]&0x0f) + 4);
|
||||
m_banks[0].type = identify_bank_type(m_banks[0].page);
|
||||
|
||||
if (m_banks[0].type != BANK_UNKNOWN)
|
||||
{
|
||||
program.install_readwrite_handler(0x8000, 0x9fff, 0, 0, read8_delegate(FUNC(rex6000_state::flash_0x8000_r), this), write8_delegate(FUNC(rex6000_state::flash_0x8000_w), this));
|
||||
}
|
||||
else
|
||||
{
|
||||
program.unmap_readwrite(0x8000, 0x9fff);
|
||||
}
|
||||
|
||||
m_bankdev0->set_bank(MAKE_BANK(m_bank[0], m_bank[1]) + 4);
|
||||
break;
|
||||
}
|
||||
case 2: //bank 2 low
|
||||
case 3: //bank 2 high
|
||||
{
|
||||
m_banks[1].page = MAKE_BANK(m_bank[2], m_bank[3]&0x1f);
|
||||
m_banks[1].type = identify_bank_type(m_banks[1].page);
|
||||
|
||||
if (m_banks[1].type == BANK_RAM)
|
||||
{
|
||||
program.install_ram(0xa000, 0xbfff, m_ram_base + ((m_banks[1].page & 0x03)<<13));
|
||||
}
|
||||
else if (m_banks[1].type != BANK_UNKNOWN)
|
||||
{
|
||||
program.install_readwrite_handler(0xa000, 0xbfff, 0, 0, read8_delegate(FUNC(rex6000_state::flash_0xa000_r), this), write8_delegate(FUNC(rex6000_state::flash_0xa000_w), this));
|
||||
}
|
||||
else
|
||||
{
|
||||
program.unmap_readwrite(0xa000, 0xbfff);
|
||||
}
|
||||
|
||||
m_bankdev1->set_bank(MAKE_BANK(m_bank[2], m_bank[3]));
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -362,42 +291,24 @@ WRITE8_MEMBER( rex6000_state::touchscreen_w )
|
||||
m_touchscreen[offset&0x0f] = data;
|
||||
}
|
||||
|
||||
READ8_MEMBER( rex6000_state::flash_0x0000_r )
|
||||
{
|
||||
return m_flash[0]->read(offset);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( rex6000_state::flash_0x0000_w )
|
||||
{
|
||||
m_flash[0]->write(offset, data);
|
||||
}
|
||||
static ADDRESS_MAP_START(rex6000_banked_map, AS_PROGRAM, 8, rex6000_state)
|
||||
AM_RANGE( 0x0000000, 0x00fffff ) AM_DEVREADWRITE("flash0a", intelfsh8_device, read, write)
|
||||
AM_RANGE( 0x0100000, 0x01fffff ) AM_DEVREADWRITE("flash0b", intelfsh8_device, read, write)
|
||||
AM_RANGE( 0x0c00000, 0x0cfffff ) AM_DEVREADWRITE("flash1a", intelfsh8_device, read, write)
|
||||
AM_RANGE( 0x0d00000, 0x0dfffff ) AM_DEVREADWRITE("flash1b", intelfsh8_device, read, write)
|
||||
AM_RANGE( 0x1600000, 0x16fffff ) AM_DEVREADWRITE("flash1a", intelfsh8_device, read, write)
|
||||
AM_RANGE( 0x1700000, 0x17fffff ) AM_DEVREADWRITE("flash1b", intelfsh8_device, read, write)
|
||||
AM_RANGE( 0x2000000, 0x2007fff ) AM_RAM AM_SHARE("nvram")
|
||||
ADDRESS_MAP_END
|
||||
|
||||
READ8_MEMBER( rex6000_state::flash_0x8000_r )
|
||||
{
|
||||
return m_flash[m_banks[0].type]->read(((m_banks[0].page & 0x7f)<<13) | offset);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( rex6000_state::flash_0x8000_w )
|
||||
{
|
||||
m_flash[m_banks[0].type]->write(((m_banks[0].page & 0x7f)<<13) | offset, data);
|
||||
}
|
||||
|
||||
READ8_MEMBER( rex6000_state::flash_0xa000_r )
|
||||
{
|
||||
return m_flash[m_banks[1].type]->read(((m_banks[1].page & 0x7f)<<13) | offset);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( rex6000_state::flash_0xa000_w )
|
||||
{
|
||||
m_flash[m_banks[1].type]->write(((m_banks[1].page & 0x7f)<<13) | offset, data);
|
||||
}
|
||||
|
||||
|
||||
static ADDRESS_MAP_START(rex6000_mem, AS_PROGRAM, 8, rex6000_state)
|
||||
ADDRESS_MAP_UNMAP_HIGH
|
||||
AM_RANGE( 0x0000, 0x7fff ) AM_READWRITE(flash_0x0000_r, flash_0x0000_w)
|
||||
AM_RANGE( 0x8000, 0x9fff ) AM_READWRITE(flash_0x8000_r, flash_0x8000_w)
|
||||
AM_RANGE( 0xa000, 0xbfff ) AM_READWRITE(flash_0xa000_r, flash_0xa000_w)
|
||||
AM_RANGE( 0x0000, 0x7fff ) AM_DEVREADWRITE("flash0a", intelfsh8_device, read, write)
|
||||
AM_RANGE( 0x8000, 0x9fff ) AM_DEVREADWRITE("bank0", address_map_bank_device, read8, write8)
|
||||
AM_RANGE( 0xa000, 0xbfff ) AM_DEVREADWRITE("bank1", address_map_bank_device, read8, write8)
|
||||
AM_RANGE( 0xc000, 0xffff ) AM_RAMBANK("ram") //system RAM
|
||||
ADDRESS_MAP_END
|
||||
|
||||
@ -450,27 +361,11 @@ INPUT_PORTS_END
|
||||
|
||||
void rex6000_state::machine_start()
|
||||
{
|
||||
m_flash[0] = machine().device<fujitsu_29dl16x_device>("flash0a");
|
||||
m_flash[1] = machine().device<fujitsu_29dl16x_device>("flash0b");
|
||||
m_flash[2] = machine().device<fujitsu_29dl16x_device>("flash1a");
|
||||
m_flash[3] = machine().device<fujitsu_29dl16x_device>("flash1b");
|
||||
|
||||
m_ram_base = m_ram->pointer();
|
||||
membank("ram")->set_base(m_ram_base + 0x4000);
|
||||
membank("ram")->set_base((UINT8*)m_nvram + 0x4000);
|
||||
}
|
||||
|
||||
void rex6000_state::machine_reset()
|
||||
{
|
||||
address_space& program = m_maincpu->space(AS_PROGRAM);
|
||||
|
||||
program.install_readwrite_handler(0x8000, 0x9fff, 0, 0, read8_delegate(FUNC(rex6000_state::flash_0x8000_r), this), write8_delegate(FUNC(rex6000_state::flash_0x8000_w), this));
|
||||
program.install_readwrite_handler(0xa000, 0xbfff, 0, 0, read8_delegate(FUNC(rex6000_state::flash_0xa000_r), this), write8_delegate(FUNC(rex6000_state::flash_0xa000_w), this));
|
||||
|
||||
m_banks[0].type = 0x04;
|
||||
m_banks[0].type = 0;
|
||||
m_banks[1].type = 0x00;
|
||||
m_banks[1].type = 0;
|
||||
|
||||
memset(m_ram_base, 0, m_ram->size());
|
||||
memset(m_bank, 0, sizeof(m_bank));
|
||||
memset(m_beep_io, 0, sizeof(m_beep_io));
|
||||
memset(m_lcd_base, 0, sizeof(m_lcd_base));
|
||||
@ -485,25 +380,14 @@ void rex6000_state::machine_reset()
|
||||
|
||||
UINT32 rex6000_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
|
||||
{
|
||||
UINT16 lcd_bank = MAKE_BANK(m_lcd_base[0], m_lcd_base[1]&0x1f);
|
||||
UINT8 mem_type = identify_bank_type(lcd_bank);
|
||||
UINT16 lcd_bank = MAKE_BANK(m_lcd_base[0], m_lcd_base[1]);
|
||||
|
||||
if (m_lcd_enabled && mem_type != BANK_UNKNOWN)
|
||||
if (m_lcd_enabled)
|
||||
{
|
||||
for (int y=0; y<120; y++)
|
||||
for (int x=0; x<30; x++)
|
||||
{
|
||||
UINT8 data = 0;
|
||||
|
||||
if (mem_type == BANK_RAM)
|
||||
{
|
||||
data = (m_ram_base + ((lcd_bank & 0x03)<<13))[y*30 + x];
|
||||
}
|
||||
else
|
||||
{
|
||||
data = m_flash[mem_type]->space(0).read_byte(((lcd_bank & 0x7f)<<13) | (y*30 + x));
|
||||
}
|
||||
|
||||
UINT8 data = m_bankdev0->space(AS_PROGRAM).read_byte((lcd_bank << 13) + y*30 + x);
|
||||
|
||||
for (int b=0; b<8; b++)
|
||||
{
|
||||
@ -570,7 +454,7 @@ PALETTE_INIT_MEMBER(rex6000_state, rex6000)
|
||||
QUICKLOAD_LOAD_MEMBER( rex6000_state,rex6000)
|
||||
{
|
||||
static const char magic[] = "ApplicationName:Addin";
|
||||
address_space& flash = machine().device("flash0b")->memory().space(0);
|
||||
address_space& flash = m_flash0b->space(0);
|
||||
UINT32 img_start = 0;
|
||||
|
||||
dynamic_buffer data(image.length());
|
||||
@ -661,6 +545,18 @@ static MACHINE_CONFIG_START( rex6000, rex6000_state )
|
||||
MCFG_PALETTE_INIT_OWNER(rex6000_state, rex6000)
|
||||
MCFG_GFXDECODE_ADD("gfxdecode", "palette", rex6000)
|
||||
|
||||
MCFG_DEVICE_ADD("bank0", ADDRESS_MAP_BANK, 0)
|
||||
MCFG_DEVICE_PROGRAM_MAP(rex6000_banked_map)
|
||||
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
|
||||
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
|
||||
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
|
||||
|
||||
MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
|
||||
MCFG_DEVICE_PROGRAM_MAP(rex6000_banked_map)
|
||||
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
|
||||
MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(8)
|
||||
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
|
||||
|
||||
/* quickload */
|
||||
MCFG_QUICKLOAD_ADD("quickload", rex6000_state, rex6000, "rex,ds2", 0)
|
||||
|
||||
|
||||
@ -14,6 +14,7 @@
|
||||
#include "machine/rp5c01.h"
|
||||
#include "machine/ins8250.h"
|
||||
#include "machine/intelfsh.h"
|
||||
#include "machine/bankdev.h"
|
||||
#include "machine/nvram.h"
|
||||
#include "sound/speaker.h"
|
||||
#include "machine/ram.h"
|
||||
@ -36,7 +37,11 @@ public:
|
||||
m_speaker(*this, "speaker"),
|
||||
m_uart(*this, "ns16550"),
|
||||
m_serport(*this, "serport"),
|
||||
m_palette(*this, "palette")
|
||||
m_palette(*this, "palette"),
|
||||
m_bankdev1(*this, "bank0"),
|
||||
m_bankdev2(*this, "bank1"),
|
||||
m_flash1(*this, "flash1"),
|
||||
m_nvram(*this, "nvram")
|
||||
{ }
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
@ -45,25 +50,20 @@ public:
|
||||
required_device<ns16550_device> m_uart;
|
||||
required_device<rs232_port_device> m_serport;
|
||||
required_device<palette_device> m_palette;
|
||||
required_device<address_map_bank_device> m_bankdev1;
|
||||
required_device<address_map_bank_device> m_bankdev2;
|
||||
required_device<intelfsh8_device> m_flash1;
|
||||
required_shared_ptr<UINT8> m_nvram;
|
||||
|
||||
// defined in drivers/avigo.c
|
||||
virtual void machine_start() override;
|
||||
virtual void machine_reset() override;
|
||||
void postload();
|
||||
void refresh_memory(UINT8 bank, UINT8 chip_select);
|
||||
void refresh_ints();
|
||||
void nvram_init(nvram_device &nvram, void *base, size_t size);
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER( tc8521_alarm_int );
|
||||
DECLARE_WRITE_LINE_MEMBER( com_interrupt );
|
||||
|
||||
DECLARE_READ8_MEMBER(flash_0x0000_read_handler);
|
||||
DECLARE_WRITE8_MEMBER(flash_0x0000_write_handler);
|
||||
DECLARE_READ8_MEMBER(flash_0x4000_read_handler);
|
||||
DECLARE_WRITE8_MEMBER(flash_0x4000_write_handler);
|
||||
DECLARE_READ8_MEMBER(flash_0x8000_read_handler);
|
||||
DECLARE_WRITE8_MEMBER(flash_0x8000_write_handler);
|
||||
|
||||
DECLARE_READ8_MEMBER(key_data_read_r);
|
||||
DECLARE_WRITE8_MEMBER(set_key_line_w);
|
||||
DECLARE_WRITE8_MEMBER(port2_w);
|
||||
@ -99,14 +99,10 @@ public:
|
||||
UINT8 m_bank1_l;
|
||||
UINT8 m_bank1_h;
|
||||
UINT8 m_ad_control_status;
|
||||
intelfsh8_device * m_flashes[3];
|
||||
int m_flash_at_0x4000;
|
||||
int m_flash_at_0x8000;
|
||||
UINT16 m_ad_value;
|
||||
UINT8 * m_video_memory;
|
||||
UINT8 m_screen_column;
|
||||
UINT8 m_warm_start;
|
||||
UINT8 * m_ram_base;
|
||||
DECLARE_PALETTE_INIT(avigo);
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(avigo_scan_timer);
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(avigo_1hz_timer);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user