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Lucky Ball 96: Changes to the memory map and banking

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after an exhaustive hardware analysis. [Grull Osgo]
This commit is contained in:
Roberto Fresca 2018-09-02 02:14:29 +02:00
parent 40ff8a384e
commit 30efff8c13
1 changed files with 2 additions and 5 deletions
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7
src/mame/drivers/luckybal.cpp
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@ -262,7 +262,7 @@
*********************************************************************/ *********************************************************************/
#define CPU_CLOCK XTAL(12'000'000) #define CPU_CLOCK XTAL(12'000'000) // 12MHz. from schematics.
#define MCU_CLOCK XTAL(8'000'000) #define MCU_CLOCK XTAL(8'000'000)
#define VID_CLOCK XTAL(21'477'272) #define VID_CLOCK XTAL(21'477'272)
@ -340,10 +340,7 @@ private:
void luckybal_state::main_map(address_map &map) void luckybal_state::main_map(address_map &map)
{ {
map(0x0000, 0x57ff).rom(); map(0x0000, 0xbfff).rom();
map(0x6000, 0x7fff).bankr("bank1"); // Banked ROM.
map(0x8000, 0x9fff).bankr("bank1"); // Banked ROM.
map(0xa000, 0xbfff).bankr("bank1"); // Banked ROM.
map(0xc000, 0xdfff).bankr("bank1"); // Banked ROM. map(0xc000, 0xdfff).bankr("bank1"); // Banked ROM.
map(0xe000, 0xffff).ram().share("nvram"); // 6264 SRAM map(0xe000, 0xffff).ram().share("nvram"); // 6264 SRAM
} }