mirror of
https://github.com/holub/mame
synced 2025-04-28 11:11:48 +03:00
Align naming conventions of CD4XXX series. (nw)
This commit is contained in:
parent
d97724dfb6
commit
324de35c38
@ -24,7 +24,7 @@
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NETDEV_PARAMI(_name, model, _model)
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NETDEV_PARAMI(_name, model, _model)
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#define LM3900(_name) \
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#define LM3900(_name) \
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SUBMODEL(opamp_lm3900, name)
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SUBMODEL(opamp_lm3900, _name)
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// ----------------------------------------------------------------------------------------
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// ----------------------------------------------------------------------------------------
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// Devices ...
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// Devices ...
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@ -43,7 +43,7 @@ NETLIST_END()
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NETLIST_START(family_models)
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NETLIST_START(family_models)
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NET_MODEL(".model 74XXOC FAMILY(IVL=0.8 IVH=2.0 OVL=0.1 OVH=4.95 ORL=10.0 ORH=1.0e8)")
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NET_MODEL(".model 74XXOC FAMILY(IVL=0.8 IVH=2.0 OVL=0.1 OVH=4.95 ORL=10.0 ORH=1.0e8)")
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NET_MODEL(".model CD4000 FAMILY(TYPE=CD4000)")
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NET_MODEL(".model CD4XXX FAMILY(TYPE=CD4XXX)")
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NETLIST_END()
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NETLIST_END()
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@ -88,8 +88,6 @@ void initialize_factory(factory_list_t &factory)
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ENTRY(switch2, SWITCH2, "-")
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ENTRY(switch2, SWITCH2, "-")
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ENTRY(nicRSFF, NETDEV_RSFF, "+S,R")
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ENTRY(nicRSFF, NETDEV_RSFF, "+S,R")
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ENTRY(nicDelay, NETDEV_DELAY, "-")
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ENTRY(nicDelay, NETDEV_DELAY, "-")
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ENTRY(4020, CD_4020, "+IP,RESET,VDD,VSS")
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//ENTRY(4066, CD_4066, "+A,B")
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ENTRY(7400, TTL_7400_NAND, "+A,B")
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ENTRY(7400, TTL_7400_NAND, "+A,B")
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ENTRY(7402, TTL_7402_NOR, "+A,B")
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ENTRY(7402, TTL_7402_NOR, "+A,B")
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ENTRY(7404, TTL_7404_INVERT, "+A")
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ENTRY(7404, TTL_7404_INVERT, "+A")
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@ -122,11 +120,15 @@ void initialize_factory(factory_list_t &factory)
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ENTRY(9310, TTL_9310, "-")
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ENTRY(9310, TTL_9310, "-")
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ENTRY(9312, TTL_9312, "-")
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ENTRY(9312, TTL_9312, "-")
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ENTRY(9316, TTL_9316, "+CLK,ENP,ENT,CLRQ,LOADQ,A,B,C,D")
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ENTRY(9316, TTL_9316, "+CLK,ENP,ENT,CLRQ,LOADQ,A,B,C,D")
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ENTRY(CD4020, CD4020, "")
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/* entries with suffix _WI are legacy only */
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ENTRY(CD4020, CD4020_WI, "+IP,RESET,VDD,VSS")
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//ENTRY(4066, CD_4066, "+A,B")
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ENTRY(NE555, NE555, "-")
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ENTRY(NE555, NE555, "-")
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ENTRY(r2r_dac, R2R_DAC, "+VIN,R,N")
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ENTRY(r2r_dac, R2R_DAC, "+VIN,R,N")
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ENTRY(4020_dip, CD_4020_DIP, "-")
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ENTRY(CD4020_DIP, CD4020_DIP, "-")
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ENTRY(4016_dip, CD_4016_DIP, "-")
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ENTRY(CD4016_DIP, CD4016_DIP, "-")
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ENTRY(4066_dip, CD_4066_DIP, "-")
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ENTRY(CD4066_DIP, CD4066_DIP, "-")
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ENTRY(4538_dip, CD4538_DIP, "-")
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ENTRY(4538_dip, CD4538_DIP, "-")
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ENTRY(7400_dip, TTL_7400_DIP, "-")
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ENTRY(7400_dip, TTL_7400_DIP, "-")
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ENTRY(7402_dip, TTL_7402_DIP, "-")
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ENTRY(7402_dip, TTL_7402_DIP, "-")
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@ -9,7 +9,7 @@
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NETLIB_NAMESPACE_DEVICES_START()
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NETLIB_NAMESPACE_DEVICES_START()
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NETLIB_START(4020)
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NETLIB_START(CD4020)
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{
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{
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register_sub("sub", sub);
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register_sub("sub", sub);
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register_sub("supply", m_supply);
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register_sub("supply", m_supply);
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@ -32,13 +32,13 @@ NETLIB_START(4020)
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register_subalias("VSS", m_supply.m_vss);
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register_subalias("VSS", m_supply.m_vss);
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}
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}
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NETLIB_RESET(4020)
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NETLIB_RESET(CD4020)
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{
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{
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sub.do_reset();
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sub.do_reset();
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}
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}
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NETLIB_START(4020_sub)
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NETLIB_START(CD4020_sub)
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{
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{
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register_input("IP", m_IP);
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register_input("IP", m_IP);
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@ -58,13 +58,13 @@ NETLIB_START(4020_sub)
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save(NLNAME(m_cnt));
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save(NLNAME(m_cnt));
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}
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}
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NETLIB_RESET(4020_sub)
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NETLIB_RESET(CD4020_sub)
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{
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{
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m_IP.set_state(logic_t::STATE_INP_HL);
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m_IP.set_state(logic_t::STATE_INP_HL);
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m_cnt = 0;
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m_cnt = 0;
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}
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}
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NETLIB_UPDATE(4020_sub)
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NETLIB_UPDATE(CD4020_sub)
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{
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{
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UINT8 cnt = m_cnt;
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UINT8 cnt = m_cnt;
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cnt = ( cnt + 1) & 0x3fff;
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cnt = ( cnt + 1) & 0x3fff;
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@ -72,7 +72,7 @@ NETLIB_UPDATE(4020_sub)
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m_cnt = cnt;
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m_cnt = cnt;
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}
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}
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NETLIB_UPDATE(4020)
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NETLIB_UPDATE(CD4020)
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{
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{
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if (INPLOGIC(m_RESET))
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if (INPLOGIC(m_RESET))
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{
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{
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@ -87,7 +87,7 @@ NETLIB_UPDATE(4020)
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sub.m_IP.activate_hl();
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sub.m_IP.activate_hl();
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}
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}
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inline NETLIB_FUNC_VOID(4020_sub, update_outputs, (const UINT16 cnt))
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inline NETLIB_FUNC_VOID(CD4020_sub, update_outputs, (const UINT16 cnt))
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{
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{
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/* static */ const netlist_time out_delayQn[14] = {
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/* static */ const netlist_time out_delayQn[14] = {
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NLTIME_FROM_NS(180), NLTIME_FROM_NS(280),
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NLTIME_FROM_NS(180), NLTIME_FROM_NS(280),
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@ -104,9 +104,9 @@ inline NETLIB_FUNC_VOID(4020_sub, update_outputs, (const UINT16 cnt))
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OUTLOGIC(m_Q[i], (cnt >> i) & 1, out_delayQn[i]);
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OUTLOGIC(m_Q[i], (cnt >> i) & 1, out_delayQn[i]);
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}
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}
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NETLIB_START(4020_dip)
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NETLIB_START(CD4020_DIP)
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{
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{
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NETLIB_NAME(4020)::start();
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NETLIB_NAME(CD4020)::start();
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/* +--------------+
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/* +--------------+
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* Q12 |1 ++ 16| VDD
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* Q12 |1 ++ 16| VDD
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@ -139,14 +139,14 @@ NETLIB_START(4020_dip)
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register_subalias("16", m_supply.m_vdd);
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register_subalias("16", m_supply.m_vdd);
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}
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}
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NETLIB_UPDATE(4020_dip)
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NETLIB_UPDATE(CD4020_DIP)
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{
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{
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NETLIB_NAME(4020)::update();
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NETLIB_NAME(CD4020)::update();
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}
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}
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NETLIB_RESET(4020_dip)
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NETLIB_RESET(CD4020_DIP)
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{
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{
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NETLIB_NAME(4020)::reset();
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NETLIB_NAME(CD4020)::reset();
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}
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}
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NETLIB_NAMESPACE_DEVICES_END()
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NETLIB_NAMESPACE_DEVICES_END()
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@ -30,21 +30,25 @@
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#include "../nl_base.h"
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#include "../nl_base.h"
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#include "nld_cmos.h"
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#include "nld_cmos.h"
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#define CD_4020(_name, _IP, _RESET, _VDD, _VSS) \
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/* FIXME: only used in mario.c */
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NET_REGISTER_DEV(4020, _name) \
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#define CD4020_WI(_name, _IP, _RESET, _VDD, _VSS) \
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NET_REGISTER_DEV(CD4020, _name) \
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NET_CONNECT(_name, IP, _IP) \
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NET_CONNECT(_name, IP, _IP) \
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NET_CONNECT(_name, RESET, _RESET) \
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NET_CONNECT(_name, RESET, _RESET) \
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NET_CONNECT(_name, VDD, _VDD) \
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NET_CONNECT(_name, VDD, _VDD) \
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NET_CONNECT(_name, VSS, _VSS)
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NET_CONNECT(_name, VSS, _VSS)
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#define CD_4020_DIP(_name) \
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#define CD4020(_name, _IP, _RESET, _VDD, _VSS) \
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NET_REGISTER_DEV(4020_dip, _name)
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NET_REGISTER_DEV(CD4020, _name)
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#define CD4020_DIP(_name) \
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NET_REGISTER_DEV(CD4020_DIP, _name)
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NETLIB_NAMESPACE_DEVICES_START()
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NETLIB_NAMESPACE_DEVICES_START()
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NETLIB_SUBDEVICE(4020_sub,
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NETLIB_SUBDEVICE(CD4020_sub,
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NETLIB_LOGIC_FAMILY(CD4000)
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NETLIB_LOGIC_FAMILY(CD4XXX)
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ATTR_HOT void update_outputs(const UINT16 cnt);
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ATTR_HOT void update_outputs(const UINT16 cnt);
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logic_input_t m_IP;
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logic_input_t m_IP;
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@ -54,14 +58,14 @@ NETLIB_SUBDEVICE(4020_sub,
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logic_output_t m_Q[14];
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logic_output_t m_Q[14];
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);
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);
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NETLIB_DEVICE(4020,
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NETLIB_DEVICE(CD4020,
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NETLIB_LOGIC_FAMILY(CD4000)
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NETLIB_LOGIC_FAMILY(CD4XXX)
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NETLIB_NAME(4020_sub) sub;
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NETLIB_NAME(CD4020_sub) sub;
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NETLIB_NAME(vdd_vss) m_supply;
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NETLIB_NAME(vdd_vss) m_supply;
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logic_input_t m_RESET;
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logic_input_t m_RESET;
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);
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);
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NETLIB_DEVICE_DERIVED_PURE(4020_dip, 4020);
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NETLIB_DEVICE_DERIVED_PURE(CD4020_DIP, CD4020);
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NETLIB_NAMESPACE_DEVICES_END()
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NETLIB_NAMESPACE_DEVICES_END()
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@ -9,19 +9,19 @@
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NETLIB_NAMESPACE_DEVICES_START()
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NETLIB_NAMESPACE_DEVICES_START()
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NETLIB_START(4066)
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NETLIB_START(CD4066)
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{
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{
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register_input("CTL", m_control);
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register_input("CTL", m_control);
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register_sub("R", m_R);
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register_sub("R", m_R);
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m_base_r = 270.0;
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m_base_r = 270.0;
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}
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}
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NETLIB_RESET(4066)
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NETLIB_RESET(CD4066)
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{
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{
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m_R.do_reset();
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m_R.do_reset();
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}
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}
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NETLIB_UPDATE(4066)
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NETLIB_UPDATE(CD4066)
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{
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{
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nl_double sup = (m_supply->vdd() - m_supply->vss());
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nl_double sup = (m_supply->vdd() - m_supply->vss());
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nl_double low = NL_FCONST(0.45) * sup;
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nl_double low = NL_FCONST(0.45) * sup;
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@ -56,7 +56,7 @@ NETLIB_UPDATE(4066)
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}
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}
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NETLIB_START(4066_dip)
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NETLIB_START(CD4066_DIP)
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{
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{
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register_sub("supply", m_supply);
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register_sub("supply", m_supply);
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m_A.m_supply = m_B.m_supply = m_C.m_supply = m_D.m_supply = &m_supply;
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m_A.m_supply = m_B.m_supply = m_C.m_supply = m_D.m_supply = &m_supply;
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@ -85,7 +85,7 @@ NETLIB_START(4066_dip)
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}
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}
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NETLIB_RESET(4066_dip)
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NETLIB_RESET(CD4066_DIP)
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{
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{
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m_A.do_reset();
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m_A.do_reset();
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m_B.do_reset();
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m_B.do_reset();
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@ -93,7 +93,7 @@ NETLIB_RESET(4066_dip)
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m_D.do_reset();
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m_D.do_reset();
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}
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}
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NETLIB_UPDATE(4066_dip)
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NETLIB_UPDATE(CD4066_DIP)
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{
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{
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/* only called during startup */
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/* only called during startup */
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m_A.update_dev();
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m_A.update_dev();
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@ -102,22 +102,22 @@ NETLIB_UPDATE(4066_dip)
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m_D.update_dev();
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m_D.update_dev();
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}
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}
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NETLIB_START(4016_dip)
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NETLIB_START(CD4016_DIP)
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{
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{
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NETLIB_NAME(4066_dip)::start();
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NETLIB_NAME(CD4066_DIP)::start();
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m_A.m_base_r = m_B.m_base_r = m_C.m_base_r = m_D.m_base_r = 1000.0;
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m_A.m_base_r = m_B.m_base_r = m_C.m_base_r = m_D.m_base_r = 1000.0;
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}
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}
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NETLIB_RESET(4016_dip)
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NETLIB_RESET(CD4016_DIP)
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{
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{
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NETLIB_NAME(4066_dip)::reset();
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NETLIB_NAME(CD4066_DIP)::reset();
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}
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}
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NETLIB_UPDATE(4016_dip)
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NETLIB_UPDATE(CD4016_DIP)
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{
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{
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/* only called during startup */
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/* only called during startup */
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NETLIB_NAME(4066_dip)::update();
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NETLIB_NAME(CD4066_DIP)::update();
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}
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}
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NETLIB_NAMESPACE_DEVICES_END()
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NETLIB_NAMESPACE_DEVICES_END()
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@ -27,16 +27,16 @@
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#include "../nl_base.h"
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#include "../nl_base.h"
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#include "nld_cmos.h"
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#include "nld_cmos.h"
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#define CD_4066_DIP(_name) \
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#define CD4066_DIP(_name) \
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NET_REGISTER_DEV(4066_dip, _name)
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NET_REGISTER_DEV(CD4066_DIP, _name)
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#define CD_4016_DIP(_name) \
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#define CD4016_DIP(_name) \
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NET_REGISTER_DEV(4016_dip, _name)
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NET_REGISTER_DEV(CD4016_DIP, _name)
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NETLIB_NAMESPACE_DEVICES_START()
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NETLIB_NAMESPACE_DEVICES_START()
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NETLIB_SUBDEVICE(4066,
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NETLIB_SUBDEVICE(CD4066,
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NETLIB_LOGIC_FAMILY(CD4000)
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NETLIB_LOGIC_FAMILY(CD4XXX)
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public:
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public:
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analog_input_t m_control;
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analog_input_t m_control;
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@ -46,17 +46,17 @@ public:
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nl_double m_base_r;
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nl_double m_base_r;
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);
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);
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NETLIB_DEVICE(4066_dip,
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NETLIB_DEVICE(CD4066_DIP,
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NETLIB_LOGIC_FAMILY(CD4000)
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NETLIB_LOGIC_FAMILY(CD4XXX)
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NETLIB_NAME(4066) m_A;
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NETLIB_NAME(CD4066) m_A;
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NETLIB_NAME(4066) m_B;
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NETLIB_NAME(CD4066) m_B;
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NETLIB_NAME(4066) m_C;
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NETLIB_NAME(CD4066) m_C;
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NETLIB_NAME(4066) m_D;
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NETLIB_NAME(CD4066) m_D;
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NETLIB_NAME(vdd_vss) m_supply;
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NETLIB_NAME(vdd_vss) m_supply;
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);
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);
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NETLIB_DEVICE_DERIVED_PURE(4016_dip, 4066_dip);
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NETLIB_DEVICE_DERIVED_PURE(CD4016_DIP, CD4066_DIP);
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NETLIB_NAMESPACE_DEVICES_END()
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NETLIB_NAMESPACE_DEVICES_END()
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@ -116,7 +116,7 @@ NETLIB_DEVICE(9602_dip,
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NET_REGISTER_DEV(4538_dip, _name)
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NET_REGISTER_DEV(4538_dip, _name)
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|
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NETLIB_DEVICE(4538_dip,
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NETLIB_DEVICE(4538_dip,
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NETLIB_LOGIC_FAMILY(CD4000)
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NETLIB_LOGIC_FAMILY(CD4XXX)
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NETLIB_NAME(74123) m_1;
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NETLIB_NAME(74123) m_1;
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NETLIB_NAME(74123) m_2;
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NETLIB_NAME(74123) m_2;
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);
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);
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@ -150,7 +150,7 @@ NETLIB_UPDATE(SN74LS629)
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m_clock.m_inc = netlist_time::from_double(0.5 / (double) freq);
|
m_clock.m_inc = netlist_time::from_double(0.5 / (double) freq);
|
||||||
//m_clock.update();
|
//m_clock.update();
|
||||||
|
|
||||||
NL_VERBOSE_OUT(("%s %f %f %f\n", name().cstr(), v_freq, v_rng, freq));
|
//NL_VERBOSE_OUT(("%s %f %f %f\n", name().cstr(), v_freq, v_rng, freq));
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!m_clock.m_enableq && INPLOGIC(m_ENQ))
|
if (!m_clock.m_enableq && INPLOGIC(m_ENQ))
|
||||||
|
@ -46,7 +46,7 @@ NETLIST_START(CD4XXX_lib)
|
|||||||
TT_LINE("0,0|1|85")
|
TT_LINE("0,0|1|85")
|
||||||
TT_LINE("X,1|0|120")
|
TT_LINE("X,1|0|120")
|
||||||
TT_LINE("1,X|0|120")
|
TT_LINE("1,X|0|120")
|
||||||
TT_FAMILY("CD4000")
|
TT_FAMILY("CD4XXX")
|
||||||
TRUTHTABLE_END()
|
TRUTHTABLE_END()
|
||||||
|
|
||||||
LOCAL_LIB_ENTRY(CD4001_DIP)
|
LOCAL_LIB_ENTRY(CD4001_DIP)
|
||||||
|
@ -64,10 +64,10 @@ public:
|
|||||||
};
|
};
|
||||||
|
|
||||||
//FIXME: set to proper values
|
//FIXME: set to proper values
|
||||||
class logic_family_cd4000_t : public logic_family_desc_t
|
class logic_family_cd4xxx_t : public logic_family_desc_t
|
||||||
{
|
{
|
||||||
public:
|
public:
|
||||||
logic_family_cd4000_t() : logic_family_desc_t()
|
logic_family_cd4xxx_t() : logic_family_desc_t()
|
||||||
{
|
{
|
||||||
m_low_thresh_V = 0.8;
|
m_low_thresh_V = 0.8;
|
||||||
m_high_thresh_V = 2.0;
|
m_high_thresh_V = 2.0;
|
||||||
@ -85,7 +85,7 @@ public:
|
|||||||
};
|
};
|
||||||
|
|
||||||
logic_family_desc_t *netlist_family_TTL = palloc(logic_family_ttl_t);
|
logic_family_desc_t *netlist_family_TTL = palloc(logic_family_ttl_t);
|
||||||
logic_family_desc_t *netlist_family_CD4000 = palloc(logic_family_cd4000_t);
|
logic_family_desc_t *netlist_family_CD4XXX = palloc(logic_family_cd4xxx_t);
|
||||||
|
|
||||||
class logic_family_std_proxy_t : public logic_family_desc_t
|
class logic_family_std_proxy_t : public logic_family_desc_t
|
||||||
{
|
{
|
||||||
@ -101,8 +101,8 @@ logic_family_desc_t *logic_family_desc_t::from_model(const pstring &model)
|
|||||||
{
|
{
|
||||||
if (setup_t::model_value_str(model, "TYPE", "") == "TTL")
|
if (setup_t::model_value_str(model, "TYPE", "") == "TTL")
|
||||||
return netlist_family_TTL;
|
return netlist_family_TTL;
|
||||||
if (setup_t::model_value_str(model, "TYPE", "") == "CD4000")
|
if (setup_t::model_value_str(model, "TYPE", "") == "CD4XXX")
|
||||||
return netlist_family_CD4000;
|
return netlist_family_CD4XXX;
|
||||||
|
|
||||||
logic_family_std_proxy_t *ret = palloc(logic_family_std_proxy_t);
|
logic_family_std_proxy_t *ret = palloc(logic_family_std_proxy_t);
|
||||||
|
|
||||||
|
@ -351,7 +351,7 @@ namespace netlist
|
|||||||
|
|
||||||
|
|
||||||
extern logic_family_desc_t *netlist_family_TTL;
|
extern logic_family_desc_t *netlist_family_TTL;
|
||||||
extern logic_family_desc_t *netlist_family_CD4000;
|
extern logic_family_desc_t *netlist_family_CD4XXX;
|
||||||
|
|
||||||
|
|
||||||
// -----------------------------------------------------------------------------
|
// -----------------------------------------------------------------------------
|
||||||
|
@ -125,7 +125,7 @@ static NETLIST_START(nl_mario_snd7)
|
|||||||
NET_C(R65.2, 4K_A.FC, C44.1)
|
NET_C(R65.2, 4K_A.FC, C44.1)
|
||||||
NET_C(C44.2, GND)
|
NET_C(C44.2, GND)
|
||||||
|
|
||||||
CD_4020(3H, 4K_B.Y, ttllow, V5, GND)
|
CD4020_WI(3H, 4K_B.Y, ttllow, V5, GND)
|
||||||
TTL_7404_INVERT(4J_B, 3H.Q12)
|
TTL_7404_INVERT(4J_B, 3H.Q12)
|
||||||
|
|
||||||
RES(R64, RES_K(20))
|
RES(R64, RES_K(20))
|
||||||
@ -201,7 +201,7 @@ static NETLIST_START(nl_mario)
|
|||||||
PARAM(Solver.ACCURACY, 1e-8)
|
PARAM(Solver.ACCURACY, 1e-8)
|
||||||
PARAM(Solver.SOR_FACTOR, 1.0)
|
PARAM(Solver.SOR_FACTOR, 1.0)
|
||||||
PARAM(Solver.GS_THRESHOLD, 5)
|
PARAM(Solver.GS_THRESHOLD, 5)
|
||||||
PARAM(Solver.GS_LOOPS, 4)
|
PARAM(Solver.GS_LOOPS, 1)
|
||||||
//PARAM(Solver.LTE, 5e-2) // Default is not enough for paddle control
|
//PARAM(Solver.LTE, 5e-2) // Default is not enough for paddle control
|
||||||
PARAM(Solver.DYNAMIC_TS, 0)
|
PARAM(Solver.DYNAMIC_TS, 0)
|
||||||
ANALOG_INPUT(V5, 5)
|
ANALOG_INPUT(V5, 5)
|
||||||
@ -231,14 +231,7 @@ static NETLIST_START(nl_mario)
|
|||||||
NET_C(GND, R19.1) //FIXME
|
NET_C(GND, R19.1) //FIXME
|
||||||
NET_C(2K_C.Q, R41.1)
|
NET_C(2K_C.Q, R41.1)
|
||||||
|
|
||||||
#if 1
|
|
||||||
RES(DUM, RES_K(22))
|
|
||||||
NET_C(R39.1, DUM.1)
|
|
||||||
NET_C(DUM.2, GND)
|
|
||||||
FRONTIER(front1, R39.1, R40.1)
|
|
||||||
#else
|
|
||||||
NET_C(R39.1, R40.1)
|
NET_C(R39.1, R40.1)
|
||||||
#endif
|
|
||||||
|
|
||||||
NET_C(R20.2, R19.2, R40.2, R41.2, C31.1)
|
NET_C(R20.2, R19.2, R40.2, R41.2, C31.1)
|
||||||
NET_C(C31.2, GND)
|
NET_C(C31.2, GND)
|
||||||
@ -285,6 +278,7 @@ static NETLIST_START(nl_mario)
|
|||||||
|
|
||||||
NET_C(GND, ROUT.2)
|
NET_C(GND, ROUT.2)
|
||||||
|
|
||||||
|
OPTIMIZE_FRONTIER(R40.1, RES_K(22), 50)
|
||||||
NETLIST_END()
|
NETLIST_END()
|
||||||
|
|
||||||
#else
|
#else
|
||||||
|
@ -1619,7 +1619,7 @@ CIRCUIT_LAYOUT( breakout )
|
|||||||
|
|
||||||
RES(R33, 47)
|
RES(R33, 47)
|
||||||
|
|
||||||
CD_4016_DIP(D9)
|
CD4016_DIP(D9)
|
||||||
NET_C(D9.7, GND)
|
NET_C(D9.7, GND)
|
||||||
NET_C(D9.14, V5)
|
NET_C(D9.14, V5)
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user