mirror of
https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
vegas: Clean up duart code and make parallel read return not busy. (nw)
atlantis: Clean up interrupt handling and adjust PCI device mapping. (nw) vrc4373: Change to interrupt callback instead of direct interrupt assertion. (nw)
This commit is contained in:
Ted Green
parent
a381ec2f9f
commit
342a2dd3ed
@ -92,7 +92,7 @@ ADDRESS_MAP_END
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vrc4373_device::vrc4373_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: pci_host_device(mconfig, VRC4373, tag, owner, clock),
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m_cpu_space(nullptr), m_cpu(nullptr), cpu_tag(nullptr), m_irq_num(-1), m_ram_size(0x0), m_simm0_size(0x0),
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m_cpu_space(nullptr), m_irq_cb(*this), m_cpu(nullptr), cpu_tag(nullptr), m_ram_size(0x0), m_simm0_size(0x0),
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m_mem_config("memory_space", ENDIANNESS_LITTLE, 32, 32),
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m_io_config("io_space", ENDIANNESS_LITTLE, 32, 32), m_pci1_laddr(0), m_pci2_laddr(0), m_pci_io_laddr(0), m_target1_laddr(0), m_target2_laddr(0),
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m_romRegion(*this, "rom")
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@ -114,6 +114,7 @@ void vrc4373_device::device_start()
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m_cpu_space = &m_cpu->space(AS_PCI_CONFIG);
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memory_space = &space(AS_PCI_MEM);
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io_space = &space(AS_PCI_IO);
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is_multifunction_device = false;
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memset(m_cpu_regs, 0, sizeof(m_cpu_regs));
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@ -124,6 +125,9 @@ void vrc4373_device::device_start()
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io_window_end = 0xffffffff;
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io_offset = 0x00000000;
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status = 0x0280;
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m_irq_cb.resolve();
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// Reserve 8M for ram
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m_ram.reserve(0x00800000 / 4);
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m_ram.resize(m_ram_size);
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@ -414,8 +418,8 @@ TIMER_CALLBACK_MEMBER (vrc4373_device::dma_transfer)
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m_cpu_regs[NREG_DMACR1 + which * 0xc] &= ~DMA_GO;
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// Set the interrupt
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if (m_cpu_regs[NREG_DMACR1 + which * 0xc] & DMA_INT_EN) {
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if (m_irq_num != -1) {
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m_cpu->set_input_line(m_irq_num, ASSERT_LINE);
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if (!m_irq_cb.isnull()) {
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m_irq_cb(ASSERT_LINE);
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} else {
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logerror("vrc4373_device::dma_transfer Error: DMA configured to trigger interrupt but no interrupt line configured\n");
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}
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@ -436,6 +440,10 @@ READ32_MEMBER (vrc4373_device::cpu_if_r)
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case NREG_PCICDR:
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result = config_data_r(space, offset);
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break;
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case NREG_ICSR:
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// Top 16 bits always read as zero
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result &= 0xffff;
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break;
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default:
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break;
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}
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@ -514,6 +522,13 @@ WRITE32_MEMBER(vrc4373_device::cpu_if_w)
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LOGNILE("%08X:nile Start DMA Lane %i PCI: %08X MEM: %08X Words: %X\n", m_cpu->space(AS_PCI_CONFIG).device().safe_pc(), which, m_cpu_regs[NREG_DMA_CPAR], m_cpu_regs[NREG_DMA_CMAR], m_cpu_regs[NREG_DMA_REM]);
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}
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break;
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case NREG_ICSR:
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// TODO: Check and clear individual interrupts
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if (data & 0xff000000) {
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if (!m_irq_cb.isnull())
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m_irq_cb(CLEAR_LINE);
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}
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break;
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case NREG_BMCR:
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case NREG_SIMM1:
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case NREG_SIMM2:
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@ -20,6 +20,9 @@
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#define MCFG_VRC4373_SET_SIMM0(_size) \
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downcast<vrc4373_device *>(device)->set_simm0_size(_size);
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#define MCFG_VRC4373_IRQ_CB(_devcb) \
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devcb = &ide_pci_device::set_irq_cb(*device, DEVCB_##_devcb);
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class vrc4373_device : public pci_host_device {
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public:
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@ -30,6 +33,7 @@ public:
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uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override;
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void postload(void);
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template <class Object> static devcb_base &set_irq_cb(device_t &device, Object &&cb) { return downcast<vrc4373_device &>(device).m_irq_cb.set_callback(std::forward<Object>(cb)); }
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void set_cpu_tag(const char *tag);
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void set_ram_size(const int size) { m_ram_size = size; };
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void set_simm0_size(const int size) { m_simm0_size = size; };
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@ -80,9 +84,10 @@ private:
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void map_cpu_space();
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devcb_write_line m_irq_cb;
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mips3_device *m_cpu;
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const char *cpu_tag;
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int m_irq_num;
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int m_ram_size;
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int m_simm0_size;
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@ -61,29 +61,33 @@
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#define RESET_IDE 0x10
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#define RESET_DUART 0x20
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// IRQ Bits
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// IRQ Status Bits
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#define IOASIC_IRQ_SHIFT 0
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#define ROMBUS_IRQ_SHIFT 1
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#define ZEUS0_IRQ_SHIFT 2
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#define ZEUS1_IRQ_SHIFT 3
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#define ZEUS2_IRQ_SHIFT 4
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#define ZEUS_IRQ_SHIFT 2
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#define DUART_IRQ_SHIFT 3
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// PCI Slot and USB Chip
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#define PCI_IRQ_SHIFT 4
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#define WDOG_IRQ_SHIFT 5
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#define A2D_IRQ_SHIFT 6
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#define VBLANK_IRQ_SHIFT 7
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// DUART mapped to int3 (map3 = 0x08)
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#define UART1_IRQ_SHIFT ZEUS1_IRQ_SHIFT
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#define UART2_IRQ_SHIFT ZEUS1_IRQ_SHIFT
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// PCI mapped to int2 (map2 = 0x10)
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#define PCI_IRQ_SHIFT ZEUS2_IRQ_SHIFT
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/* static interrupts */
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#define GALILEO_IRQ_NUM MIPS3_IRQ0
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#define IDE_IRQ_NUM MIPS3_IRQ4
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#define PCI_ID_NILE ":pci:00.0"
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// From linux header
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// IDSEL = AD17, USB chip
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// IDSEL = AD18, CMD646 chip
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// IDSEL = AD19, onboard PCI slot
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// IDSEL = AD20, Nile 3 chip
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// IDSEL = AD21, PLX9050 chip
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// IDSEL = AD22, PCI expansion
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// IDSEL = AD23, PCI expansion
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// IDSEL = AD24, PCI expansion
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#define PCI_ID_IDE ":pci:08.0"
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#define PCI_ID_NILE ":pci:0a.0"
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#define PCI_ID_9050 ":pci:0b.0"
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#define PCI_ID_IDE ":pci:0c.0"
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#define DEBUG_CONSOLE (0)
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#define LOG_RTC (0)
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@ -161,8 +165,7 @@ public:
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DECLARE_WRITE_LINE_MEMBER(watchdog_irq);
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DECLARE_WRITE_LINE_MEMBER(watchdog_reset);
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DECLARE_WRITE_LINE_MEMBER(uart1_irq_callback);
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DECLARE_WRITE_LINE_MEMBER(uart2_irq_callback);
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DECLARE_WRITE_LINE_MEMBER(duart_irq_callback);
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DECLARE_CUSTOM_INPUT_MEMBER(port_mod_r);
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DECLARE_READ16_MEMBER(port_ctrl_r);
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@ -183,8 +186,9 @@ public:
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// Parallel Port
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READ8_MEMBER(atlantis_state::parallel_r)
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{
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logerror("%06X: parallel_r %08x = %02x\n", machine().device("maincpu")->safe_pc(), offset, 0);
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return 0x3;
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uint8_t result = 0x7;
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logerror("%06X: parallel_r %08x = %02x\n", machine().device("maincpu")->safe_pc(), offset, result);
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return result;
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}
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WRITE8_MEMBER(atlantis_state::parallel_w)
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@ -268,9 +272,7 @@ WRITE32_MEMBER(atlantis_state::board_ctrl_w)
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// 0x1 VBlank clear?
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if (changeData & 0x1) {
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if ((data & 0x0001) == 0) {
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uint32_t status_bit = (1 << VBLANK_IRQ_SHIFT);
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board_ctrl[CAUSE] &= ~status_bit;
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board_ctrl[STATUS] &= ~status_bit;
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board_ctrl[STATUS] &= ~(1 << VBLANK_IRQ_SHIFT);
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update_asic_irq();
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}
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else {
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@ -281,7 +283,6 @@ WRITE32_MEMBER(atlantis_state::board_ctrl_w)
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break;
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case IRQ_EN:
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// Zero bit will clear cause
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board_ctrl[CAUSE] &= data;
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update_asic_irq();
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if (LOG_IRQ)
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logerror("%s:board_ctrl_w write to IRQ_EN offset %04X = %08X & %08X bus offset = %08X\n", machine().describe_context(), newOffset, data, mem_mask, offset);
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@ -395,39 +396,20 @@ READ32_MEMBER(atlantis_state::user_io_input)
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}
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/*************************************
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* UART1 interrupt handler
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* DUART interrupt handler
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*************************************/
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WRITE_LINE_MEMBER(atlantis_state::uart1_irq_callback)
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WRITE_LINE_MEMBER(atlantis_state::duart_irq_callback)
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{
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uint32_t status_bit = UART1_IRQ_SHIFT;
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uint32_t status_bit = 1 << DUART_IRQ_SHIFT;
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if (state && !(board_ctrl[STATUS] & status_bit)) {
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board_ctrl[STATUS] |= status_bit;
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update_asic_irq();
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}
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else if (!state && (board_ctrl[STATUS] & status_bit)) {
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board_ctrl[STATUS] &= ~status_bit;
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board_ctrl[CAUSE] &= ~status_bit;
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update_asic_irq();
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}
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logerror("atlantis_state::uart1_irq_callback state = %1x\n", state);
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}
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/*************************************
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* UART2 interrupt handler
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*************************************/
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WRITE_LINE_MEMBER(atlantis_state::uart2_irq_callback)
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{
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uint32_t status_bit = UART2_IRQ_SHIFT;
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if (state && !(board_ctrl[STATUS] & status_bit)) {
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board_ctrl[STATUS] |= status_bit;
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update_asic_irq();
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}
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else if (!state && (board_ctrl[STATUS] & status_bit)) {
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board_ctrl[STATUS] &= ~status_bit;
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board_ctrl[CAUSE] &= ~status_bit;
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update_asic_irq();
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}
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logerror("atlantis_state::uart2_irq_callback state = %1x\n", state);
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logerror("atlantis_state::duart_irq_callback state = %1x\n", state);
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}
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/*************************************
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@ -438,27 +420,23 @@ WRITE_LINE_MEMBER(atlantis_state::vblank_irq)
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//logerror("%s: atlantis_state::vblank state = %i\n", machine().describe_context(), state);
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if (state) {
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board_ctrl[STATUS] |= (1 << VBLANK_IRQ_SHIFT);
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update_asic_irq();
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}
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else {
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board_ctrl[STATUS] &= ~(1 << VBLANK_IRQ_SHIFT);
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board_ctrl[CAUSE] &= ~(1 << VBLANK_IRQ_SHIFT);
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update_asic_irq();
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}
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update_asic_irq();
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}
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WRITE_LINE_MEMBER(atlantis_state::zeus_irq)
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{
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//logerror("%s: atlantis_state::zeus_irq state = %i\n", machine().describe_context(), state);
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if (state) {
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board_ctrl[STATUS] |= (1 << ZEUS0_IRQ_SHIFT);
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update_asic_irq();
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board_ctrl[STATUS] |= (1 << ZEUS_IRQ_SHIFT);
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}
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else {
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board_ctrl[STATUS] &= ~(1 << ZEUS0_IRQ_SHIFT);
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board_ctrl[CAUSE] &= ~(1 << ZEUS0_IRQ_SHIFT);
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update_asic_irq();
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board_ctrl[STATUS] &= ~(1 << ZEUS_IRQ_SHIFT);
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}
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update_asic_irq();
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}
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/*************************************
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@ -466,7 +444,14 @@ WRITE_LINE_MEMBER(atlantis_state::zeus_irq)
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*************************************/
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WRITE_LINE_MEMBER(atlantis_state::ide_irq)
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{
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m_maincpu->set_input_line(IDE_IRQ_NUM, state);
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if (state) {
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m_maincpu->set_input_line(IDE_IRQ_NUM, ASSERT_LINE);
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m_irq_state |= (1 << IDE_IRQ_NUM);
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}
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else {
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m_maincpu->set_input_line(IDE_IRQ_NUM, CLEAR_LINE);
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m_irq_state &= ~(1 << IDE_IRQ_NUM);
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}
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if (LOG_IRQ)
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logerror("%s: atlantis_state::ide_irq state = %i\n", machine().describe_context(), state);
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}
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@ -480,13 +465,11 @@ WRITE_LINE_MEMBER(atlantis_state::ioasic_irq)
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logerror("%s: atlantis_state::ioasic_irq state = %i\n", machine().describe_context(), state);
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if (state) {
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board_ctrl[STATUS] |= (1 << IOASIC_IRQ_SHIFT);
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update_asic_irq();
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}
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else {
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board_ctrl[STATUS] &= ~(1 << IOASIC_IRQ_SHIFT);
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board_ctrl[CAUSE] &= ~(1 << IOASIC_IRQ_SHIFT);
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update_asic_irq();
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}
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update_asic_irq();
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}
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/*************************************
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@ -498,14 +481,11 @@ WRITE_LINE_MEMBER(atlantis_state::watchdog_irq)
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logerror("%s: atlantis_state::watchdog_irq state = %i\n", machine().describe_context(), state);
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if (state) {
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board_ctrl[STATUS] |= (1 << WDOG_IRQ_SHIFT);
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update_asic_irq();
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}
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else {
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board_ctrl[STATUS] &= ~(1 << WDOG_IRQ_SHIFT);
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board_ctrl[CAUSE] &= ~(1 << WDOG_IRQ_SHIFT);
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update_asic_irq();
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}
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update_asic_irq();
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}
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/*************************************
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@ -525,12 +505,13 @@ WRITE_LINE_MEMBER(atlantis_state::watchdog_reset)
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*************************************/
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void atlantis_state::update_asic_irq()
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{
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// Update cause register
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board_ctrl[CAUSE] = board_ctrl[IRQ_EN] & board_ctrl[STATUS];
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// Check the MAP1, MAP2, and MAP3 and signal interrupt
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for (int irqIndex = 0; irqIndex < 3; irqIndex++) {
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uint32_t irqBits = (board_ctrl[IRQ_EN] & board_ctrl[IRQ_MAP1 + irqIndex] & board_ctrl[STATUS]);
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uint32_t causeBits = (board_ctrl[IRQ_EN] & board_ctrl[IRQ_MAP1 + irqIndex] & board_ctrl[CAUSE]);
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uint32_t causeBits = board_ctrl[CAUSE] & board_ctrl[IRQ_MAP1 + irqIndex];
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uint32_t currState = m_irq_state & (2 << irqIndex);
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board_ctrl[CAUSE] |= irqBits;
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if (irqBits && !currState) {
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if (causeBits && !currState) {
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m_maincpu->set_input_line(MIPS3_IRQ1 + irqIndex, ASSERT_LINE);
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m_irq_state |= (2 << irqIndex);
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if (LOG_IRQ)
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@ -727,9 +708,9 @@ static INPUT_PORTS_START( mwskins )
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PORT_DIPSETTING(0x0002, "Boot Disk Based Self Test")
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PORT_DIPSETTING(0x0001, "Boot EEPROM Based Self Test")
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PORT_DIPSETTING(0x0000, "Run Interactive Tests")
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PORT_DIPNAME(0x0004, 0x0004, "Boot Message")
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PORT_DIPSETTING(0x0004, "Quiet")
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PORT_DIPSETTING(0x0000, "Squawk During Boot")
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PORT_DIPNAME(0x0004, 0x0004, "Console Enable")
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PORT_DIPSETTING(0x0004, DEF_STR(No))
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PORT_DIPSETTING(0x0000, DEF_STR(Yes))
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PORT_DIPUNUSED(0xfff8, 0xfff8)
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PORT_START("SYSTEM")
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@ -816,6 +797,7 @@ static MACHINE_CONFIG_START( mwskins )
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MCFG_CPU_ADD("maincpu", VR4310LE, 166666666) // clock is TRUSTED
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MCFG_MIPS3_ICACHE_SIZE(16384)
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MCFG_MIPS3_DCACHE_SIZE(16384)
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MCFG_MIPS3_SYSTEM_CLOCK(66666666)
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MCFG_PCI_ROOT_ADD( ":pci")
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MCFG_VRC4373_ADD( PCI_ID_NILE, ":maincpu")
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@ -832,8 +814,13 @@ static MACHINE_CONFIG_START( mwskins )
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MCFG_M48T37_RESET_HANDLER(WRITELINE(atlantis_state, watchdog_reset))
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MCFG_M48T37_IRQ_HANDLER(WRITELINE(atlantis_state, watchdog_irq))
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MCFG_IDE_PCI_ADD(PCI_ID_IDE, 0x10950646, 0x07, 0x0)
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MCFG_IDE_PCI_ADD(PCI_ID_IDE, 0x10950646, 0x05, 0x0)
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MCFG_IDE_PCI_IRQ_HANDLER(DEVWRITELINE(":", atlantis_state, ide_irq))
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// The pci-ide by default expects the system controller to be pci:00.0 so need to fix here
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MCFG_DEVICE_MODIFY(PCI_ID_IDE":ide")
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MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(PCI_ID_NILE, AS_DATA)
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MCFG_DEVICE_MODIFY(PCI_ID_IDE":ide2")
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MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(PCI_ID_NILE, AS_DATA)
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/* video hardware */
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MCFG_DEVICE_ADD("zeus2", ZEUS2, ZEUS2_VIDEO_CLOCK)
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@ -868,13 +855,13 @@ static MACHINE_CONFIG_START( mwskins )
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MCFG_INS8250_OUT_TX_CB(DEVWRITELINE("com1", rs232_port_device, write_txd))
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MCFG_INS8250_OUT_DTR_CB(DEVWRITELINE("com1", rs232_port_device, write_dtr))
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MCFG_INS8250_OUT_RTS_CB(DEVWRITELINE("com1", rs232_port_device, write_rts))
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MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", atlantis_state, uart1_irq_callback))
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MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", atlantis_state, duart_irq_callback))
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MCFG_DEVICE_ADD("uart2", NS16550, XTAL_24MHz)
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MCFG_INS8250_OUT_TX_CB(DEVWRITELINE("com2", rs232_port_device, write_txd))
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MCFG_INS8250_OUT_DTR_CB(DEVWRITELINE("com2", rs232_port_device, write_dtr))
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MCFG_INS8250_OUT_RTS_CB(DEVWRITELINE("com2", rs232_port_device, write_rts))
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MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", atlantis_state, uart2_irq_callback))
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MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", atlantis_state, duart_irq_callback))
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||||
|
||||
MCFG_RS232_PORT_ADD("com1", default_rs232_devices, nullptr)
|
||||
MCFG_RS232_RXD_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, rx_w))
|
||||
|
||||
@ -358,8 +358,7 @@ public:
|
||||
uint32_t m_keypad_select;
|
||||
uint32_t m_gear;
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER(uart1_irq_cb);
|
||||
DECLARE_WRITE_LINE_MEMBER(uart2_irq_cb);
|
||||
DECLARE_WRITE_LINE_MEMBER(duart_irq_cb);
|
||||
DECLARE_WRITE_LINE_MEMBER(vblank_assert);
|
||||
DECLARE_DRIVER_INIT(gauntleg);
|
||||
DECLARE_DRIVER_INIT(cartfury);
|
||||
@ -581,22 +580,12 @@ void vegas_state::update_sio_irqs()
|
||||
}
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(vegas_state::uart1_irq_cb)
|
||||
WRITE_LINE_MEMBER(vegas_state::duart_irq_cb)
|
||||
{
|
||||
if (state)
|
||||
m_sio_irq_state |= (1 << 4);
|
||||
m_nile->pci_intr_c(ASSERT_LINE);
|
||||
else
|
||||
m_sio_irq_state &= ~(1 << 4);
|
||||
update_sio_irqs();
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(vegas_state::uart2_irq_cb)
|
||||
{
|
||||
if (state)
|
||||
m_sio_irq_state |= (1 << 4);
|
||||
else
|
||||
m_sio_irq_state &= ~(1 << 4);
|
||||
update_sio_irqs();
|
||||
m_nile->pci_intr_c(CLEAR_LINE);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(vegas_state::vblank_assert)
|
||||
@ -949,7 +938,7 @@ READ32_MEMBER(vegas_state::unknown_r)
|
||||
*************************************/
|
||||
READ8_MEMBER(vegas_state::parallel_r)
|
||||
{
|
||||
uint8_t result = 0x3;
|
||||
uint8_t result = 0x7;
|
||||
logerror("%06X: parallel_r %08x = %02x\n", machine().device("maincpu")->safe_pc(), offset, result);
|
||||
return result;
|
||||
}
|
||||
@ -1524,9 +1513,9 @@ static INPUT_PORTS_START( sf2049se )
|
||||
|
||||
PORT_MODIFY("DIPS")
|
||||
PORT_DIPUNUSED( 0x001e, 0x001e )
|
||||
PORT_DIPNAME(0x0020, 0x0020, "Boot Message")
|
||||
PORT_DIPSETTING( 0x0020, "Quiet")
|
||||
PORT_DIPSETTING( 0x0000, "Squawk During Boot")
|
||||
PORT_DIPNAME( 0x0020, 0x0020, "Console Enable" )
|
||||
PORT_DIPSETTING( 0x0020, DEF_STR(No))
|
||||
PORT_DIPSETTING( 0x0000, DEF_STR(Yes))
|
||||
PORT_DIPNAME( 0x00c0, 0x00c0, "Test Mode" )
|
||||
PORT_DIPSETTING( 0x00c0, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x0080, "Disk-based Test" )
|
||||
@ -1636,9 +1625,10 @@ static ADDRESS_MAP_START(vegas_cs7_map, AS_PROGRAM, 32, vegas_state)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START(vegas_cs8_map, AS_PROGRAM, 32, vegas_state)
|
||||
AM_RANGE(0x01000000, 0x0100001f) AM_DEVREADWRITE8("uart2", ns16550_device, ins8250_r, ins8250_w, 0xff) // Serial UART2 (TL16C552 CS0)
|
||||
AM_RANGE(0x01400000, 0x0140001f) AM_DEVREADWRITE8("uart1", ns16550_device, ins8250_r, ins8250_w, 0xff) // Serial UART1 (TL16C552 CS1)
|
||||
AM_RANGE(0x01000000, 0x0100001f) AM_DEVREADWRITE8("uart1", ns16550_device, ins8250_r, ins8250_w, 0xff) // Serial ttyS01 (TL16C552 CS0)
|
||||
AM_RANGE(0x01400000, 0x0140001f) AM_DEVREADWRITE8("uart2", ns16550_device, ins8250_r, ins8250_w, 0xff) // Serial ttyS02 (TL16C552 CS1)
|
||||
AM_RANGE(0x01800000, 0x0180001f) AM_READWRITE8(parallel_r, parallel_w, 0xff) // Parallel UART (TL16C552 CS2)
|
||||
//AM_RANGE(0x01c00000, 0x0180001f) AM_READWRITE8(parallel_r, parallel_w, 0xff) // MPS Reset
|
||||
ADDRESS_MAP_END
|
||||
|
||||
/*************************************
|
||||
@ -1667,7 +1657,7 @@ static MACHINE_CONFIG_START( vegascore )
|
||||
MCFG_VRC5074_SET_CS(6, vegas_cs6_map)
|
||||
MCFG_VRC5074_SET_CS(7, vegas_cs7_map)
|
||||
|
||||
MCFG_IDE_PCI_ADD(PCI_ID_IDE, 0x10950646, 0x07, 0x0)
|
||||
MCFG_IDE_PCI_ADD(PCI_ID_IDE, 0x10950646, 0x05, 0x0)
|
||||
MCFG_IDE_PCI_IRQ_HANDLER(DEVWRITELINE(PCI_ID_NILE, vrc5074_device, pci_intr_d))
|
||||
//MCFG_IDE_PCI_SET_PIF(0x8f)
|
||||
|
||||
@ -1762,25 +1752,25 @@ static MACHINE_CONFIG_DERIVED( denver, vegascore )
|
||||
|
||||
// TL16C552 UART
|
||||
MCFG_DEVICE_ADD("uart1", NS16550, vegas_state::SYSTEM_CLOCK / 12)
|
||||
MCFG_INS8250_OUT_TX_CB(DEVWRITELINE("com1", rs232_port_device, write_txd))
|
||||
MCFG_INS8250_OUT_DTR_CB(DEVWRITELINE("com1", rs232_port_device, write_dtr))
|
||||
MCFG_INS8250_OUT_RTS_CB(DEVWRITELINE("com1", rs232_port_device, write_rts))
|
||||
MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", vegas_state, uart1_irq_cb))
|
||||
MCFG_INS8250_OUT_TX_CB(DEVWRITELINE("ttys01", rs232_port_device, write_txd))
|
||||
MCFG_INS8250_OUT_DTR_CB(DEVWRITELINE("ttys01", rs232_port_device, write_dtr))
|
||||
MCFG_INS8250_OUT_RTS_CB(DEVWRITELINE("ttys01", rs232_port_device, write_rts))
|
||||
MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", vegas_state, duart_irq_cb))
|
||||
|
||||
MCFG_DEVICE_ADD("uart2", NS16550, vegas_state::SYSTEM_CLOCK / 12)
|
||||
MCFG_INS8250_OUT_TX_CB(DEVWRITELINE("com2", rs232_port_device, write_txd))
|
||||
MCFG_INS8250_OUT_DTR_CB(DEVWRITELINE("com2", rs232_port_device, write_dtr))
|
||||
MCFG_INS8250_OUT_RTS_CB(DEVWRITELINE("com2", rs232_port_device, write_rts))
|
||||
MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", vegas_state, uart2_irq_cb))
|
||||
MCFG_INS8250_OUT_TX_CB(DEVWRITELINE("ttys02", rs232_port_device, write_txd))
|
||||
MCFG_INS8250_OUT_DTR_CB(DEVWRITELINE("ttys02", rs232_port_device, write_dtr))
|
||||
MCFG_INS8250_OUT_RTS_CB(DEVWRITELINE("ttys02", rs232_port_device, write_rts))
|
||||
MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", vegas_state, duart_irq_cb))
|
||||
|
||||
MCFG_RS232_PORT_ADD("com1", default_rs232_devices, nullptr)
|
||||
MCFG_RS232_PORT_ADD("ttys01", default_rs232_devices, nullptr)
|
||||
MCFG_RS232_RXD_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, rx_w))
|
||||
MCFG_RS232_DCD_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, dcd_w))
|
||||
MCFG_RS232_DSR_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, dsr_w))
|
||||
MCFG_RS232_RI_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, ri_w))
|
||||
MCFG_RS232_CTS_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, cts_w))
|
||||
|
||||
MCFG_RS232_PORT_ADD("com2", default_rs232_devices, nullptr)
|
||||
MCFG_RS232_PORT_ADD("ttys02", default_rs232_devices, nullptr)
|
||||
MCFG_RS232_RXD_HANDLER(DEVWRITELINE("uart2", ins8250_uart_device, rx_w))
|
||||
MCFG_RS232_DCD_HANDLER(DEVWRITELINE("uart2", ins8250_uart_device, dcd_w))
|
||||
MCFG_RS232_DSR_HANDLER(DEVWRITELINE("uart2", ins8250_uart_device, dsr_w))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user