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Attempt to improve gd-rom timings

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This commit is contained in:
Angelo Salese 2013-09-04 20:57:50 +00:00
parent e6fd16cf84
commit 38c1aeba3b
3 changed files with 14 additions and 2 deletions
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4
src/mame/machine/naomig1.c
View File

@ -153,7 +153,9 @@ WRITE32_MEMBER(naomi_g1_device::sb_gdst_w)
len -= tlen;
}
timer->adjust(attotime::from_usec(500));
/* 12x * 75 Hz = 0,00(1) secs per sector */
/* TODO: make DMA to be single step */
timer->adjust(attotime::from_usec(1111*(gdlen/2048)));
}
}

7
src/mess/drivers/dccons.c
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@ -375,6 +375,11 @@ static ADDRESS_MAP_START( dc_map, AS_PROGRAM, 64, dc_cons_state )
AM_RANGE(0x00700000, 0x00707fff) AM_READWRITE32(dc_aica_reg_r, dc_aica_reg_w, U64(0xffffffffffffffff))
AM_RANGE(0x00710000, 0x0071000f) AM_MIRROR(0x02000000) AM_READWRITE32(dc_rtc_r, dc_rtc_w, U64(0xffffffffffffffff) )
AM_RANGE(0x00800000, 0x009fffff) AM_READWRITE(dc_arm_r, dc_arm_w )
// AM_RANGE(0x01000000, 0x01ffffff) G2 Ext Device #1
// AM_RANGE(0x02700000, 0x02707fff) AICA reg mirror
// AM_RANGE(0x02800000, 0x02ffffff) AICA wave mem mirror
// AM_RANGE(0x03000000, 0x03ffffff) G2 Ext Device #2
/* Area 1 */
AM_RANGE(0x04000000, 0x04ffffff) AM_RAM AM_SHARE("dc_texture_ram") // texture memory 64 bit access
@ -395,6 +400,8 @@ static ADDRESS_MAP_START( dc_map, AS_PROGRAM, 64, dc_cons_state )
AM_RANGE(0x12800000, 0x12ffffff) AM_DEVWRITE8("powervr2", powervr2_device, ta_fifo_yuv_w, U64(0xffffffffffffffff))
AM_RANGE(0x13000000, 0x137fffff) AM_DEVWRITE("powervr2", powervr2_device, ta_texture_directpath1_w) AM_MIRROR(0x00800000) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue
// AM_RANGE(0x14000000, 0x17ffffff) G2 Ext Device #3
AM_RANGE(0x8c000000, 0x8cffffff) AM_RAM AM_SHARE("dc_ram") // another RAM mirror
AM_RANGE(0xa0000000, 0xa01fffff) AM_ROM AM_REGION("maincpu", 0)

5
src/mess/machine/dccons.c
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@ -145,7 +145,10 @@ WRITE32_MEMBER(dc_cons_state::dc_mess_g1_ctrl_w )
}
atapi_xferbase = g1bus_regs[SB_GDSTAR];
atapi_timer->adjust(m_maincpu->cycles_to_attotime((ATAPI_CYCLES_PER_SECTOR * (atapi_xferlen/2048))));
//atapi_timer->adjust(m_maincpu->cycles_to_attotime((ATAPI_CYCLES_PER_SECTOR * (atapi_xferlen/2048))));
/* 12x * 75 Hz = 0,00(1) secs per sector */
/* TODO: make DMA to be single step */
atapi_timer->adjust(attotime::from_usec(1111*atapi_xferlen/2048));
// atapi_regs[ATAPI_REG_SAMTAG] = GDROM_PAUSE_STATE | 0x80;
}
break;