Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-04-19 15:11:37 +03:00
Code Issues Actions 3 Packages Projects Releases Wiki Activity

Implement 7402, 7408 as macro device. (nw)

Browse Source
This commit is contained in:
couriersud 2016-05-03 02:32:29 +02:00
parent 6f889d51ae
commit 3acd03bd5f
10 changed files with 135 additions and 272 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
scripts/src/netlist.lua
View File

@ -86,10 +86,6 @@ project "netlist"
MAME_DIR .. "src/lib/netlist/devices/nld_4020.h",
MAME_DIR .. "src/lib/netlist/devices/nld_4066.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_4066.h",
MAME_DIR .. "src/lib/netlist/devices/nld_7402.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_7402.h",
MAME_DIR .. "src/lib/netlist/devices/nld_7408.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_7408.h",
MAME_DIR .. "src/lib/netlist/devices/nld_7410.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_7410.h",
MAME_DIR .. "src/lib/netlist/devices/nld_7411.cpp",

4
src/lib/netlist/devices/net_lib.cpp
View File

@ -98,8 +98,6 @@ void initialize_factory(factory_list_t &factory)
ENTRY(switch2, SWITCH2, "-")
ENTRY(nicRSFF, NETDEV_RSFF, "+S,R")
ENTRY(nicDelay, NETDEV_DELAY, "-")
ENTRY(7402, TTL_7402_NOR, "+A,B")
ENTRY(7408, TTL_7408_AND, "+A,B")
ENTRY(7410, TTL_7410_NAND, "+A,B,C")
ENTRY(7411, TTL_7411_AND, "+A,B,C")
ENTRY(7420, TTL_7420_NAND, "+A,B,C,D")
@ -136,8 +134,6 @@ void initialize_factory(factory_list_t &factory)
ENTRY(NE555, NE555, "-")
ENTRY(r2r_dac, R2R_DAC, "+VIN,R,N")
ENTRY(4538_dip, CD4538_DIP, "-")
ENTRY(7402_dip, TTL_7402_DIP, "-")
ENTRY(7408_dip, TTL_7408_DIP, "-")
ENTRY(7410_dip, TTL_7410_DIP, "-")
ENTRY(7411_dip, TTL_7411_DIP, "-")
ENTRY(7420_dip, TTL_7420_DIP, "-")

2
src/lib/netlist/devices/net_lib.h
View File

@ -17,8 +17,6 @@
#include "nld_4020.h"
#include "nld_4066.h"
#include "nld_7402.h"
#include "nld_7408.h"
#include "nld_7410.h"
#include "nld_7411.h"
#include "nld_7420.h"

65
src/lib/netlist/devices/nld_7402.cpp
View File

@ -1,65 +0,0 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_7402.c
*
*/
#include "nld_7402.h"
NETLIB_NAMESPACE_DEVICES_START()
#if (USE_TRUTHTABLE)
nld_7402::truthtable_t nld_7402::m_ttbl;
const char *nld_7402::m_desc[] = {
"A , B | Q ",
"0,0|1|22",
"X,1|0|15",
"1,X|0|15",
""
};
#endif
NETLIB_START(7402_dip)
{
register_sub("1", m_1);
register_sub("2", m_2);
register_sub("3", m_3);
register_sub("4", m_4);
register_subalias("1", m_1->m_Q[0]);
register_subalias("2", m_1->m_I[0]);
register_subalias("3", m_1->m_I[1]);
register_subalias("4", m_2->m_Q[0]);
register_subalias("5", m_2->m_I[0]);
register_subalias("6", m_2->m_I[1]);
register_subalias("8", m_3->m_I[0]);
register_subalias("9", m_3->m_I[1]);
register_subalias("10", m_3->m_Q[0]);
register_subalias("11", m_4->m_I[0]);
register_subalias("12", m_4->m_I[1]);
register_subalias("13", m_4->m_Q[0]);
}
NETLIB_UPDATE(7402_dip)
{
/* only called during startup */
m_1->update_dev();
m_2->update_dev();
m_3->update_dev();
m_4->update_dev();
}
NETLIB_RESET(7402_dip)
{
m_1->do_reset();
m_2->do_reset();
m_3->do_reset();
m_4->do_reset();
}
NETLIB_NAMESPACE_DEVICES_END()

65
src/lib/netlist/devices/nld_7402.h
View File

@ -1,65 +0,0 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_7402.h
*
* DM7402: Quad 2-Input NOR Gates
*
* +--------------+
* Y1 |1 ++ 14| VCC
* A1 |2 13| Y4
* B1 |3 12| B4
* Y2 |4 7402 11| A4
* A2 |5 10| Y3
* B2 |6 9| B3
* GND |7 8| A3
* +--------------+
* ___
* Y = A+B
* +---+---++---+
* | A | B || Y |
* +===+===++===+
* | 0 | 0 || 1 |
* | 0 | 1 || 0 |
* | 1 | 0 || 0 |
* | 1 | 1 || 0 |
* +---+---++---+
*
* Naming conventions follow National Semiconductor datasheet
*
*/
#ifndef NLD_7402_H_
#define NLD_7402_H_
#include "nld_signal.h"
#include "nld_truthtable.h"
#define TTL_7402_NOR(_name, _I1, _I2) \
NET_REGISTER_DEV(TTL_7402_NOR, _name) \
NET_CONNECT(_name, A, _I1) \
NET_CONNECT(_name, B, _I2)
#define TTL_7402_DIP(_name) \
NET_REGISTER_DEV(TTL_7402_DIP, _name)
NETLIB_NAMESPACE_DEVICES_START()
#if (USE_TRUTHTABLE)
NETLIB_TRUTHTABLE(7402, 2, 1, 0);
#else
NETLIB_SIGNAL(7402, 2, 1, 0);
#endif
NETLIB_DEVICE(7402_dip,
NETLIB_SUB(7402) m_1;
NETLIB_SUB(7402) m_2;
NETLIB_SUB(7402) m_3;
NETLIB_SUB(7402) m_4;
);
NETLIB_NAMESPACE_DEVICES_END()
#endif /* NLD_7402_H_ */

65
src/lib/netlist/devices/nld_7408.cpp
View File

@ -1,65 +0,0 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_7408.c
*
*/
#include "nld_7408.h"
NETLIB_NAMESPACE_DEVICES_START()
#if (USE_TRUTHTABLE)
nld_7408::truthtable_t nld_7408::m_ttbl;
const char *nld_7408::m_desc[] = {
"A , B | Q ",
"X,0|0|15",
"0,X|0|15",
"1,1|1|22",
""
};
#endif
NETLIB_START(7408_dip)
{
register_sub("1", m_1);
register_sub("2", m_2);
register_sub("3", m_3);
register_sub("4", m_4);
register_subalias("1", m_1->m_I[0]);
register_subalias("2", m_1->m_I[1]);
register_subalias("3", m_1->m_Q[0]);
register_subalias("4", m_2->m_I[0]);
register_subalias("5", m_2->m_I[1]);
register_subalias("6", m_2->m_Q[0]);
register_subalias("9", m_3->m_I[0]);
register_subalias("10", m_3->m_I[1]);
register_subalias("8", m_3->m_Q[0]);
register_subalias("12", m_4->m_I[0]);
register_subalias("13", m_4->m_I[1]);
register_subalias("11", m_4->m_Q[0]);
}
NETLIB_UPDATE(7408_dip)
{
/* only called during startup */
m_1->update_dev();
m_2->update_dev();
m_3->update_dev();
m_4->update_dev();
}
NETLIB_RESET(7408_dip)
{
m_1->do_reset();
m_2->do_reset();
m_3->do_reset();
m_4->do_reset();
}
NETLIB_NAMESPACE_DEVICES_END()

65
src/lib/netlist/devices/nld_7408.h
View File

@ -1,65 +0,0 @@
// license:GPL-2.0+
// copyright-holders:Couriersud
/*
* nld_7408.h
*
* DM7408: Quad 2-Input AND Gates
*
* +--------------+
* A1 |1 ++ 14| VCC
* B1 |2 13| B4
* Y1 |3 12| A4
* A2 |4 7408 11| Y4
* B2 |5 10| B3
* Y2 |6 9| A3
* GND |7 8| Y3
* +--------------+
* __
* Y = AB
* +---+---++---+
* | A | B || Y |
* +===+===++===+
* | 0 | 0 || 0 |
* | 0 | 1 || 0 |
* | 1 | 0 || 0 |
* | 1 | 1 || 1 |
* +---+---++---+
*
* Naming conventions follow Fairchild Semiconductor datasheet
*
*/
#ifndef NLD_7408_H_
#define NLD_7408_H_
#include "nld_signal.h"
#include "nld_truthtable.h"
#define TTL_7408_AND(_name, _A, _B) \
NET_REGISTER_DEV(TTL_7408_AND, _name) \
NET_CONNECT(_name, A, _A) \
NET_CONNECT(_name, B, _B)
#define TTL_7408_DIP(_name) \
NET_REGISTER_DEV(TTL_7408_DIP, _name)
NETLIB_NAMESPACE_DEVICES_START()
#if (USE_TRUTHTABLE)
NETLIB_TRUTHTABLE(7408, 2, 1, 0);
#else
NETLIB_SIGNAL(7408, 2, 0, 1);
#endif
NETLIB_DEVICE(7408_dip,
NETLIB_SUB(7408) m_1;
NETLIB_SUB(7408) m_2;
NETLIB_SUB(7408) m_3;
NETLIB_SUB(7408) m_4;
);
NETLIB_NAMESPACE_DEVICES_END()
#endif /* NLD_7408_H_ */

2
src/lib/netlist/devices/nld_7427.cpp
View File

@ -7,8 +7,6 @@
#include "nld_7427.h"
#include "nld_7402.h"
NETLIB_NAMESPACE_DEVICES_START()
#if (USE_TRUTHTABLE)

111
src/lib/netlist/macro/nlm_ttl74xx.cpp
View File

@ -45,6 +45,44 @@ NETLIST_START(TTL_7400_DIP)
)
NETLIST_END()
/*
* DM7402: Quad 2-Input NOR Gates
*
* Y = A+B
* +---+---++---+
* | A | B || Y |
* +===+===++===+
* | 0 | 0 || 1 |
* | 0 | 1 || 0 |
* | 1 | 0 || 0 |
* | 1 | 1 || 0 |
* +---+---++---+
*
* Naming conventions follow National Semiconductor datasheet
*
*/
NETLIST_START(TTL_7402_DIP)
TTL_7402_GATE(s1)
TTL_7402_GATE(s2)
TTL_7402_GATE(s3)
TTL_7402_GATE(s4)
DUMMY_INPUT(GND)
DUMMY_INPUT(VCC)
DIPPINS( /* +--------------+ */
s1.Q, /* Y1 |1 ++ 14| VCC */ VCC.I,
s1.A, /* A1 |2 13| Y4 */ s4.Q,
s1.B, /* B1 |3 12| B4 */ s4.B,
s2.Q, /* Y2 |4 7402 11| A4 */ s4.A,
s2.A, /* A2 |5 10| Y3 */ s3.Q,
s2.B, /* B2 |6 9| B3 */ s3.B,
GND.I, /* GND |7 8| A3 */ s3.A
/* +--------------+ */
)
NETLIST_END()
/*
* DM7404: Hex Inverting Gates
* _
@ -83,6 +121,45 @@ NETLIST_START(TTL_7404_DIP)
)
NETLIST_END()
/*
* DM7408: Quad 2-Input AND Gates
*
*
* Y = AB
* +---+---++---+
* | A | B || Y |
* +===+===++===+
* | 0 | 0 || 0 |
* | 0 | 1 || 0 |
* | 1 | 0 || 0 |
* | 1 | 1 || 1 |
* +---+---++---+
*
* Naming conventions follow National Semiconductor datasheet
*
*/
NETLIST_START(TTL_7408_DIP)
TTL_7408_GATE(s1)
TTL_7408_GATE(s2)
TTL_7408_GATE(s3)
TTL_7408_GATE(s4)
DUMMY_INPUT(GND)
DUMMY_INPUT(VCC)
DIPPINS( /* +--------------+ */
s1.A, /* A1 |1 ++ 14| VCC */ VCC.I,
s1.B, /* B1 |2 13| B4 */ s4.B,
s1.Q, /* Y1 |3 12| A4 */ s4.A,
s2.A, /* A2 |4 7400 11| Y4 */ s4.Q,
s2.B, /* B2 |5 10| B3 */ s3.B,
s2.Q, /* Y2 |6 9| A3 */ s3.A,
GND.I, /* GND |7 8| Y3 */ s3.Q
/* +--------------+ */
)
NETLIST_END()
/*
* DM7416: Hex Inverting Buffers with
* High Voltage Open-Collector Outputs
@ -130,6 +207,22 @@ NETLIST_START(TTL74XX_lib)
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7402_GATE, 2, 1, 0, "")
TT_HEAD("A,B|Q ")
TT_LINE("0,0|1|22")
TT_LINE("X,1|0|15")
TT_LINE("1,X|0|15")
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7402_NOR, 2, 1, 0, "A,B")
TT_HEAD("A,B|Q ")
TT_LINE("0,0|1|22")
TT_LINE("X,1|0|15")
TT_LINE("1,X|0|15")
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7404_GATE, 1, 1, 0, "")
TT_HEAD(" A | Q ")
TT_LINE(" 0 | 1 |22")
@ -144,6 +237,22 @@ NETLIST_START(TTL74XX_lib)
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7408_GATE, 2, 1, 0, "")
TT_HEAD("A,B|Q ")
TT_LINE("0,X|0|15")
TT_LINE("X,0|0|15")
TT_LINE("1,1|1|22")
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7408_AND, 2, 1, 0, "A,B")
TT_HEAD("A,B|Q ")
TT_LINE("0,X|0|15")
TT_LINE("X,0|0|15")
TT_LINE("1,1|1|22")
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7416_GATE, 1, 1, 0, "")
TT_HEAD(" A | Q ")
TT_LINE(" 0 | 1 |15")
@ -153,6 +262,8 @@ NETLIST_START(TTL74XX_lib)
TRUTHTABLE_END()
LOCAL_LIB_ENTRY(TTL_7400_DIP)
LOCAL_LIB_ENTRY(TTL_7402_DIP)
LOCAL_LIB_ENTRY(TTL_7404_DIP)
LOCAL_LIB_ENTRY(TTL_7408_DIP)
LOCAL_LIB_ENTRY(TTL_7416_DIP)
NETLIST_END()

24
src/lib/netlist/macro/nlm_ttl74xx.h
View File

@ -23,6 +23,18 @@
NET_REGISTER_DEV(TTL_7400_DIP, _name)
#define TTL_7402_GATE(_name) \
NET_REGISTER_DEV(TTL_7402_GATE, _name)
#define TTL_7402_NOR(_name, _I1, _I2) \
NET_REGISTER_DEV(TTL_7402_NOR, _name) \
NET_CONNECT(_name, A, _I1) \
NET_CONNECT(_name, B, _I2)
#define TTL_7402_DIP(_name) \
NET_REGISTER_DEV(TTL_7402_DIP, _name)
#define TTL_7404_GATE(_name) \
NET_REGISTER_DEV(TTL_7404_GATE, _name)
@ -34,6 +46,18 @@
NET_REGISTER_DEV(TTL_7404_DIP, _name)
#define TTL_7408_GATE(_name) \
NET_REGISTER_DEV(TTL_7408_GATE, _name)
#define TTL_7408_NAND(_name, _A, _B) \
NET_REGISTER_DEV(TTL_7408_NAND, _name) \
NET_CONNECT(_name, A, _A) \
NET_CONNECT(_name, B, _B)
#define TTL_7408_DIP(_name) \
NET_REGISTER_DEV(TTL_7408_DIP, _name)
#define TTL_7416_GATE(_name) \
NET_REGISTER_DEV(TTL_7416_GATE, _name)