mirror of
https://github.com/holub/mame
synced 2025-04-25 17:56:43 +03:00
Fixed clipping of device address maps if the size of the map caused the end address to wrap. Added a proof of concept implementation of a address map bank device, which allows you to bank memory maps. Hooked it up to Taito GNET as an example [smf]
This commit is contained in:
smf-
parent
84ffcf912b
commit
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2
.gitattributes
vendored
2
.gitattributes
vendored
@ -1191,6 +1191,8 @@ src/emu/machine/at45dbxx.c svneol=native#text/plain
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src/emu/machine/at45dbxx.h svneol=native#text/plain
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src/emu/machine/ay31015.c svneol=native#text/plain
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src/emu/machine/ay31015.h svneol=native#text/plain
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src/emu/machine/bankdev.c svneol=native#text/plain
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src/emu/machine/bankdev.h svneol=native#text/plain
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src/emu/machine/cdp1852.c svneol=native#text/plain
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src/emu/machine/cdp1852.h svneol=native#text/plain
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src/emu/machine/cdp1871.c svneol=native#text/plain
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@ -790,7 +790,7 @@ void address_map::uplift_submaps(running_machine &machine, device_t &device, dev
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subentry->m_addrend = entry->m_addrstart + (end_offset / slot_count) * databytes + databytes - 1;
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// Clip the entry to the end of the range
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if (subentry->m_addrend > entry->m_addrend)
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if (subentry->m_addrend > entry->m_addrend || subentry->m_addrend < entry->m_addrstart)
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subentry->m_addrend = entry->m_addrend;
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// Detect special unhandled case (range straddling
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@ -173,6 +173,7 @@ EMUMACHINEOBJS = \
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$(EMUMACHINE)/at29040a.o \
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$(EMUMACHINE)/at45dbxx.o \
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$(EMUMACHINE)/ay31015.o \
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$(EMUMACHINE)/bankdev.o \
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$(EMUMACHINE)/cdp1852.o \
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$(EMUMACHINE)/cdp1871.o \
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$(EMUMACHINE)/com8116.o \
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93
src/emu/machine/bankdev.c
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93
src/emu/machine/bankdev.c
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@ -0,0 +1,93 @@
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#include "bankdev.h"
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// device type definition
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const device_type ADDRESS_MAP_BANK = &device_creator<address_map_bank_device>;
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address_map_bank_device::address_map_bank_device( const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock )
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: device_t(mconfig, ADDRESS_MAP_BANK, "Address Map Bank", tag, owner, clock),
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device_memory_interface(mconfig, *this),
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m_endianness(ENDIANNESS_NATIVE),
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m_databus_width(0),
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m_addrbus_width(32),
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m_stride(1),
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m_offset(0)
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{
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}
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DEVICE_ADDRESS_MAP_START(amap8, 8, address_map_bank_device)
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AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE(read8, write8)
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ADDRESS_MAP_END
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DEVICE_ADDRESS_MAP_START(amap16, 16, address_map_bank_device)
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AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE(read16, write16) /// TODO: fix memory.c bug that ignores the upper limit on the AM_DEVICE
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ADDRESS_MAP_END
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DEVICE_ADDRESS_MAP_START(amap32, 32, address_map_bank_device)
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AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE(read32, write32)
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ADDRESS_MAP_END
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DEVICE_ADDRESS_MAP_START(amap64, 64, address_map_bank_device)
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AM_RANGE(0x00000000, 0xffffffff) AM_READWRITE(read64, write64)
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ADDRESS_MAP_END
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WRITE8_MEMBER(address_map_bank_device::write8)
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{
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m_program->write_byte(m_offset + offset, data);
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}
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WRITE16_MEMBER(address_map_bank_device::write16)
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{
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m_program->write_word(m_offset + (offset * 2), data, mem_mask);
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}
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WRITE32_MEMBER(address_map_bank_device::write32)
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{
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m_program->write_dword(m_offset + (offset * 4), data, mem_mask);
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}
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WRITE64_MEMBER(address_map_bank_device::write64)
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{
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m_program->write_qword(m_offset + (offset * 8), data, mem_mask);
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}
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READ8_MEMBER(address_map_bank_device::read8)
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{
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return m_program->read_byte(m_offset + offset);
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}
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READ16_MEMBER(address_map_bank_device::read16)
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{
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return m_program->read_word(m_offset + (offset * 2), mem_mask);
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}
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READ32_MEMBER(address_map_bank_device::read32)
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{
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return m_program->read_dword(m_offset + (offset * 4), mem_mask);
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}
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READ64_MEMBER(address_map_bank_device::read64)
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{
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return m_program->read_qword(m_offset + (offset * 8), mem_mask);
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}
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void address_map_bank_device::device_config_complete()
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{
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m_program_config = address_space_config( "program", m_endianness, m_databus_width, m_addrbus_width );
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}
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void address_map_bank_device::device_start()
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{
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m_program = &space(AS_PROGRAM);
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save_item(NAME(m_offset));
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}
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void address_map_bank_device::device_reset()
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{
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m_offset = 0;
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}
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void address_map_bank_device::set_bank(offs_t bank)
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{
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m_offset = bank * m_stride;
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}
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67
src/emu/machine/bankdev.h
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67
src/emu/machine/bankdev.h
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@ -0,0 +1,67 @@
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#include "emu.h"
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#define MCFG_ADDRESS_MAP_BANK_ENDIANNESS(_endianness) \
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address_map_bank_device::set_endianness(*device, _endianness);
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#define MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(_databus_width) \
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address_map_bank_device::set_databus_width(*device, _databus_width);
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#define MCFG_ADDRESS_MAP_BANK_ADDRBUS_WIDTH(_addrbus_width) \
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address_map_bank_device::set_addrbus_width(*device, _addrbus_width);
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#define MCFG_ADDRESS_MAP_BANK_STRIDE(_stride) \
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address_map_bank_device::set_stride(*device, _stride);
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class address_map_bank_device :
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public device_t,
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public device_memory_interface
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{
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public:
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// construction/destruction
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address_map_bank_device( const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock );
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// static configuration helpers
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static void set_endianness(device_t &device, endianness_t endianness) { downcast<address_map_bank_device &>(device).m_endianness = endianness; }
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static void set_databus_width(device_t &device, UINT8 databus_width) { downcast<address_map_bank_device &>(device).m_databus_width = databus_width; }
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static void set_addrbus_width(device_t &device, UINT8 addrbus_width) { downcast<address_map_bank_device &>(device).m_addrbus_width = addrbus_width; }
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static void set_stride(device_t &device, UINT32 stride) { downcast<address_map_bank_device &>(device).m_stride = stride; }
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DECLARE_ADDRESS_MAP(amap8, 8);
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DECLARE_ADDRESS_MAP(amap16, 16);
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DECLARE_ADDRESS_MAP(amap32, 32);
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DECLARE_ADDRESS_MAP(amap64, 64);
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DECLARE_WRITE8_MEMBER(write8);
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DECLARE_WRITE16_MEMBER(write16);
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DECLARE_WRITE32_MEMBER(write32);
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DECLARE_WRITE64_MEMBER(write64);
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DECLARE_READ8_MEMBER(read8);
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DECLARE_READ16_MEMBER(read16);
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DECLARE_READ32_MEMBER(read32);
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DECLARE_READ64_MEMBER(read64);
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void set_bank(offs_t offset);
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protected:
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virtual void device_start();
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virtual void device_config_complete();
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virtual void device_reset();
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// device_memory_interface overrides
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virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
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private:
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// internal state
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endianness_t m_endianness;
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UINT8 m_databus_width;
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UINT8 m_addrbus_width;
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UINT32 m_stride;
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address_space_config m_program_config;
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address_space *m_program;
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offs_t m_offset;
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};
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// device type definition
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extern const device_type ADDRESS_MAP_BANK;
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@ -325,6 +325,7 @@ Type 3 (PCMCIA Compact Flash Adaptor + Compact Flash card, sealed together with
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#include "machine/znsec.h"
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#include "machine/zndip.h"
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#include "machine/idectrl.h"
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#include "machine/bankdev.h"
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#include "machine/mb3773.h"
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#include "sound/spu.h"
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#include "audio/taito_zm.h"
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@ -339,18 +340,11 @@ public:
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m_zndip(*this,"maincpu:sio0:zndip"),
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m_card(*this,"card"),
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m_maincpu(*this, "maincpu"),
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m_mn10200(*this, "mn10200") {
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m_mn10200(*this, "mn10200"),
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m_flashbank(*this, "flashbank")
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{
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}
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required_device<znsec_device> m_znsec0;
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required_device<znsec_device> m_znsec1;
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required_device<zndip_device> m_zndip;
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required_device<ide_controller_device> m_card;
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intel_te28f160_device *m_biosflash;
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intel_e28f400_device *m_pgmflash;
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intel_te28f160_device *m_sndflash[3];
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unsigned char m_cis[512];
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int m_locked;
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@ -388,9 +382,14 @@ public:
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DECLARE_MACHINE_RESET(coh3002t);
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void rf5c296_reg_w(ATTR_UNUSED UINT8 reg, UINT8 data);
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UINT8 rf5c296_reg_r(ATTR_UNUSED UINT8 reg);
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void install_handlers(int mode);
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required_device<znsec_device> m_znsec0;
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required_device<znsec_device> m_znsec1;
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required_device<zndip_device> m_zndip;
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required_device<ide_controller_device> m_card;
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required_device<cpu_device> m_maincpu;
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required_device<cpu_device> m_mn10200;
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required_device<address_map_bank_device> m_flashbank;
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};
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@ -496,24 +495,6 @@ WRITE16_MEMBER(taitogn_state::rf5c296_mem_w)
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}
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}
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void taitogn_state::install_handlers(int mode)
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{
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address_space &a = m_maincpu->space(AS_PROGRAM);
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if(mode == 0) {
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// Mode 0 has access to the subbios, the mn102 flash and the rf5c296 mem zone
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a.install_readwrite_handler(0x1f000000, 0x1f1fffff, read16_delegate(FUNC(intelfsh16_device::read),m_biosflash), write16_delegate(FUNC(intel_te28f160_device::write),m_biosflash), 0xffffffff);
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a.install_readwrite_handler(0x1f200000, 0x1f2fffff, read16_delegate(FUNC(taitogn_state::rf5c296_mem_r),this), write16_delegate(FUNC(taitogn_state::rf5c296_mem_w),this), 0xffffffff);
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a.install_readwrite_handler(0x1f300000, 0x1f37ffff, read16_delegate(FUNC(intelfsh16_device::read),m_pgmflash), write16_delegate(FUNC(intelfsh16_device::write),m_pgmflash), 0xffffffff);
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a.nop_readwrite(0x1f380000, 0x1f5fffff);
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} else {
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// Mode 1 has access to the 3 samples flashes
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a.install_readwrite_handler(0x1f000000, 0x1f1fffff, read16_delegate(FUNC(intelfsh16_device::read),m_sndflash[0]), write16_delegate(FUNC(intelfsh16_device::write),m_sndflash[0]), 0xffffffff);
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a.install_readwrite_handler(0x1f200000, 0x1f3fffff, read16_delegate(FUNC(intelfsh16_device::read),m_sndflash[1]), write16_delegate(FUNC(intelfsh16_device::write),m_sndflash[1]), 0xffffffff);
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a.install_readwrite_handler(0x1f400000, 0x1f5fffff, read16_delegate(FUNC(intelfsh16_device::read),m_sndflash[2]), write16_delegate(FUNC(intelfsh16_device::write),m_sndflash[2]), 0xffffffff);
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}
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}
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// Misc. controls
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READ8_MEMBER(taitogn_state::control_r)
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@ -551,7 +532,7 @@ WRITE8_MEMBER(taitogn_state::control_w)
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#endif
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if((p ^ m_control) & 0x04)
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install_handlers(m_control & 4 ? 1 : 0);
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m_flashbank->set_bank(m_control & 4 ? 1 : 0);
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}
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WRITE16_MEMBER(taitogn_state::control2_w)
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@ -684,12 +665,6 @@ READ8_MEMBER(taitogn_state::gnet_mahjong_panel_r)
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DRIVER_INIT_MEMBER(taitogn_state,coh3002t)
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{
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m_biosflash = machine().device<intel_te28f160_device>("biosflash");
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m_pgmflash = machine().device<intel_e28f400_device>("pgmflash");
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m_sndflash[0] = machine().device<intel_te28f160_device>("sndflash0");
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m_sndflash[1] = machine().device<intel_te28f160_device>("sndflash1");
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m_sndflash[2] = machine().device<intel_te28f160_device>("sndflash2");
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m_znsec0->init(tt10);
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m_znsec1->init(tt16);
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@ -708,7 +683,6 @@ DRIVER_INIT_MEMBER(taitogn_state,coh3002t_mp)
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MACHINE_RESET_MEMBER(taitogn_state,coh3002t)
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{
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m_locked = 0x1ff;
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install_handlers(0);
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m_control = 0;
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m_card->reset();
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@ -719,9 +693,7 @@ MACHINE_RESET_MEMBER(taitogn_state,coh3002t)
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}
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static ADDRESS_MAP_START( taitogn_map, AS_PROGRAM, 32, taitogn_state )
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// AM_RANGE(0x1f000000, 0x1f1fffff) AM_DEVREADWRITE16("sndflash0", intelfsh16_device, read, write, 0xffffffff)
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// AM_RANGE(0x1f200000, 0x1f3fffff) AM_DEVREADWRITE16("sndflash1", intelfsh16_device, read, write, 0xffffffff)
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// AM_RANGE(0x1f400000, 0x1f5fffff) AM_DEVREADWRITE16("sndflash2", intelfsh16_device, read, write, 0xffffffff)
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AM_RANGE(0x1f000000, 0x1f7fffff) AM_DEVICE16("flashbank", address_map_bank_device, amap16, 0xffffffff)
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AM_RANGE(0x1fa00000, 0x1fa00003) AM_READ_PORT("P1")
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AM_RANGE(0x1fa00100, 0x1fa00103) AM_READ_PORT("P2")
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AM_RANGE(0x1fa00200, 0x1fa00203) AM_READ_PORT("SERVICE")
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@ -742,6 +714,18 @@ static ADDRESS_MAP_START( taitogn_map, AS_PROGRAM, 32, taitogn_state )
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AM_RANGE(0x1fbe0000, 0x1fbe01ff) AM_RAM // 256 bytes com zone with the mn102, low bytes of words only, with additional comm at 1fb80000
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( flashbank_map, AS_PROGRAM, 16, taitogn_state )
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// Bank 0 has access to the subbios, the mn102 flash and the rf5c296 mem zone
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AM_RANGE(0x00000000, 0x001fffff) AM_DEVREADWRITE("biosflash", intelfsh16_device, read, write)
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AM_RANGE(0x00200000, 0x002fffff) AM_READWRITE( rf5c296_mem_r, rf5c296_mem_w )
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AM_RANGE(0x00300000, 0x0037ffff) AM_DEVREADWRITE("pgmflash", intelfsh16_device, read, write)
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// Bank 1 has access to the 3 samples flashes
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AM_RANGE(0x08000000, 0x081fffff) AM_DEVREADWRITE("sndflash0", intelfsh16_device, read, write)
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AM_RANGE(0x08200000, 0x083fffff) AM_DEVREADWRITE("sndflash1", intelfsh16_device, read, write)
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AM_RANGE(0x08400000, 0x085fffff) AM_DEVREADWRITE("sndflash2", intelfsh16_device, read, write)
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ADDRESS_MAP_END
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static MACHINE_CONFIG_START( coh3002t, taitogn_state )
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/* basic machine hardware */
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@ -773,6 +757,12 @@ static MACHINE_CONFIG_START( coh3002t, taitogn_state )
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MCFG_MB3773_ADD("mb3773")
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MCFG_DEVICE_ADD("flashbank", ADDRESS_MAP_BANK, 0)
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MCFG_DEVICE_PROGRAM_MAP(flashbank_map)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
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MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(16)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000000)
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MCFG_INTEL_TE28F160_ADD("biosflash")
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MCFG_INTEL_E28F400_ADD("pgmflash")
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MCFG_INTEL_TE28F160_ADD("sndflash0")
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