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-dsp56k: Renamed relevant classes, files and namespaces to indicate that it is a DSP56156 core, not a DSP5600x core. [Ryan Holtz]

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This commit is contained in:
mooglyguy 2019-08-19 15:53:47 +02:00
parent 9372646200
commit 450a57568e
25 changed files with 2066 additions and 2066 deletions
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40
scripts/src/cpu.lua
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@ -1675,34 +1675,34 @@ if (CPUS["M680X0"]~=null or _OPTIONS["with-tools"]) then
end
--------------------------------------------------
-- Motorola/Freescale dsp56k
--@src/devices/cpu/dsp56k/dsp56k.h,CPUS["DSP56156"] = true
-- Motorola/Freescale DSP56156
--@src/devices/cpu/dsp56156/dsp56156.h,CPUS["DSP56156"] = true
--------------------------------------------------
if (CPUS["DSP56156"]~=null) then
files {
MAME_DIR .. "src/devices/cpu/dsp56k/dsp56k.cpp",
MAME_DIR .. "src/devices/cpu/dsp56k/dsp56k.h",
MAME_DIR .. "src/devices/cpu/dsp56k/dsp56mem.cpp",
MAME_DIR .. "src/devices/cpu/dsp56k/dsp56mem.h",
MAME_DIR .. "src/devices/cpu/dsp56k/dsp56pcu.cpp",
MAME_DIR .. "src/devices/cpu/dsp56k/dsp56pcu.h",
MAME_DIR .. "src/devices/cpu/dsp56k/dsp56def.h",
MAME_DIR .. "src/devices/cpu/dsp56k/dsp56ops.hxx",
MAME_DIR .. "src/devices/cpu/dsp56156/dsp56156.cpp",
MAME_DIR .. "src/devices/cpu/dsp56156/dsp56156.h",
MAME_DIR .. "src/devices/cpu/dsp56156/dsp56mem.cpp",
MAME_DIR .. "src/devices/cpu/dsp56156/dsp56mem.h",
MAME_DIR .. "src/devices/cpu/dsp56156/dsp56pcu.cpp",
MAME_DIR .. "src/devices/cpu/dsp56156/dsp56pcu.h",
MAME_DIR .. "src/devices/cpu/dsp56156/dsp56def.h",
MAME_DIR .. "src/devices/cpu/dsp56156/dsp56ops.hxx",
}
end
if (CPUS["DSP56156"]~=null or _OPTIONS["with-tools"]) then
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56k/dsp56dsm.cpp")
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56k/dsp56dsm.h")
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56k/opcode.cpp")
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56k/opcode.h")
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56k/inst.cpp")
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56k/inst.h")
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56k/pmove.cpp")
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56k/pmove.h")
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56k/tables.cpp")
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56k/tables.h")
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56156/dsp56dsm.cpp")
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56156/dsp56dsm.h")
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56156/opcode.cpp")
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56156/opcode.h")
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56156/inst.cpp")
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56156/inst.h")
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56156/pmove.cpp")
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56156/pmove.h")
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56156/tables.cpp")
table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/dsp56156/tables.h")
end
--------------------------------------------------

515
src/devices/cpu/dsp56156/dsp56156.cpp Normal file
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@ -0,0 +1,515 @@
// license:BSD-3-Clause
// copyright-holders:Andrew Gardner
/***************************************************************************
dsp56156.cpp
Core implementation for the portable DSP56156 emulator.
Written by Andrew Gardner
****************************************************************************
Note:
This CPU emulator is very much a work-in-progress.
DONE:
1: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
11, , , , , , ,18, , ,
TODO:
X 1-6 Explore CORE naming scheme.
- 1-9 paragraph 1 : memory access timings
- 1-9 Data ALU arithmetic operations generally use fractional two's complement arithmetic
(Unsigned numbers are only supported by the multiply and multiply-accumulate instruction)
- 1-9 For fractional arithmetic, the 31-bit product is added to the 40-bit contents of A or B. No pipeline!
- 1-10 Two types of rounding: convergent rounding and two's complement rounding. See status register bit R.
- 1-10 Logic unit is 16-bits wide and works on MSP portion of accum register
- 1-10 The AGU can implement three types of arithmetic: linear, modulo, and reverse carry.
- 1-12 "Two external interrupt pins!!!"
- 1-12 Take care of all interrupt priority (IPR) stuff!
- 1-19 Memory WAIT states
- 1-20 The timer's interesting!
- 1-21 Vectored exception requests on the Host Interface!
***************************************************************************/
#include "emu.h"
#include "dsp56156.h"
#include "dsp56dsm.h"
#include "opcode.h"
#include "debugger.h"
#include "dsp56def.h"
/***************************************************************************
COMPONENT FUNCTIONALITY
***************************************************************************/
/* 1-9 ALU */
// #include "dsp56alu.h"
/* 1-10 Address Generation Unit (AGU) */
// #include "dsp56agu.h"
/* 1-11 Program Control Unit (PCU) */
#include "dsp56pcu.h"
/* 5-1 Host Interface (HI) */
//#include "dsp56hi.h"
/* 4-8 Memory handlers for on-chip peripheral memory. */
#include "dsp56mem.h"
DEFINE_DEVICE_TYPE_NS(DSP56156, DSP_56156, dsp56156_device, "dsp56156", "Motorola DSP56156")
namespace DSP_56156 {
enum
{
// PCU
DSP56156_PC=1,
DSP56156_SR,
DSP56156_LC,
DSP56156_LA,
DSP56156_SP,
DSP56156_OMR,
// ALU
DSP56156_X, DSP56156_Y,
DSP56156_A, DSP56156_B,
// AGU
DSP56156_R0,DSP56156_R1,DSP56156_R2,DSP56156_R3,
DSP56156_N0,DSP56156_N1,DSP56156_N2,DSP56156_N3,
DSP56156_M0,DSP56156_M1,DSP56156_M2,DSP56156_M3,
DSP56156_TEMP,
DSP56156_STATUS,
// CPU STACK
DSP56156_ST0,
DSP56156_ST1,
DSP56156_ST2,
DSP56156_ST3,
DSP56156_ST4,
DSP56156_ST5,
DSP56156_ST6,
DSP56156_ST7,
DSP56156_ST8,
DSP56156_ST9,
DSP56156_ST10,
DSP56156_ST11,
DSP56156_ST12,
DSP56156_ST13,
DSP56156_ST14,
DSP56156_ST15
};
/****************************************************************************
* Internal Memory Maps
****************************************************************************/
void dsp56156_device::dsp56156_program_map(address_map &map)
{
map(0x0000, 0x07ff).ram().share("dsk56156_program_ram"); /* 1-5 */
// AM_RANGE(0x2f00,0x2fff) AM_ROM /* 1-5 PROM reserved memory. Is this the right spot for it? */
}
void dsp56156_device::dsp56156_x_data_map(address_map &map)
{
map(0x0000, 0x07ff).ram(); /* 1-5 */
map(0xffc0, 0xffff).rw(FUNC(dsp56156_device::peripheral_register_r), FUNC(dsp56156_device::peripheral_register_w)); /* 1-5 On-chip peripheral registers memory mapped in data space */
}
dsp56156_device::dsp56156_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: cpu_device(mconfig, DSP56156, tag, owner, clock)
, m_program_config("program", ENDIANNESS_LITTLE, 16, 16, -1, address_map_constructor(FUNC(dsp56156_device::dsp56156_program_map), this))
, m_data_config("data", ENDIANNESS_LITTLE, 16, 16, -1, address_map_constructor(FUNC(dsp56156_device::dsp56156_x_data_map), this))
, m_program_ram(*this, "dsk56156_program_ram")
{
}
device_memory_interface::space_config_vector dsp56156_device::memory_space_config() const
{
return space_config_vector {
std::make_pair(AS_PROGRAM, &m_program_config),
std::make_pair(AS_DATA, &m_data_config)
};
}
/***************************************************************************
MEMORY ACCESSORS
***************************************************************************/
#define ROPCODE(pc) cpustate->cache->read_word(pc)
/***************************************************************************
IRQ HANDLING
***************************************************************************/
void dsp56156_device::execute_set_input(int irqline, int state)
{
//logerror("DSP56156 set irq line %d %d\n", irqline, state);
switch(irqline)
{
case DSP56156_IRQ_MODA:
// TODO: 1-12 Get this triggering right
if (irqa_trigger(&m_core))
logerror("DSP56156 IRQA is set to fire on the \"Negative Edge\".\n");
if (state != CLEAR_LINE)
m_core.modA_state = true;
else
m_core.modA_state = false;
if (m_core.reset_state != true)
dsp56156_add_pending_interrupt(&m_core, "IRQA");
break;
case DSP56156_IRQ_MODB:
// TODO: 1-12 Get this triggering right
if (irqb_trigger(&m_core))
logerror("DSP56156 IRQB is set to fire on the \"Negative Edge\".\n");
if (state != CLEAR_LINE)
m_core.modB_state = true;
else
m_core.modB_state = false;
if (m_core.reset_state != true)
dsp56156_add_pending_interrupt(&m_core, "IRQB");
break;
case DSP56156_IRQ_MODC:
if (state != CLEAR_LINE)
m_core.modC_state = true;
else
m_core.modC_state = false;
// TODO : Set bus mode or whatever
break;
case DSP56156_IRQ_RESET:
if (state != CLEAR_LINE)
m_core.reset_state = true;
else
{
/* If it changes state from asserted to cleared. Call the reset function. */
if (m_core.reset_state == true)
device_reset();
m_core.reset_state = false;
}
// dsp56156_add_pending_interrupt("Hardware RESET");
break;
default:
logerror("DSP56156 setting some weird irq line : %d", irqline);
break;
}
/* If the reset line isn't asserted, service interrupts */
// TODO: Is it right to immediately service interrupts?
//if (cpustate->reset_state != true)
// pcu_service_interrupts();
}
/***************************************************************************
INITIALIZATION AND SHUTDOWN
***************************************************************************/
void dsp56156_device::agu_init()
{
/* save states - dsp56156_agu members */
save_item(NAME(m_core.AGU.r0));
save_item(NAME(m_core.AGU.r1));
save_item(NAME(m_core.AGU.r2));
save_item(NAME(m_core.AGU.r3));
save_item(NAME(m_core.AGU.n0));
save_item(NAME(m_core.AGU.n1));
save_item(NAME(m_core.AGU.n2));
save_item(NAME(m_core.AGU.n3));
save_item(NAME(m_core.AGU.m0));
save_item(NAME(m_core.AGU.m1));
save_item(NAME(m_core.AGU.m2));
save_item(NAME(m_core.AGU.m3));
save_item(NAME(m_core.AGU.temp));
}
void dsp56156_device::alu_init()
{
/* save states - dsp56156_alu members */
save_item(NAME(m_core.ALU.x));
save_item(NAME(m_core.ALU.y));
save_item(NAME(m_core.ALU.a));
save_item(NAME(m_core.ALU.b));
}
void dsp56156_device::device_start()
{
memset(&m_core, 0, sizeof(m_core));
m_core.device = this;
m_core.program_ram = m_program_ram;
/* Call specific module inits */
pcu_init(&m_core, this);
agu_init();
alu_init();
/* HACK - You're not in bootstrap mode upon bootup */
m_core.bootstrap_mode = BOOTSTRAP_OFF;
/* Clear the irq states */
m_core.modA_state = false;
m_core.modB_state = false;
m_core.modC_state = false;
m_core.reset_state = false;
/* save states - dsp56156_core members */
save_item(NAME(m_core.modA_state));
save_item(NAME(m_core.modB_state));
save_item(NAME(m_core.modC_state));
save_item(NAME(m_core.reset_state));
save_item(NAME(m_core.bootstrap_mode));
save_item(NAME(m_core.repFlag));
save_item(NAME(m_core.repAddr));
save_item(NAME(m_core.ppc));
save_item(NAME(m_core.op));
save_item(NAME(m_core.interrupt_cycles));
/* save states - dsp56156_host_interface members */
save_item(NAME(m_core.HI.icr));
save_item(NAME(m_core.HI.cvr));
save_item(NAME(m_core.HI.isr));
save_item(NAME(m_core.HI.ivr));
save_item(NAME(m_core.HI.trxh));
save_item(NAME(m_core.HI.trxl));
save_item(NAME(m_core.HI.bootstrap_offset));
save_item(NAME(m_core.peripheral_ram));
m_core.program = &space(AS_PROGRAM);
m_core.cache = m_core.program->cache<1, -1, ENDIANNESS_LITTLE>();
m_core.data = &space(AS_DATA);
state_add(DSP56156_PC, "PC", m_core.PCU.pc).formatstr("%04X");
state_add(DSP56156_SR, "SR", m_core.PCU.sr).formatstr("%04X");
state_add(DSP56156_LC, "LC", m_core.PCU.lc).formatstr("%04X");
state_add(DSP56156_LA, "LA", m_core.PCU.la).formatstr("%04X");
state_add(DSP56156_SP, "SP", m_core.PCU.sp).formatstr("%02X");
state_add(DSP56156_OMR, "OMR", m_core.PCU.omr).formatstr("%02X");
state_add(DSP56156_X, "X", m_core.ALU.x.d).mask(0xffffffff).formatstr("%9s");
state_add(DSP56156_Y, "Y", m_core.ALU.y.d).mask(0xffffffff).formatstr("%9s");
state_add(DSP56156_A, "A", m_core.ALU.a.q).mask(u64(0xffffffffffffffffU)).formatstr("%12s"); /* could benefit from a better mask? */
state_add(DSP56156_B, "B", m_core.ALU.b.q).mask(u64(0xffffffffffffffffU)).formatstr("%12s"); /* could benefit from a better mask? */
state_add(DSP56156_R0, "R0", m_core.AGU.r0).formatstr("%04X");
state_add(DSP56156_R1, "R1", m_core.AGU.r1).formatstr("%04X");
state_add(DSP56156_R2, "R2", m_core.AGU.r2).formatstr("%04X");
state_add(DSP56156_R3, "R3", m_core.AGU.r3).formatstr("%04X");
state_add(DSP56156_N0, "N0", m_core.AGU.n0).formatstr("%04X");
state_add(DSP56156_N1, "N1", m_core.AGU.n1).formatstr("%04X");
state_add(DSP56156_N2, "N2", m_core.AGU.n2).formatstr("%04X");
state_add(DSP56156_N3, "N3", m_core.AGU.n3).formatstr("%04X");
state_add(DSP56156_M0, "M0", m_core.AGU.m0).formatstr("%04X");
state_add(DSP56156_M1, "M1", m_core.AGU.m1).formatstr("%04X");
state_add(DSP56156_M2, "M2", m_core.AGU.m2).formatstr("%04X");
state_add(DSP56156_M3, "M3", m_core.AGU.m3).formatstr("%04X");
state_add(DSP56156_TEMP, "TMP", m_core.AGU.temp).formatstr("%04X").noshow();
//state_add(DSP56156_STATUS, "STS", STATUS).formatstr("%02X");
state_add(DSP56156_ST0, "ST0", m_core.PCU.ss[0].d).formatstr("%08X");
state_add(DSP56156_ST1, "ST1", m_core.PCU.ss[1].d).formatstr("%08X");
state_add(DSP56156_ST2, "ST2", m_core.PCU.ss[2].d).formatstr("%08X");
state_add(DSP56156_ST3, "ST3", m_core.PCU.ss[3].d).formatstr("%08X");
state_add(DSP56156_ST4, "ST4", m_core.PCU.ss[4].d).formatstr("%08X");
state_add(DSP56156_ST5, "ST5", m_core.PCU.ss[5].d).formatstr("%08X");
state_add(DSP56156_ST6, "ST6", m_core.PCU.ss[6].d).formatstr("%08X");
state_add(DSP56156_ST7, "ST7", m_core.PCU.ss[7].d).formatstr("%08X");
state_add(DSP56156_ST8, "ST8", m_core.PCU.ss[8].d).formatstr("%08X");
state_add(DSP56156_ST9, "ST9", m_core.PCU.ss[9].d).formatstr("%08X");
state_add(DSP56156_ST10, "ST10", m_core.PCU.ss[10].d).formatstr("%08X");
state_add(DSP56156_ST11, "ST11", m_core.PCU.ss[11].d).formatstr("%08X");
state_add(DSP56156_ST12, "ST12", m_core.PCU.ss[12].d).formatstr("%08X");
state_add(DSP56156_ST13, "ST13", m_core.PCU.ss[13].d).formatstr("%08X");
state_add(DSP56156_ST14, "ST14", m_core.PCU.ss[14].d).formatstr("%08X");
state_add(DSP56156_ST15, "ST15", m_core.PCU.ss[15].d).formatstr("%08X");
state_add(STATE_GENPC, "GENPC", m_core.PCU.pc).noshow();
state_add(STATE_GENPCBASE, "CURPC", m_core.ppc).noshow();
state_add(STATE_GENSP, "GENSP", m_core.PCU.sp).noshow();
state_add(STATE_GENFLAGS, "GENFLAGS", m_core.PCU.sr).formatstr("%14s").noshow();
set_icountptr(m_core.icount);
}
void dsp56156_device::state_string_export(const device_state_entry &entry, std::string &str) const
{
const dsp56156_core *cpustate = &m_core;
switch (entry.index())
{
case STATE_GENFLAGS:
str = string_format("%s%s %s%s%s%s%s%s%s%s %s%s",
/* Status Register */
LF_bit(cpustate) ? "L" : ".",
FV_bit(cpustate) ? "F" : ".",
S_bit(cpustate) ? "S" : ".",
L_bit(cpustate) ? "L" : ".",
E_bit(cpustate) ? "E" : ".",
U_bit(cpustate) ? "U" : ".",
N_bit(cpustate) ? "N" : ".",
Z_bit(cpustate) ? "Z" : ".",
V_bit(cpustate) ? "V" : ".",
C_bit(cpustate) ? "C" : ".",
/* Stack Pointer */
UF_bit(cpustate) ? "U" : ".",
SE_bit(cpustate) ? "S" : ".");
break;
case DSP56156_X:
str = string_format("%04x %04x", X1, X0);
break;
case DSP56156_Y:
str = string_format("%04x %04x", Y1, Y0);
break;
case DSP56156_A:
str = string_format("%02x %04x %04x", A2, A1, A0);
break;
case DSP56156_B:
str = string_format("%02x %04x %04x", B2, B1, B0);
break;
}
}
/***************************************************************************
RESET BEHAVIOR
***************************************************************************/
static void agu_reset(dsp56156_core* cpustate)
{
/* FM.4-3 */
R0 = 0x0000;
R1 = 0x0000;
R2 = 0x0000;
R3 = 0x0000;
N0 = 0x0000;
N1 = 0x0000;
N2 = 0x0000;
N3 = 0x0000;
M0 = 0xffff;
M1 = 0xffff;
M2 = 0xffff;
M3 = 0xffff;
TEMP = 0x0000;
}
static void alu_reset(dsp56156_core* cpustate)
{
X = 0x00000000;
Y = 0x00000000;
A = 0x0000000000;
B = 0x0000000000;
}
void dsp56156_device::device_reset()
{
logerror("DSP56156 reset\n");
m_core.interrupt_cycles = 0;
m_core.repFlag = 0;
m_core.repAddr = 0x0000;
pcu_reset(&m_core);
mem_reset(&m_core);
agu_reset(&m_core);
alu_reset(&m_core);
m_core.ppc = m_core.PCU.pc;
/* HACK - Put a jump to 0x0000 at 0x0000 - this keeps the CPU locked to the instruction at address 0x0000 */
m_core.program->write_word(0x0000, 0x0124);
}
/***************************************************************************
CORE INCLUDE
***************************************************************************/
#include "dsp56ops.hxx"
/***************************************************************************
CORE EXECUTION LOOP
***************************************************************************/
// Execute a single opcode and return how many cycles it took.
static size_t execute_one_new(dsp56156_core* cpustate)
{
// For MAME
cpustate->ppc = PC;
if (cpustate->device->machine().debug_flags & DEBUG_FLAG_CALL_HOOK) // FIXME: if this was a member, the helper would work
cpustate->device->debug()->instruction_hook(PC);
cpustate->op = ROPCODE(PC);
uint16_t w0 = ROPCODE(PC);
uint16_t w1 = ROPCODE(PC + 1);
Opcode op(w0, w1);
op.evaluate(cpustate);
PC += op.evalSize(); // Special size function needed to handle jmps, etc.
// TODO: Currently all operations take up 4 cycles (inst->cycles()).
return 4;
}
void dsp56156_device::execute_run()
{
/* If reset line is asserted, do nothing */
if (m_core.reset_state)
{
m_core.icount = 0;
return;
}
/* HACK - if you're in bootstrap mode, simply pretend you ate up all your cycles waiting for data. */
if (m_core.bootstrap_mode != BOOTSTRAP_OFF)
{
m_core.icount = 0;
return;
}
//m_core.icount -= m_core.interrupt_cycles;
//m_core.interrupt_cycles = 0;
while(m_core.icount > 0)
{
execute_one(&m_core);
if (0) m_core.icount -= execute_one_new(&m_core);
pcu_service_interrupts(&m_core); // TODO: Is it incorrect to service after each instruction?
}
}
std::unique_ptr<util::disasm_interface> dsp56156_device::create_disassembler()
{
return std::make_unique<dsp56156_disassembler>();
}
} // namespace DSP_56156

58
src/devices/cpu/dsp56k/dsp56k.h → src/devices/cpu/dsp56156/dsp56156.h
View File

@ -2,15 +2,15 @@
// copyright-holders:Andrew Gardner
/***************************************************************************
dsp56k.h
Interface file for the portable Motorola/Freescale DSP56k emulator.
dsp56156.h
Interface file for the portable Motorola/Freescale DSP56156 emulator.
Written by Andrew Gardner
***************************************************************************/
#ifndef MAME_CPU_DSP56K_DSP56K_H
#define MAME_CPU_DSP56K_DSP56K_H
#ifndef MAME_CPU_DSP56156_DSP56156_H
#define MAME_CPU_DSP56156_DSP56156_H
#pragma once
@ -18,21 +18,21 @@
// IRQ Lines
// MODA and MODB are also known as IRQA and IRQB
#define DSP56K_IRQ_MODA 0
#define DSP56K_IRQ_MODB 1
#define DSP56K_IRQ_MODC 2
#define DSP56K_IRQ_RESET 3 /* Is this needed? */
#define DSP56156_IRQ_MODA 0
#define DSP56156_IRQ_MODB 1
#define DSP56156_IRQ_MODC 2
#define DSP56156_IRQ_RESET 3 /* Is this needed? */
namespace DSP56K {
namespace DSP_56156 {
/***************************************************************************
STRUCTURES & TYPEDEFS
***************************************************************************/
// 5-4 Host Interface
struct dsp56k_host_interface
struct dsp56156_host_interface
{
// **** Dsp56k side **** //
// **** DSP56156 side **** //
// Host Control Register
uint16_t* hcr;
@ -65,7 +65,7 @@ struct dsp56k_host_interface
};
// 1-9 ALU
struct dsp56k_data_alu
struct dsp56156_data_alu
{
// Four 16-bit input registers (can be accessed as 2 32-bit registers)
PAIR x;
@ -82,7 +82,7 @@ struct dsp56k_data_alu
};
// 1-10 Address Generation Unit (AGU)
struct dsp56k_agu
struct dsp56156_agu
{
// Four address registers
uint16_t r0;
@ -112,7 +112,7 @@ struct dsp56k_agu
};
// 1-11 Program Control Unit (PCU)
struct dsp56k_pcu
struct dsp56156_pcu
{
// Program Counter
uint16_t pc;
@ -138,7 +138,7 @@ struct dsp56k_pcu
// Controls IRQ processing
void (*service_interrupts)(void);
// A list of pending interrupts (indices into dsp56k_interrupt_sources array)
// A list of pending interrupts (indices into dsp56156_interrupt_sources array)
int8_t pending_interrupts[32];
// Basics
@ -149,26 +149,26 @@ struct dsp56k_pcu
};
// 1-8 The dsp56156 CORE
struct dsp56k_core
struct dsp56156_core
{
// PROGRAM CONTROLLER
dsp56k_pcu PCU;
dsp56156_pcu PCU;
// ADR ALU (AGU)
dsp56k_agu AGU;
dsp56156_agu AGU;
// CLOCK GEN
//static emu_timer *dsp56k_timer; // 1-5, 1-8 - Clock gen
//static emu_timer *dsp56156_timer; // 1-5, 1-8 - Clock gen
// DATA ALU
dsp56k_data_alu ALU;
dsp56156_data_alu ALU;
// OnCE
// IBS and BITFIELD UNIT
// Host Interface
dsp56k_host_interface HI;
dsp56156_host_interface HI;
// IRQ line states
bool modA_state;
@ -200,10 +200,10 @@ struct dsp56k_core
};
class dsp56k_device : public cpu_device
class dsp56156_device : public cpu_device
{
public:
dsp56k_device(const machine_config &mconfig, const char *_tag, device_t *_owner, uint32_t _clock);
dsp56156_device(const machine_config &mconfig, const char *_tag, device_t *_owner, uint32_t _clock);
DECLARE_READ16_MEMBER( peripheral_register_r );
DECLARE_WRITE16_MEMBER( peripheral_register_w );
@ -226,7 +226,7 @@ protected:
virtual uint32_t execute_min_cycles() const override { return 1; }
virtual uint32_t execute_max_cycles() const override { return 8; }
virtual uint32_t execute_input_lines() const override { return 4; }
virtual bool execute_input_edge_triggered(int inputnum) const override { return inputnum == DSP56K_IRQ_RESET; }
virtual bool execute_input_edge_triggered(int inputnum) const override { return inputnum == DSP56156_IRQ_RESET; }
virtual void execute_run() override;
virtual void execute_set_input(int inputnum, int state) override;
@ -244,16 +244,16 @@ private:
address_space_config m_data_config;
required_shared_ptr<uint16_t> m_program_ram;
dsp56k_core m_dsp56k_core;
dsp56156_core m_core;
void agu_init();
void alu_init();
};
} // namespace DSP56K
} // namespace DSP_56156
DECLARE_DEVICE_TYPE_NS(DSP56156, DSP56K, dsp56k_device)
using DSP56K::dsp56k_device;
DECLARE_DEVICE_TYPE_NS(DSP56156, DSP_56156, dsp56156_device)
using DSP_56156::dsp56156_device;
#endif // MAME_CPU_DSP56K_DSP56K_H
#endif // MAME_CPU_DSP56156_DSP56156_H

6
src/devices/cpu/dsp56k/dsp56def.h → src/devices/cpu/dsp56156/dsp56def.h
View File

@ -7,9 +7,9 @@
#ifndef __DSP56_DEF_H__
#define __DSP56_DEF_H__
#include "dsp56k.h"
#include "dsp56156.h"
namespace DSP56K
namespace DSP_56156
{
/***************************************************************************
ALU
@ -51,6 +51,6 @@ namespace DSP56K
#define TEMP cpustate->AGU.temp
} // namespace DSP56K
} // namespace DSP_56156
#endif

10
src/devices/cpu/dsp56k/dsp56dsm.cpp → src/devices/cpu/dsp56156/dsp56dsm.cpp
View File

@ -2,8 +2,8 @@
// copyright-holders:Andrew Gardner
/***************************************************************************
dsp56dsm.c
Disassembler for the portable Motorola/Freescale dsp56k emulator.
dsp56dsm.cpp
Disassembler for the portable Motorola/Freescale DSP56156 emulator.
Written by Andrew Gardner
***************************************************************************/
@ -12,7 +12,7 @@
#include "opcode.h"
#include "dsp56dsm.h"
u32 dsp56k_disassembler::opcode_alignment() const
u32 dsp56156_disassembler::opcode_alignment() const
{
return 1;
}
@ -20,13 +20,13 @@ u32 dsp56k_disassembler::opcode_alignment() const
/*****************************/
/* Main disassembly function */
/*****************************/
offs_t dsp56k_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer &params)
offs_t dsp56156_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer &params)
{
const uint16_t w0 = opcodes.r16(pc);
const uint16_t w1 = opcodes.r16(pc+1);
// Decode and disassemble.
DSP56K::Opcode op(w0, w1);
DSP_56156::Opcode op(w0, w1);
stream << op.disassemble();
const unsigned size = op.size();

14
src/devices/cpu/dsp56k/dsp56dsm.h → src/devices/cpu/dsp56156/dsp56dsm.h
View File

@ -2,22 +2,22 @@
// copyright-holders:Andrew Gardner
/***************************************************************************
dsp56dsm.c
Disassembler for the portable Motorola/Freescale dsp56k emulator.
dsp56dsm.cpp
Disassembler for the portable Motorola/Freescale DSP56156 emulator.
Written by Andrew Gardner
***************************************************************************/
#ifndef MAME_CPU_DSP56K_DSP56DSM_H
#define MAME_CPU_DSP56K_DSP56DSM_H
#ifndef MAME_CPU_DSP56156_DSP56156DSM_H
#define MAME_CPU_DSP56156_DSP56156DSM_H
#pragma once
class dsp56k_disassembler : public util::disasm_interface
class dsp56156_disassembler : public util::disasm_interface
{
public:
dsp56k_disassembler() = default;
virtual ~dsp56k_disassembler() = default;
dsp56156_disassembler() = default;
virtual ~dsp56156_disassembler() = default;
virtual u32 opcode_alignment() const override;
virtual offs_t disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer &params) override;

258
src/devices/cpu/dsp56k/dsp56mem.cpp → src/devices/cpu/dsp56156/dsp56mem.cpp
View File

@ -7,32 +7,32 @@
#include "dsp56mem.h"
#include "dsp56pcu.h"
namespace DSP56K {
namespace DSP_56156 {
/* IPR Accessor Implementations */
void IPR_set(dsp56k_core* cpustate, uint16_t value)
void IPR_set(dsp56156_core* cpustate, uint16_t value)
{
/* TODO: Is there anything else? */
IPR = value;
}
int8_t irqa_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0003) >> 0) - 1; }
uint8_t irqa_trigger(dsp56k_core* cpustate){ return (IPR & 0x0004) >> 2; }
int8_t irqb_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0018) >> 3) - 1; }
uint8_t irqb_trigger(dsp56k_core* cpustate){ return (IPR & 0x0002) >> 5; }
int8_t codec_ipl(dsp56k_core* cpustate) { return ((IPR & 0x00c0) >> 6) - 1; }
int8_t host_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0300) >> 8) - 1; }
int8_t ssi0_ipl(dsp56k_core* cpustate) { return ((IPR & 0x0c00) >> 10) - 1; }
int8_t ssi1_ipl(dsp56k_core* cpustate) { return ((IPR & 0x3000) >> 12) - 1; }
int8_t tm_ipl(dsp56k_core* cpustate) { return ((IPR & 0xc000) >> 14) - 1; }
int8_t irqa_ipl(dsp56156_core* cpustate) { return ((IPR & 0x0003) >> 0) - 1; }
uint8_t irqa_trigger(dsp56156_core* cpustate){ return (IPR & 0x0004) >> 2; }
int8_t irqb_ipl(dsp56156_core* cpustate) { return ((IPR & 0x0018) >> 3) - 1; }
uint8_t irqb_trigger(dsp56156_core* cpustate){ return (IPR & 0x0002) >> 5; }
int8_t codec_ipl(dsp56156_core* cpustate) { return ((IPR & 0x00c0) >> 6) - 1; }
int8_t host_ipl(dsp56156_core* cpustate) { return ((IPR & 0x0300) >> 8) - 1; }
int8_t ssi0_ipl(dsp56156_core* cpustate) { return ((IPR & 0x0c00) >> 10) - 1; }
int8_t ssi1_ipl(dsp56156_core* cpustate) { return ((IPR & 0x3000) >> 12) - 1; }
int8_t tm_ipl(dsp56156_core* cpustate) { return ((IPR & 0xc000) >> 14) - 1; }
void mem_reset(dsp56k_core* cpustate)
void mem_reset(dsp56156_core* cpustate)
{
// Reset the HI registers
dsp56k_host_interface_reset(cpustate);
dsp56156_host_interface_reset(cpustate);
// Reset the IO registers
dsp56k_io_reset(cpustate);
dsp56156_io_reset(cpustate);
}
@ -45,7 +45,7 @@ void mem_reset(dsp56k_core* cpustate)
/************************************/
/* Host Control Register (HCR) Bits */
/************************************/
void HCR_set(dsp56k_core* cpustate, uint16_t value)
void HCR_set(dsp56156_core* cpustate, uint16_t value)
{
HF3_bit_set (cpustate, (value & 0x0010) >> 4);
HF2_bit_set (cpustate, (value & 0x0008) >> 3);
@ -53,13 +53,13 @@ void HCR_set(dsp56k_core* cpustate, uint16_t value)
HTIE_bit_set(cpustate, (value & 0x0002) >> 1);
HRIE_bit_set(cpustate, (value & 0x0001) >> 0);
}
//uint16_t HF3_bit(dsp56k_core* cpustate) { return ((HCR & 0x0010) != 0); }
//uint16_t HF2_bit(dsp56k_core* cpustate) { return ((HCR & 0x0008) != 0); }
uint16_t HCIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0004) != 0); }
uint16_t HTIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0002) != 0); }
uint16_t HRIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0001) != 0); }
//uint16_t HF3_bit(dsp56156_core* cpustate) { return ((HCR & 0x0010) != 0); }
//uint16_t HF2_bit(dsp56156_core* cpustate) { return ((HCR & 0x0008) != 0); }
uint16_t HCIE_bit(dsp56156_core* cpustate) { return ((HCR & 0x0004) != 0); }
uint16_t HTIE_bit(dsp56156_core* cpustate) { return ((HCR & 0x0002) != 0); }
uint16_t HRIE_bit(dsp56156_core* cpustate) { return ((HCR & 0x0001) != 0); }
void HF3_bit_set(dsp56k_core* cpustate, uint16_t value)
void HF3_bit_set(dsp56156_core* cpustate, uint16_t value)
{
value = value & 0x01;
HCR &= ~(0x0010);
@ -67,7 +67,7 @@ void HF3_bit_set(dsp56k_core* cpustate, uint16_t value)
HF3_bit_host_set(cpustate, value);
}
void HF2_bit_set(dsp56k_core* cpustate, uint16_t value)
void HF2_bit_set(dsp56156_core* cpustate, uint16_t value)
{
value = value & 0x01;
HCR &= ~(0x0008);
@ -75,19 +75,19 @@ void HF2_bit_set(dsp56k_core* cpustate, uint16_t value)
HF2_bit_host_set(cpustate, value);
}
void HCIE_bit_set(dsp56k_core* cpustate, uint16_t value)
void HCIE_bit_set(dsp56156_core* cpustate, uint16_t value)
{
value = value & 0x01;
HCR &= ~(0x0004);
HCR |= (value << 2);
}
void HTIE_bit_set(dsp56k_core* cpustate, uint16_t value)
void HTIE_bit_set(dsp56156_core* cpustate, uint16_t value)
{
value = value & 0x01;
HCR &= ~(0x0002);
HCR |= (value << 1);
}
void HRIE_bit_set(dsp56k_core* cpustate, uint16_t value)
void HRIE_bit_set(dsp56156_core* cpustate, uint16_t value)
{
value = value & 0x01;
HCR &= ~(0x0001);
@ -97,42 +97,42 @@ void HRIE_bit_set(dsp56k_core* cpustate, uint16_t value)
/***********************************/
/* Host Status Register (HSR) Bits */
/***********************************/
//uint16_t DMA_bit(dsp56k_core* cpustate) { return ((HSR & 0x0080) != 0); }
//uint16_t HF1_bit(dsp56k_core* cpustate) { return ((HSR & 0x0010) != 0); }
//uint16_t HF0_bit(dsp56k_core* cpustate) { return ((HSR & 0x0008) != 0); }
//uint16_t HCP_bit(dsp56k_core* cpustate) { return ((HSR & 0x0004) != 0); }
uint16_t HTDE_bit(dsp56k_core* cpustate) { return ((HSR & 0x0002) != 0); }
uint16_t HRDF_bit(dsp56k_core* cpustate) { return ((HSR & 0x0001) != 0); }
//uint16_t DMA_bit(dsp56156_core* cpustate) { return ((HSR & 0x0080) != 0); }
//uint16_t HF1_bit(dsp56156_core* cpustate) { return ((HSR & 0x0010) != 0); }
//uint16_t HF0_bit(dsp56156_core* cpustate) { return ((HSR & 0x0008) != 0); }
//uint16_t HCP_bit(dsp56156_core* cpustate) { return ((HSR & 0x0004) != 0); }
uint16_t HTDE_bit(dsp56156_core* cpustate) { return ((HSR & 0x0002) != 0); }
uint16_t HRDF_bit(dsp56156_core* cpustate) { return ((HSR & 0x0001) != 0); }
void DMA_bit_set(dsp56k_core* cpustate, uint16_t value)
void DMA_bit_set(dsp56156_core* cpustate, uint16_t value)
{
value = value & 0x01;
HSR &= ~(0x0080);
HSR |= (value << 7);
// TODO: 5-12 When the DMA bit is set, the DMA mode is enabled by the Host Mode bits HM0 & HM1
}
void HF1_bit_set(dsp56k_core* cpustate, uint16_t value)
void HF1_bit_set(dsp56156_core* cpustate, uint16_t value)
{
value = value & 0x01;
HSR &= ~(0x0010);
HSR |= (value << 4);
}
void HF0_bit_set(dsp56k_core* cpustate, uint16_t value)
void HF0_bit_set(dsp56156_core* cpustate, uint16_t value)
{
value = value & 0x01;
HSR &= ~(0x0008);
HSR |= (value << 3);
}
void HCP_bit_set(dsp56k_core* cpustate, uint16_t value)
void HCP_bit_set(dsp56156_core* cpustate, uint16_t value)
{
value = value & 0x01;
HSR &= ~(0x0004);
HSR |= (value << 2);
if (value && HCIE_bit(cpustate))
dsp56k_add_pending_interrupt(cpustate, "Host Command");
dsp56156_add_pending_interrupt(cpustate, "Host Command");
}
void HTDE_bit_set(dsp56k_core* cpustate, uint16_t value)
void HTDE_bit_set(dsp56156_core* cpustate, uint16_t value)
{
value = value & 0x01;
HSR &= ~(0x0002);
@ -140,13 +140,13 @@ void HTDE_bit_set(dsp56k_core* cpustate, uint16_t value)
// 5-10 If HTIE bit is set, whip out a Host Transmit Data interrupt
if (value && HTIE_bit(cpustate))
dsp56k_add_pending_interrupt(cpustate, "Host Transmit Data");
dsp56156_add_pending_interrupt(cpustate, "Host Transmit Data");
// 5-5 If both me and RXDF are cleared, transmit data to the host
if (!value && !RXDF_bit(cpustate))
dsp56k_host_interface_HTX_to_host(cpustate);
dsp56156_host_interface_HTX_to_host(cpustate);
}
void HRDF_bit_set(dsp56k_core* cpustate, uint16_t value)
void HRDF_bit_set(dsp56156_core* cpustate, uint16_t value)
{
value = value & 0x01;
HSR &= ~(0x0001);
@ -154,11 +154,11 @@ void HRDF_bit_set(dsp56k_core* cpustate, uint16_t value)
// 5-10 If HRIE is set, whip out a Host Receive Data interrupt
if (value && HRIE_bit(cpustate))
dsp56k_add_pending_interrupt(cpustate, "Host Receive Data");
dsp56156_add_pending_interrupt(cpustate, "Host Receive Data");
// 5-5 If both me and TXDE are cleared, transmit data to the dsp56k
// 5-5 If both me and TXDE are cleared, transmit data to the dsp56156
if (!value && !TXDE_bit(cpustate))
dsp56k_host_interface_host_to_HTX(cpustate);
dsp56156_host_interface_host_to_HTX(cpustate);
}
@ -169,7 +169,7 @@ void HRDF_bit_set(dsp56k_core* cpustate, uint16_t value)
/*****************************************/
/* Interrupt Control Register (ICR) Bits */
/*****************************************/
void ICR_set(dsp56k_core* cpustate, uint8_t value)
void ICR_set(dsp56156_core* cpustate, uint8_t value)
{
HF1_bit_host_set(cpustate, (value & 0x10) >> 4);
HF0_bit_host_set(cpustate, (value & 0x08) >> 3);
@ -177,18 +177,18 @@ void ICR_set(dsp56k_core* cpustate, uint8_t value)
RREQ_bit_set(cpustate, (value & 0x01) >> 0);
}
//uint8_t INIT_bit(dsp56k_core* cpustate); #define x_initBIT ((dsp56k.HI.ICR & 0x0080) != 0)
//uint8_t HM1_bit(dsp56k_core* cpustate); #define x_hm1BIT ((dsp56k.HI.ICR & 0x0040) != 0)
//uint8_t HM0_bit(dsp56k_core* cpustate); #define x_hm0BIT ((dsp56k.HI.ICR & 0x0020) != 0)
//uint8_t HF1_bit_host(dsp56k_core* cpustate); #define x_hf1BIT ((dsp56k.HI.ICR & 0x0010) != 0)
//uint8_t HF0_bit_host(dsp56k_core* cpustate); #define x_hf0BIT ((dsp56k.HI.ICR & 0x0008) != 0)
//uint8_t TREQ_bit(dsp56k_core* cpustate); #define x_treqBIT ((dsp56k.HI.ICR & 0x0002) != 0)
//uint8_t RREQ_bit(dsp56k_core* cpustate); #define x_rreqBIT ((dsp56k.HI.ICR & 0x0001) != 0)
//uint8_t INIT_bit(dsp56156_core* cpustate); #define x_initBIT ((dsp56156.HI.ICR & 0x0080) != 0)
//uint8_t HM1_bit(dsp56156_core* cpustate); #define x_hm1BIT ((dsp56156.HI.ICR & 0x0040) != 0)
//uint8_t HM0_bit(dsp56156_core* cpustate); #define x_hm0BIT ((dsp56156.HI.ICR & 0x0020) != 0)
//uint8_t HF1_bit_host(dsp56156_core* cpustate); #define x_hf1BIT ((dsp56156.HI.ICR & 0x0010) != 0)
//uint8_t HF0_bit_host(dsp56156_core* cpustate); #define x_hf0BIT ((dsp56156.HI.ICR & 0x0008) != 0)
//uint8_t TREQ_bit(dsp56156_core* cpustate); #define x_treqBIT ((dsp56156.HI.ICR & 0x0002) != 0)
//uint8_t RREQ_bit(dsp56156_core* cpustate); #define x_rreqBIT ((dsp56156.HI.ICR & 0x0001) != 0)
//void INIT_bit_set(dsp56k_core* cpustate, uint8_t value); #define CLEAR_x_initBIT() (dsp56k.HI.ICR &= (~0x0080))
//void HM1_bit_set(dsp56k_core* cpustate, uint8_t value); #define CLEAR_x_hm1BIT() (dsp56k.HI.ICR &= (~0x0040))
//void HM0_bit_set(dsp56k_core* cpustate, uint8_t value); #define CLEAR_x_hm0BIT() (dsp56k.HI.ICR &= (~0x0020))
void HF1_bit_host_set(dsp56k_core* cpustate, uint8_t value)
//void INIT_bit_set(dsp56156_core* cpustate, uint8_t value); #define CLEAR_x_initBIT() (dsp56156.HI.ICR &= (~0x0080))
//void HM1_bit_set(dsp56156_core* cpustate, uint8_t value); #define CLEAR_x_hm1BIT() (dsp56156.HI.ICR &= (~0x0040))
//void HM0_bit_set(dsp56156_core* cpustate, uint8_t value); #define CLEAR_x_hm0BIT() (dsp56156.HI.ICR &= (~0x0020))
void HF1_bit_host_set(dsp56156_core* cpustate, uint8_t value)
{
value = value & 0x01;
ICR &= ~(0x10);
@ -196,7 +196,7 @@ void HF1_bit_host_set(dsp56k_core* cpustate, uint8_t value)
HF1_bit_set(cpustate, value); // 5-14
}
void HF0_bit_host_set(dsp56k_core* cpustate, uint8_t value)
void HF0_bit_host_set(dsp56156_core* cpustate, uint8_t value)
{
value = value & 0x01;
ICR &= ~(0x08);
@ -204,13 +204,13 @@ void HF0_bit_host_set(dsp56k_core* cpustate, uint8_t value)
HF0_bit_set(cpustate, value); // 5-13
}
void TREQ_bit_set(dsp56k_core* cpustate, uint8_t value)
void TREQ_bit_set(dsp56156_core* cpustate, uint8_t value)
{
value = value & 0x01;
ICR &= ~(0x02);
ICR |= (value << 1);
}
void RREQ_bit_set(dsp56k_core* cpustate, uint8_t value)
void RREQ_bit_set(dsp56156_core* cpustate, uint8_t value)
{
value = value & 0x01;
ICR &= ~(0x01);
@ -228,16 +228,16 @@ void RREQ_bit_set(dsp56k_core* cpustate, uint8_t value)
/**************************************/
/* Command Vector Register (CVR) Bits */
/**************************************/
uint8_t HV_bits(dsp56k_core* cpustate) { return (CVR & 0x1f); }
uint8_t HV_bits(dsp56156_core* cpustate) { return (CVR & 0x1f); }
void CVR_set(dsp56k_core* cpustate, uint8_t value)
void CVR_set(dsp56156_core* cpustate, uint8_t value)
{
/* A single, unified place to run all callbacks for each of the bits */
HC_bit_set(cpustate, (value & 0x80) >> 7);
HV_bits_set(cpustate, (value & 0x1f));
}
void HC_bit_set(dsp56k_core* cpustate, uint8_t value)
void HC_bit_set(dsp56156_core* cpustate, uint8_t value)
{
value = value & 0x01;
CVR &= ~(0x80);
@ -245,7 +245,7 @@ void HC_bit_set(dsp56k_core* cpustate, uint8_t value)
HCP_bit_set(cpustate, value); // 5-9 & 5-11
}
void HV_bits_set(dsp56k_core* cpustate, uint8_t value)
void HV_bits_set(dsp56156_core* cpustate, uint8_t value)
{
value = value & 0x1f;
CVR &= ~(0x1f);
@ -256,34 +256,34 @@ void HV_bits_set(dsp56k_core* cpustate, uint8_t value)
/****************************************/
/* Interrupt Status Register (ISR) Bits */
/****************************************/
uint8_t TXDE_bit(dsp56k_core* cpustate) { return ((ISR & 0x0002) != 0); }
uint8_t RXDF_bit(dsp56k_core* cpustate) { return ((ISR & 0x0001) != 0); }
uint8_t TXDE_bit(dsp56156_core* cpustate) { return ((ISR & 0x0002) != 0); }
uint8_t RXDF_bit(dsp56156_core* cpustate) { return ((ISR & 0x0001) != 0); }
void HF3_bit_host_set(dsp56k_core* cpustate, uint8_t value)
void HF3_bit_host_set(dsp56156_core* cpustate, uint8_t value)
{
value = value & 0x01;
ISR &= ~(0x0010);
ISR |= (value << 4);
}
void HF2_bit_host_set(dsp56k_core* cpustate, uint8_t value)
void HF2_bit_host_set(dsp56156_core* cpustate, uint8_t value)
{
value = value & 0x01;
ISR &= ~(0x0008);
ISR |= (value << 3);
}
void TXDE_bit_set(dsp56k_core* cpustate, uint8_t value)
void TXDE_bit_set(dsp56156_core* cpustate, uint8_t value)
{
value = value & 0x01;
ISR &= ~(0x0002);
ISR |= (value << 1);
// If both me and the HRDF are cleared, transmit data to the dsp56k
// If both me and the HRDF are cleared, transmit data to the dsp56156
if (!value && !HRDF_bit(cpustate))
dsp56k_host_interface_host_to_HTX(cpustate);
dsp56156_host_interface_host_to_HTX(cpustate);
}
void RXDF_bit_set(dsp56k_core* cpustate, uint8_t value)
void RXDF_bit_set(dsp56156_core* cpustate, uint8_t value)
{
value = value & 0x01;
ISR &= ~(0x0001);
@ -291,13 +291,13 @@ void RXDF_bit_set(dsp56k_core* cpustate, uint8_t value)
// If both me and HTDE are cleared, transmit data to the host
if (!value && !HTDE_bit(cpustate))
dsp56k_host_interface_HTX_to_host(cpustate);
dsp56156_host_interface_HTX_to_host(cpustate);
}
// TODO: 5-11 What is the host processor Initialize function?
void dsp56k_host_interface_reset(dsp56k_core* cpustate)
void dsp56156_host_interface_reset(dsp56156_core* cpustate)
{
// Hook up the CPU-side pointers properly.
cpustate->HI.hcr = &cpustate->peripheral_ram[A2O(0xffc4)];
@ -325,7 +325,7 @@ void dsp56k_host_interface_reset(dsp56k_core* cpustate)
/* TODO: ISR (at least) */
}
void dsp56k_host_interface_HTX_to_host(dsp56k_core* cpustate)
void dsp56156_host_interface_HTX_to_host(dsp56156_core* cpustate)
{
RXH = ((HTX & 0xff00) >> 8);
RXL = ((HTX & 0x00ff));
@ -333,7 +333,7 @@ void dsp56k_host_interface_HTX_to_host(dsp56k_core* cpustate)
HTDE_bit_set(cpustate, 1);
}
void dsp56k_host_interface_host_to_HTX(dsp56k_core* cpustate)
void dsp56156_host_interface_host_to_HTX(dsp56156_core* cpustate)
{
HRX &= 0x00ff;
HRX |= (TXH << 8);
@ -348,7 +348,7 @@ void dsp56k_host_interface_host_to_HTX(dsp56k_core* cpustate)
I/O INTERFACE
***************************************************************************/
/* BCR */
void BCR_set(dsp56k_core* cpustate, uint16_t value)
void BCR_set(dsp56156_core* cpustate, uint16_t value)
{
RH_bit_set(cpustate, (value & 0x8000) >> 15);
BS_bit_set(cpustate, (value & 0x4000) >> 14);
@ -356,12 +356,12 @@ void BCR_set(dsp56k_core* cpustate, uint16_t value)
external_p_wait_states_set(cpustate, (value & 0x001f) >> 0);
}
//uint16_t RH_bit(dsp56k_core* cpustate);
//uint16_t BS_bit(dsp56k_core* cpustate);
//uint16_t external_x_wait_states(dsp56k_core* cpustate);
//uint16_t external_p_wait_states(dsp56k_core* cpustate);
//uint16_t RH_bit(dsp56156_core* cpustate);
//uint16_t BS_bit(dsp56156_core* cpustate);
//uint16_t external_x_wait_states(dsp56156_core* cpustate);
//uint16_t external_p_wait_states(dsp56156_core* cpustate);
void RH_bit_set(dsp56k_core* cpustate, uint16_t value)
void RH_bit_set(dsp56156_core* cpustate, uint16_t value)
{
value = value & 0x0001;
BCR &= ~(0x8000);
@ -369,7 +369,7 @@ void RH_bit_set(dsp56k_core* cpustate, uint16_t value)
// TODO: 4-6 Assert BR pin?
}
void BS_bit_set(dsp56k_core* cpustate, uint16_t value)
void BS_bit_set(dsp56156_core* cpustate, uint16_t value)
{
value = value & 0x0001;
BCR &= ~(0x4000);
@ -377,13 +377,13 @@ void BS_bit_set(dsp56k_core* cpustate, uint16_t value)
// TODO: 4-6 Respond to BR pin?
}
void external_x_wait_states_set(dsp56k_core* cpustate, uint16_t value)
void external_x_wait_states_set(dsp56156_core* cpustate, uint16_t value)
{
value = value & 0x001f;
BCR &= ~(0x03e0);
BCR |= (value << 5);
}
void external_p_wait_states_set(dsp56k_core* cpustate, uint16_t value)
void external_p_wait_states_set(dsp56156_core* cpustate, uint16_t value)
{
value = value & 0x001f;
BCR &= ~(0x001f);
@ -392,7 +392,7 @@ void external_p_wait_states_set(dsp56k_core* cpustate, uint16_t value)
/* Port B Control Register PBC */
void PBC_set(dsp56k_core* cpustate, uint16_t value)
void PBC_set(dsp56156_core* cpustate, uint16_t value)
{
if (value & 0xfffe)
cpustate->device->logerror("Dsp56k : Attempting to set reserved bits in the PBC. Ignoring.\n");
@ -403,7 +403,7 @@ void PBC_set(dsp56k_core* cpustate, uint16_t value)
}
#ifdef UNUSED_FUNCTION
int host_interface_active(dsp56k_core* cpustate)
int host_interface_active(dsp56156_core* cpustate)
{
/* The host interface is active if the 0th bit in the PBC is set */
return PBC & 0x0001;
@ -411,7 +411,7 @@ int host_interface_active(dsp56k_core* cpustate)
#endif
/* Port B Data Direction Register (PBDDR) */
void PBDDR_set(dsp56k_core* cpustate, uint16_t value)
void PBDDR_set(dsp56156_core* cpustate, uint16_t value)
{
if (value & 0x8000)
cpustate->device->logerror("Dsp56k : Attempting to set reserved bits in the PBDDR. Ignoring.\n");
@ -420,11 +420,11 @@ void PBDDR_set(dsp56k_core* cpustate, uint16_t value)
PBDDR &= ~(0x7fff);
PBDDR |= (value << 0);
/* TODO: Implement dsp56k io restrictions, etc. */
/* TODO: Implement dsp56156 io restrictions, etc. */
}
/* Port B Data Register (PBD) */
void PBD_set(dsp56k_core* cpustate, uint16_t value)
void PBD_set(dsp56156_core* cpustate, uint16_t value)
{
if (value & 0x8000)
cpustate->device->logerror("Dsp56k : Attempting to set reserved bits in the PBD. Ignoring.\n");
@ -433,11 +433,11 @@ void PBD_set(dsp56k_core* cpustate, uint16_t value)
PBD &= ~(0x7fff);
PBD |= (value << 0);
/* TODO: Implement dsp56k io restrictions, etc. */
/* TODO: Implement dsp56156 io restrictions, etc. */
}
/* Port C Control Register (PCC) */
void PCC_set(dsp56k_core* cpustate, uint16_t value)
void PCC_set(dsp56156_core* cpustate, uint16_t value)
{
if (value & 0xf000)
cpustate->device->logerror("Dsp56k : Attempting to set reserved bits in the PCC. Ignoring.\n");
@ -446,11 +446,11 @@ void PCC_set(dsp56k_core* cpustate, uint16_t value)
PCC &= ~(0x0fff);
PCC |= (value << 0);
/* TODO: Implement dsp56k timer and control glue */
/* TODO: Implement dsp56156 timer and control glue */
}
/* Port C Data Direction Register (PCDDR) */
void PCDDR_set(dsp56k_core* cpustate, uint16_t value)
void PCDDR_set(dsp56156_core* cpustate, uint16_t value)
{
if (value & 0xf000)
cpustate->device->logerror("Dsp56k : Attempting to set reserved bits in the PCDDR. Ignoring.\n");
@ -459,11 +459,11 @@ void PCDDR_set(dsp56k_core* cpustate, uint16_t value)
PCDDR &= ~(0x0fff);
PCDDR |= (value << 0);
/* TODO: Implement dsp56k io restrictions, etc. */
/* TODO: Implement dsp56156 io restrictions, etc. */
}
/* Port C Data Register (PCD) */
void PCD_set(dsp56k_core* cpustate, uint16_t value)
void PCD_set(dsp56156_core* cpustate, uint16_t value)
{
if (value & 0xf000)
cpustate->device->logerror("Dsp56k : Attempting to set reserved bits in the PCD. Ignoring.\n");
@ -476,7 +476,7 @@ void PCD_set(dsp56k_core* cpustate, uint16_t value)
PCD |= (value << 0);
}
void dsp56k_io_reset(dsp56k_core* cpustate)
void dsp56156_io_reset(dsp56156_core* cpustate)
{
/* The BCR = 0x43ff */
RH_bit_set(cpustate, 0);
@ -487,9 +487,9 @@ void dsp56k_io_reset(dsp56k_core* cpustate)
/* Work */
READ16_MEMBER( dsp56k_device::peripheral_register_r )
READ16_MEMBER( dsp56156_device::peripheral_register_r )
{
dsp56k_core* cpustate = &m_dsp56k_core;
dsp56156_core* cpustate = &m_core;
// (printf) cpustate->device->logerror("Peripheral read 0x%04x\n", O2A(offset));
switch (O2A(offset))
@ -551,12 +551,12 @@ READ16_MEMBER( dsp56k_device::peripheral_register_r )
// HTX/HRX: Host TX/RX Register
case 0xffe5:
// 5-5
if (!DSP56K::HRDF_bit(cpustate))
if (!DSP_56156::HRDF_bit(cpustate))
return 0xbeef;
else
{
uint16_t value = HRX; // TODO: Maybe not exactly right? Just being safe.
DSP56K::HRDF_bit_set(cpustate, 0);
DSP_56156::HRDF_bit_set(cpustate, 0);
return value;
}
// COSR
@ -621,9 +621,9 @@ READ16_MEMBER( dsp56k_device::peripheral_register_r )
return cpustate->peripheral_ram[offset];
}
WRITE16_MEMBER( dsp56k_device::peripheral_register_w )
WRITE16_MEMBER( dsp56156_device::peripheral_register_w )
{
dsp56k_core* cpustate = &m_dsp56k_core;
dsp56156_core* cpustate = &m_core;
// Its primary behavior is RAM
// COMBINE_DATA(&cpustate->peripheral_ram[offset]);
@ -635,27 +635,27 @@ WRITE16_MEMBER( dsp56k_device::peripheral_register_w )
{
// Port B Control Register (PBC)
case 0xffc0:
DSP56K::PBC_set(cpustate, data);
DSP_56156::PBC_set(cpustate, data);
break;
// Port C Control Register (PCC)
case 0xffc1:
DSP56K::PCC_set(cpustate, data);
DSP_56156::PCC_set(cpustate, data);
break;
// Port B Data Direction Register (PBDDR)
case 0xffc2:
DSP56K::PBDDR_set(cpustate, data);
DSP_56156::PBDDR_set(cpustate, data);
break;
// Port C Data Direction Register (PCDDR)
case 0xffc3:
DSP56K::PCDDR_set(cpustate, data);
DSP_56156::PCDDR_set(cpustate, data);
break;
// HCR: Host Control Register
case 0xffc4:
DSP56K::HCR_set(cpustate, data);
DSP_56156::HCR_set(cpustate, data);
break;
// COCR
@ -688,22 +688,22 @@ WRITE16_MEMBER( dsp56k_device::peripheral_register_w )
// BCR: Bus Control Register
case 0xffde:
DSP56K::BCR_set(cpustate, data);
DSP_56156::BCR_set(cpustate, data);
break;
// IPR: Interrupt Priority Register
case 0xffdf:
DSP56K::IPR_set(cpustate, data);
DSP_56156::IPR_set(cpustate, data);
break;
// Port B Data Register (PBD)
case 0xffe2:
DSP56K::PBD_set(cpustate, data);
DSP_56156::PBD_set(cpustate, data);
break;
// Port C Data Register (PCD)
case 0xffe3:
DSP56K::PCD_set(cpustate, data);
DSP_56156::PCD_set(cpustate, data);
break;
// HSR: Host Status Register
@ -712,7 +712,7 @@ WRITE16_MEMBER( dsp56k_device::peripheral_register_w )
// HTX/HRX: Host TX/RX Register
case 0xffe5:
HTX = data;
DSP56K::HTDE_bit_set(cpustate, 0); // 5-5
DSP_56156::HTDE_bit_set(cpustate, 0); // 5-5
break;
// COSR
@ -777,10 +777,10 @@ WRITE16_MEMBER( dsp56k_device::peripheral_register_w )
}
/* These two functions are exposed to the outside world */
/* They represent the host side of the dsp56k's host interface */
void dsp56k_device::host_interface_write(uint8_t offset, uint8_t data)
/* They represent the host side of the dsp56156's host interface */
void dsp56156_device::host_interface_write(uint8_t offset, uint8_t data)
{
dsp56k_core* cpustate = &m_dsp56k_core;
dsp56156_core* cpustate = &m_core;
/* Not exactly correct since the bootstrap hack doesn't need this to be true */
/*
@ -805,12 +805,12 @@ void dsp56k_device::host_interface_write(uint8_t offset, uint8_t data)
break;
}
}
DSP56K::ICR_set(cpustate, data);
DSP_56156::ICR_set(cpustate, data);
break;
// Command Vector Register (CVR)
case 0x01:
DSP56K::CVR_set(cpustate, data);
DSP_56156::CVR_set(cpustate, data);
break;
// Interrupt status register (ISR) - Read only!
@ -841,7 +841,7 @@ void dsp56k_device::host_interface_write(uint8_t offset, uint8_t data)
break; /* Probably the right thing to do, given this is a hack */
}
if (DSP56K::TXDE_bit(cpustate)) // 5-5
if (DSP_56156::TXDE_bit(cpustate)) // 5-5
{
TXH = data;
}
@ -863,20 +863,20 @@ void dsp56k_device::host_interface_write(uint8_t offset, uint8_t data)
break; /* Probably the right thing to do, given this is a hack */
}
if (DSP56K::TXDE_bit(cpustate)) // 5-5
if (DSP_56156::TXDE_bit(cpustate)) // 5-5
{
TXL = data;
DSP56K::TXDE_bit_set(cpustate, 0);
DSP_56156::TXDE_bit_set(cpustate, 0);
}
break;
default: cpustate->device->logerror("DSP56k : dsp56k_host_interface_write called with invalid address 0x%02x.\n", offset);
default: cpustate->device->logerror("DSP56k : dsp56156_host_interface_write called with invalid address 0x%02x.\n", offset);
}
}
uint8_t dsp56k_device::host_interface_read(uint8_t offset)
uint8_t dsp56156_device::host_interface_read(uint8_t offset)
{
dsp56k_core* cpustate = &m_dsp56k_core;
dsp56156_core* cpustate = &m_core;
/* Not exactly correct since the bootstrap hack doesn't need this to be true */
/*
@ -914,7 +914,7 @@ uint8_t dsp56k_device::host_interface_read(uint8_t offset)
// Receive byte register - high byte (RXH)
case 0x06:
// 5-5
if (!DSP56K::RXDF_bit(cpustate))
if (!DSP_56156::RXDF_bit(cpustate))
return 0xbf;
else
return RXH;
@ -922,16 +922,16 @@ uint8_t dsp56k_device::host_interface_read(uint8_t offset)
// Receive byte register - low byte (RXL)
case 0x07:
// 5-5
if (!DSP56K::RXDF_bit(cpustate))
if (!DSP_56156::RXDF_bit(cpustate))
return 0xbf;
else
{
uint8_t value = RXL; // TODO: Maybe not exactly right? I'm just being safe.
DSP56K::RXDF_bit_set(cpustate, 0);
DSP_56156::RXDF_bit_set(cpustate, 0);
return value;
}
default: cpustate->device->logerror("DSP56k : dsp56k_host_interface_read called with invalid address 0x%02x.\n", offset);
default: cpustate->device->logerror("DSP56k : dsp56156_host_interface_read called with invalid address 0x%02x.\n", offset);
}
/* Shouldn't get here */
@ -939,11 +939,11 @@ uint8_t dsp56k_device::host_interface_read(uint8_t offset)
}
/* MISC*/
uint16_t dsp56k_device::get_peripheral_memory(uint16_t addr)
uint16_t dsp56156_device::get_peripheral_memory(uint16_t addr)
{
dsp56k_core* cpustate = &m_dsp56k_core;
dsp56156_core* cpustate = &m_core;
return cpustate->peripheral_ram[A2O(addr)];
}
} // namespace DSP56K
} // namespace DSP_56156

241
src/devices/cpu/dsp56156/dsp56mem.h Normal file
View File

@ -0,0 +1,241 @@
// license:BSD-3-Clause
// copyright-holders:Andrew Gardner
#ifndef MAME_CPU_DSP56156_DSP56MEM_H
#define MAME_CPU_DSP56156_DSP56MEM_H
#include "dsp56156.h"
namespace DSP_56156 {
/***************************************************************************
MEMORY
***************************************************************************/
void mem_reset(dsp56156_core* cpustate);
// Adjusts the documented address to match the offset in peripheral RAM
#define A2O(a) (a - 0xffc0)
// Adjusts the offset in peripheral RAM to match the documented address
#define O2A(a) (a + 0xffc0)
// The memory 'registers'
#define PBC (cpustate->peripheral_ram[A2O(0xffc0)])
#define PCC (cpustate->peripheral_ram[A2O(0xffc1)])
#define PBDDR (cpustate->peripheral_ram[A2O(0xffc2)])
#define PCDDR (cpustate->peripheral_ram[A2O(0xffc3)])
#define HCR (cpustate->peripheral_ram[A2O(0xffc4)])
#define COCR (cpustate->peripheral_ram[A2O(0xffc8)])
#define CRASSI0 (cpustate->peripheral_ram[A2O(0xffd0)])
#define CRBSSI0 (cpustate->peripheral_ram[A2O(0xffd1)])
#define CRASSI1 (cpustate->peripheral_ram[A2O(0xffd8)])
#define CRBSSI1 (cpustate->peripheral_ram[A2O(0xffd9)])
#define PLCR (cpustate->peripheral_ram[A2O(0xffdc)])
#define BCR (cpustate->peripheral_ram[A2O(0xffde)])
#define IPR (cpustate->peripheral_ram[A2O(0xffdf)])
#define PBD (cpustate->peripheral_ram[A2O(0xffe2)])
#define PCD (cpustate->peripheral_ram[A2O(0xffe3)])
#define HSR (cpustate->peripheral_ram[A2O(0xffe4)])
#define HTXHRX (cpustate->peripheral_ram[A2O(0xffe5)])
#define COSR (cpustate->peripheral_ram[A2O(0xffe8)])
#define CRXCTX (cpustate->peripheral_ram[A2O(0xffe9)])
#define TCR (cpustate->peripheral_ram[A2O(0xffec)])
#define TCTR (cpustate->peripheral_ram[A2O(0xffed)])
#define TCPR (cpustate->peripheral_ram[A2O(0xffee)])
#define TPR (cpustate->peripheral_ram[A2O(0xffef)])
#define TSRSSI0 (cpustate->peripheral_ram[A2O(0xfff0)])
#define TRXSSI0 (cpustate->peripheral_ram[A2O(0xfff1)])
#define RSMA0 (cpustate->peripheral_ram[A2O(0xfff2)])
#define RSMB0 (cpustate->peripheral_ram[A2O(0xfff3)])
#define TSMA0 (cpustate->peripheral_ram[A2O(0xfff4)])
#define TSMB0 (cpustate->peripheral_ram[A2O(0xfff5)])
#define TSRSSI1 (cpustate->peripheral_ram[A2O(0xfff8)])
#define TRXSSI1 (cpustate->peripheral_ram[A2O(0xfff9)])
#define RSMA1 (cpustate->peripheral_ram[A2O(0xfffa)])
#define RSMB1 (cpustate->peripheral_ram[A2O(0xfffb)])
#define TSMA1 (cpustate->peripheral_ram[A2O(0xfffc)])
#define TSMB1 (cpustate->peripheral_ram[A2O(0xfffd)])
/* Interrupt priority register (IPR) bits */
void IPR_set(dsp56156_core* cpustate, uint16_t value);
/* A return value of -1 means disabled */
int8_t irqa_ipl(dsp56156_core* cpustate);
int8_t irqb_ipl(dsp56156_core* cpustate);
uint8_t irqa_trigger(dsp56156_core* cpustate);
uint8_t irqb_trigger(dsp56156_core* cpustate);
int8_t codec_ipl(dsp56156_core* cpustate);
int8_t host_ipl(dsp56156_core* cpustate);
int8_t ssi0_ipl(dsp56156_core* cpustate);
int8_t ssi1_ipl(dsp56156_core* cpustate);
int8_t tm_ipl(dsp56156_core* cpustate);
/***************************************************************************
HOST INTERFACE
***************************************************************************/
void dsp56156_host_interface_reset(dsp56156_core* cpustate);
#define HTX (HTXHRX)
#define HRX (HTXHRX)
#define ICR (cpustate->HI.icr)
#define CVR (cpustate->HI.cvr)
#define ISR (cpustate->HI.isr)
#define IVR (cpustate->HI.ivr)
#define TXH (cpustate->HI.trxh)
#define TXL (cpustate->HI.trxl)
#define RXH (cpustate->HI.trxh)
#define RXL (cpustate->HI.trxl)
/*****************/
/* DSP56156 SIDE */
/*****************/
/* Host Control Register (HCR) Bits */
void HCR_set(dsp56156_core* cpustate, uint16_t value);
//uint16_t HF3_bit(dsp56156_core* cpustate); #define hf3BIT ((HCR & 0x0010) != 0)
//uint16_t HF2_bit(dsp56156_core* cpustate); #define hf2BIT ((HCR & 0x0008) != 0)
uint16_t HCIE_bit(dsp56156_core* cpustate);
uint16_t HTIE_bit(dsp56156_core* cpustate);
uint16_t HRIE_bit(dsp56156_core* cpustate);
void HF3_bit_set(dsp56156_core* cpustate, uint16_t value);
void HF2_bit_set(dsp56156_core* cpustate, uint16_t value);
void HCIE_bit_set(dsp56156_core* cpustate, uint16_t value);
void HTIE_bit_set(dsp56156_core* cpustate, uint16_t value);
void HRIE_bit_set(dsp56156_core* cpustate, uint16_t value);
/* Host Status Register (HSR) Bits */
//void HSR_set(dsp56156_core* cpustate, uint16_t value);
//uint16_t DMA_bit(dsp56156_core* cpustate); #define dmaBIT ((HSR & 0x0080) != 0)
//uint16_t HF1_bit(dsp56156_core* cpustate); #define hf1BIT ((HSR & 0x0010) != 0)
//uint16_t HF0_bit(dsp56156_core* cpustate); #define hf0BIT ((HSR & 0x0008) != 0)
//uint16_t HCP_bit(dsp56156_core* cpustate); #define hcpBIT ((HSR & 0x0004) != 0)
uint16_t HTDE_bit(dsp56156_core* cpustate);
uint16_t HRDF_bit(dsp56156_core* cpustate);
void DMA_bit_set(dsp56156_core* cpustate, uint16_t value);
void HF1_bit_set(dsp56156_core* cpustate, uint16_t value);
void HF0_bit_set(dsp56156_core* cpustate, uint16_t value);
void HCP_bit_set(dsp56156_core* cpustate, uint16_t value);
void HTDE_bit_set(dsp56156_core* cpustate, uint16_t value);
void HRDF_bit_set(dsp56156_core* cpustate, uint16_t value);
/*************/
/* HOST SIDE */
/*************/
/* Interrupt Control Register (ICR) Bits */
void ICR_set(dsp56156_core* cpustate, uint8_t value);
//uint8_t INIT_bit(dsp56156_core* cpustate); #define x_initBIT ((dsp56156.HI.ICR & 0x0080) != 0)
//uint8_t HM1_bit(dsp56156_core* cpustate); #define x_hm1BIT ((dsp56156.HI.ICR & 0x0040) != 0)
//uint8_t HM0_bit(dsp56156_core* cpustate); #define x_hm0BIT ((dsp56156.HI.ICR & 0x0020) != 0)
//uint8_t HF1_bit_host(dsp56156_core* cpustate); #define x_hf1BIT ((dsp56156.HI.ICR & 0x0010) != 0)
//uint8_t HF0_bit_host(dsp56156_core* cpustate); #define x_hf0BIT ((dsp56156.HI.ICR & 0x0008) != 0)
//uint8_t TREQ_bit(dsp56156_core* cpustate); #define x_treqBIT ((dsp56156.HI.ICR & 0x0002) != 0)
//uint8_t RREQ_bit(dsp56156_core* cpustate); #define x_rreqBIT ((dsp56156.HI.ICR & 0x0001) != 0)
//void INIT_bit_set(dsp56156_core* cpustate, uint8_t value); #define CLEAR_x_initBIT() (dsp56156.HI.ICR &= (~0x0080))
//void HM1_bit_set(dsp56156_core* cpustate, uint8_t value); #define CLEAR_x_hm1BIT() (dsp56156.HI.ICR &= (~0x0040))
//void HM0_bit_set(dsp56156_core* cpustate, uint8_t value); #define CLEAR_x_hm0BIT() (dsp56156.HI.ICR &= (~0x0020))
void HF1_bit_host_set(dsp56156_core* cpustate, uint8_t value);
void HF0_bit_host_set(dsp56156_core* cpustate, uint8_t value);
void TREQ_bit_set(dsp56156_core* cpustate, uint8_t value);
void RREQ_bit_set(dsp56156_core* cpustate, uint8_t value);
/* Command Vector Register (CVR) Bits */
void CVR_set(dsp56156_core* cpustate, uint8_t value);
//uint8_t HC_bit();
uint8_t HV_bits(dsp56156_core* cpustate);
void HC_bit_set(dsp56156_core* cpustate, uint8_t value);
void HV_bits_set(dsp56156_core* cpustate, uint8_t value);
/* Interrupt Status Register (ISR) Bits */
// void ISR_set(dsp56156_core* cpustate, uint8_t value);
//uint8_t HREQ_bit(dsp56156_core* cpustate); #define x_hreqBIT ((dsp56156.HI.ISR & 0x0080) != 0)
//uint8_t DMA_bit(dsp56156_core* cpustate); #define x_dmaBIT ((dsp56156.HI.ISR & 0x0040) != 0)
//uint8_t HF3_bit_host(dsp56156_core* cpustate); #define x_hf3BIT ((dsp56156.HI.ISR & 0x0010) != 0)
//uint8_t HF2_bit_host(dsp56156_core* cpustate); #define x_hf2BIT ((dsp56156.HI.ISR & 0x0008) != 0)
//uint8_t TRDY_bit(dsp56156_core* cpustate); #define x_trdyBIT ((dsp56156.HI.ISR & 0x0004) != 0)
uint8_t TXDE_bit(dsp56156_core* cpustate);
uint8_t RXDF_bit(dsp56156_core* cpustate);
//void HREQ_bit_set(dsp56156_core* cpustate, uint8_t value); #define CLEAR_x_hreqBIT() (dsp56156.HI.ISR &= (~0x0080))
//void DMA_bit_set(dsp56156_core* cpustate, uint8_t value); #define CLEAR_x_dmaBIT() (dsp56156.HI.ISR &= (~0x0040))
void HF3_bit_host_set(dsp56156_core* cpustate, uint8_t value);
void HF2_bit_host_set(dsp56156_core* cpustate, uint8_t value);
//void TRDY_bit_set(dsp56156_core* cpustate, uint8_t value); #define CLEAR_x_trdyBIT() (dsp56156.HI.ISR &= (~0x0004))
void TXDE_bit_set(dsp56156_core* cpustate, uint8_t value);
void RXDF_bit_set(dsp56156_core* cpustate, uint8_t value);
/* Interrupt Vector Register (IVR) Bits */
//void IVR_set(dsp56156_core* cpustate, uint8_t value);
//uint8_t IV7_bit(dsp56156_core* cpustate);
//uint8_t IV6_bit(dsp56156_core* cpustate);
//uint8_t IV5_bit(dsp56156_core* cpustate);
//uint8_t IV4_bit(dsp56156_core* cpustate);
//uint8_t IV3_bit(dsp56156_core* cpustate);
//uint8_t IV2_bit(dsp56156_core* cpustate);
//uint8_t IV1_bit(dsp56156_core* cpustate);
//uint8_t IV0_bit(dsp56156_core* cpustate);
//void IV7_bit_set(dsp56156_core* cpustate, uint8_t value);
//void IV6_bit_set(dsp56156_core* cpustate, uint8_t value);
//void IV5_bit_set(dsp56156_core* cpustate, uint8_t value);
//void IV4_bit_set(dsp56156_core* cpustate, uint8_t value);
//void IV3_bit_set(dsp56156_core* cpustate, uint8_t value);
//void IV2_bit_set(dsp56156_core* cpustate, uint8_t value);
//void IV1_bit_set(dsp56156_core* cpustate, uint8_t value);
//void IV0_bit_set(dsp56156_core* cpustate, uint8_t value);
/* PROTOTYPES */
void dsp56156_host_interface_HTX_to_host(dsp56156_core* cpustate);
void dsp56156_host_interface_host_to_HTX(dsp56156_core* cpustate);
/***************************************************************************
I/O INTERFACE
***************************************************************************/
void dsp56156_io_reset(dsp56156_core* cpustate);
/* Port A Bus Control Register (BCR) */
void BCR_set(dsp56156_core* cpustate, uint16_t value);
//uint16_t RH_bit(dsp56156_core* cpustate);
//uint16_t BS_bit(dsp56156_core* cpustate);
//uint16_t external_x_wait_states(dsp56156_core* cpustate);
//uint16_t external_p_wait_states(dsp56156_core* cpustate);
void RH_bit_set(dsp56156_core* cpustate, uint16_t value);
void BS_bit_set(dsp56156_core* cpustate, uint16_t value);
void external_x_wait_states_set(dsp56156_core* cpustate, uint16_t value);
void external_p_wait_states_set(dsp56156_core* cpustate, uint16_t value);
/* Port B Control Register (PBC) */
void PBC_set(dsp56156_core* cpustate, uint16_t value);
//int host_interface_active(dsp56156_core* cpustate);
/* Port B Data Direction Register (PBDDR) */
void PBDDR_set(dsp56156_core* cpustate, uint16_t value);
/* Port B Data Register (PBD) */
void PBD_set(dsp56156_core* cpustate, uint16_t value);
/* Port C Control Register (PCC) */
void PCC_set(dsp56156_core* cpustate, uint16_t value);
/* Port C Data Direction Register (PCDDR) */
void PCDDR_set(dsp56156_core* cpustate, uint16_t value);
/* Port C Dtaa Register (PCD) */
void PCD_set(dsp56156_core* cpustate, uint16_t value);
} // namespace DSP_56156
#endif // MAME_CPU_DSP56156_DSP56MEM_H

1172
src/devices/cpu/dsp56k/dsp56ops.hxx → src/devices/cpu/dsp56156/dsp56ops.hxx
View File

File diff suppressed because it is too large Load Diff

222
src/devices/cpu/dsp56k/dsp56pcu.cpp → src/devices/cpu/dsp56156/dsp56pcu.cpp
View File

@ -4,7 +4,7 @@
#include "dsp56pcu.h"
#include "dsp56mem.h"
namespace DSP56K
namespace DSP_56156
{
/* ************************************************************************* */
/* Status Register */
@ -15,34 +15,34 @@ namespace DSP56K
/* |-------------------------------------| |-------------------------------| */
/* */
/* ************************************************************************* */
uint8_t LF_bit(const dsp56k_core* cpustate) { return (SR & 0x8000) >> 15; }
uint8_t FV_bit(const dsp56k_core* cpustate) { return (SR & 0x4000) >> 14; }
// uint8_t S_bits(const dsp56k_core* cpustate) { return (SR & 0x0c00) >> 10; }
uint8_t I_bits(const dsp56k_core* cpustate) { return (SR & 0x0300) >> 8; }
uint8_t S_bit (const dsp56k_core* cpustate) { return (SR & 0x0080) >> 7; }
uint8_t L_bit (const dsp56k_core* cpustate) { return (SR & 0x0040) >> 6; }
uint8_t E_bit (const dsp56k_core* cpustate) { return (SR & 0x0020) >> 5; }
uint8_t U_bit (const dsp56k_core* cpustate) { return (SR & 0x0010) >> 4; }
uint8_t N_bit (const dsp56k_core* cpustate) { return (SR & 0x0008) >> 3; }
uint8_t Z_bit (const dsp56k_core* cpustate) { return (SR & 0x0004) >> 2; }
uint8_t V_bit (const dsp56k_core* cpustate) { return (SR & 0x0002) >> 1; }
uint8_t C_bit (const dsp56k_core* cpustate) { return (SR & 0x0001) >> 0; }
uint8_t LF_bit(const dsp56156_core* cpustate) { return (SR & 0x8000) >> 15; }
uint8_t FV_bit(const dsp56156_core* cpustate) { return (SR & 0x4000) >> 14; }
// uint8_t S_bits(const dsp56156_core* cpustate) { return (SR & 0x0c00) >> 10; }
uint8_t I_bits(const dsp56156_core* cpustate) { return (SR & 0x0300) >> 8; }
uint8_t S_bit (const dsp56156_core* cpustate) { return (SR & 0x0080) >> 7; }
uint8_t L_bit (const dsp56156_core* cpustate) { return (SR & 0x0040) >> 6; }
uint8_t E_bit (const dsp56156_core* cpustate) { return (SR & 0x0020) >> 5; }
uint8_t U_bit (const dsp56156_core* cpustate) { return (SR & 0x0010) >> 4; }
uint8_t N_bit (const dsp56156_core* cpustate) { return (SR & 0x0008) >> 3; }
uint8_t Z_bit (const dsp56156_core* cpustate) { return (SR & 0x0004) >> 2; }
uint8_t V_bit (const dsp56156_core* cpustate) { return (SR & 0x0002) >> 1; }
uint8_t C_bit (const dsp56156_core* cpustate) { return (SR & 0x0001) >> 0; }
/* MR setters */
void LF_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x8000); else (SR &= (~0x8000)); }
void FV_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x4000); else (SR &= (~0x4000)); }
void S_bits_set(dsp56k_core* cpustate, uint8_t value) { value = value & 0x03; SR &= ~(0x0c00); SR |= (value << 10); }
void I_bits_set(dsp56k_core* cpustate, uint8_t value) { value = value & 0x03; SR &= ~(0x0300); SR |= (value << 8); }
void LF_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (SR |= 0x8000); else (SR &= (~0x8000)); }
void FV_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (SR |= 0x4000); else (SR &= (~0x4000)); }
void S_bits_set(dsp56156_core* cpustate, uint8_t value) { value = value & 0x03; SR &= ~(0x0c00); SR |= (value << 10); }
void I_bits_set(dsp56156_core* cpustate, uint8_t value) { value = value & 0x03; SR &= ~(0x0300); SR |= (value << 8); }
/* CCR setters */
void S_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x0080); else (SR &= (~0x0080)); }
void L_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x0040); else (SR &= (~0x0040)); }
void E_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x0020); else (SR &= (~0x0020)); }
void U_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x0010); else (SR &= (~0x0010)); }
void N_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x0008); else (SR &= (~0x0008)); }
void Z_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x0004); else (SR &= (~0x0004)); }
void V_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x0002); else (SR &= (~0x0002)); }
void C_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x0001); else (SR &= (~0x0001)); }
void S_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (SR |= 0x0080); else (SR &= (~0x0080)); }
void L_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (SR |= 0x0040); else (SR &= (~0x0040)); }
void E_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (SR |= 0x0020); else (SR &= (~0x0020)); }
void U_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (SR |= 0x0010); else (SR &= (~0x0010)); }
void N_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (SR |= 0x0008); else (SR &= (~0x0008)); }
void Z_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (SR |= 0x0004); else (SR &= (~0x0004)); }
void V_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (SR |= 0x0002); else (SR &= (~0x0002)); }
void C_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (SR |= 0x0001); else (SR &= (~0x0001)); }
@ -55,23 +55,23 @@ void C_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (SR |= 0x0001)
/* |---------------------------------------------------------------------| */
/* */
/* ************************************************************************* */
// uint8_t CD_bit(const dsp56k_core* cpustate) { return ((OMR & 0x0080) != 0); }
// uint8_t SD_bit(const dsp56k_core* cpustate) { return ((OMR & 0x0040) != 0); }
// uint8_t R_bit(const dsp56k_core* cpustate) { return ((OMR & 0x0020) != 0); }
// uint8_t SA_bit(const dsp56k_core* cpustate) { return ((OMR & 0x0010) != 0); }
// uint8_t MC_bit(const dsp56k_core* cpustate) { return ((OMR & 0x0004) != 0); }
uint8_t MB_bit(const dsp56k_core* cpustate) { return ((OMR & 0x0002) != 0); }
uint8_t MA_bit(const dsp56k_core* cpustate) { return ((OMR & 0x0001) != 0); }
// uint8_t CD_bit(const dsp56156_core* cpustate) { return ((OMR & 0x0080) != 0); }
// uint8_t SD_bit(const dsp56156_core* cpustate) { return ((OMR & 0x0040) != 0); }
// uint8_t R_bit(const dsp56156_core* cpustate) { return ((OMR & 0x0020) != 0); }
// uint8_t SA_bit(const dsp56156_core* cpustate) { return ((OMR & 0x0010) != 0); }
// uint8_t MC_bit(const dsp56156_core* cpustate) { return ((OMR & 0x0004) != 0); }
uint8_t MB_bit(const dsp56156_core* cpustate) { return ((OMR & 0x0002) != 0); }
uint8_t MA_bit(const dsp56156_core* cpustate) { return ((OMR & 0x0001) != 0); }
void CD_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0080); else (OMR &= (~0x0080)); }
void SD_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0040); else (OMR &= (~0x0040)); }
void R_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0020); else (OMR &= (~0x0020)); }
void SA_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0010); else (OMR &= (~0x0010)); }
void MC_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0004); else (OMR &= (~0x0004)); }
void MB_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0002); else (OMR &= (~0x0002)); }
void MA_bit_set(dsp56k_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0001); else (OMR &= (~0x0001)); }
void CD_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0080); else (OMR &= (~0x0080)); }
void SD_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0040); else (OMR &= (~0x0040)); }
void R_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0020); else (OMR &= (~0x0020)); }
void SA_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0010); else (OMR &= (~0x0010)); }
void MC_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0004); else (OMR &= (~0x0004)); }
void MB_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0002); else (OMR &= (~0x0002)); }
void MA_bit_set(dsp56156_core* cpustate, uint8_t value) { if (value) (OMR |= 0x0001); else (OMR &= (~0x0001)); }
uint8_t dsp56k_operating_mode(const dsp56k_core* cpustate)
uint8_t dsp56156_operating_mode(const dsp56156_core* cpustate)
{
return ((MB_bit(cpustate) << 1) | MA_bit(cpustate));
}
@ -87,23 +87,23 @@ uint8_t dsp56k_operating_mode(const dsp56k_core* cpustate)
/* |---------------------------------------------------------------------| */
/* */
/* ************************************************************************* */
uint8_t UF_bit(const dsp56k_core* cpustate) { return ((SP & 0x0020) != 0); }
uint8_t SE_bit(const dsp56k_core* cpustate) { return ((SP & 0x0010) != 0); }
uint8_t UF_bit(const dsp56156_core* cpustate) { return ((SP & 0x0020) != 0); }
uint8_t SE_bit(const dsp56156_core* cpustate) { return ((SP & 0x0010) != 0); }
//void UF_bit_set(dsp56k_core* cpustate, uint8_t value) {};
//void SE_bit_set(dsp56k_core* cpustate, uint8_t value) {};
//void UF_bit_set(dsp56156_core* cpustate, uint8_t value) {};
//void SE_bit_set(dsp56156_core* cpustate, uint8_t value) {};
/***************************************************************************
INITIALIZATION AND RESET
***************************************************************************/
void pcu_init(dsp56k_core* cpustate, device_t *device)
void pcu_init(dsp56156_core* cpustate, device_t *device)
{
/* Init the irq table */
dsp56k_irq_table_init();
dsp56156_irq_table_init();
/* save states - dsp56k_pcu members */
/* save states - dsp56156_pcu members */
device->save_item(NAME(cpustate->PCU.pc));
device->save_item(NAME(cpustate->PCU.la));
device->save_item(NAME(cpustate->PCU.lc));
@ -115,7 +115,7 @@ void pcu_init(dsp56k_core* cpustate, device_t *device)
device->save_item(NAME(cpustate->PCU.reset_vector));
}
void pcu_reset(dsp56k_core* cpustate)
void pcu_reset(dsp56156_core* cpustate)
{
int i;
@ -125,10 +125,10 @@ void pcu_reset(dsp56k_core* cpustate)
MC_bit_set(cpustate, cpustate->modC_state);
/* Reset based on the operating mode. */
switch(dsp56k_operating_mode(cpustate))
switch(dsp56156_operating_mode(cpustate))
{
case 0x00:
cpustate->device->logerror("Dsp56k in Special Bootstrap Mode 1\n");
cpustate->device->logerror("Dsp56156 in Special Bootstrap Mode 1\n");
/* HACK - We don't need to put the bootstrap mode on here since */
/* we'll simulate it entirely in this function */
@ -161,7 +161,7 @@ void pcu_reset(dsp56k_core* cpustate)
break;
case 0x01:
cpustate->device->logerror("Dsp56k in Special Bootstrap Mode 2\n");
cpustate->device->logerror("Dsp56156 in Special Bootstrap Mode 2\n");
/* HACK - Turn bootstrap mode on. This hijacks the CPU execute loop and lets */
/* Either the host interface or the SSIO interface suck in all the data */
@ -171,12 +171,12 @@ void pcu_reset(dsp56k_core* cpustate)
if (cpustate->program->read_word(0xc000<<1) & 0x8000)
{
cpustate->bootstrap_mode = BOOTSTRAP_SSIX;
cpustate->device->logerror("DSP56k : Currently in (hacked) bootstrap mode - reading from SSIx.\n");
cpustate->device->logerror("DSP56156 : Currently in (hacked) bootstrap mode - reading from SSIx.\n");
}
else
{
cpustate->bootstrap_mode = BOOTSTRAP_HI;
cpustate->device->logerror("DSP56k : Currently in (hacked) bootstrap mode - reading from Host Interface.\n");
cpustate->device->logerror("DSP56156 : Currently in (hacked) bootstrap mode - reading from Host Interface.\n");
}
/* HACK - Set the PC to 0x0000 as per the boot ROM. */
@ -189,13 +189,13 @@ void pcu_reset(dsp56k_core* cpustate)
break;
case 0x02:
cpustate->device->logerror("Dsp56k in Normal Expanded Mode\n");
cpustate->device->logerror("Dsp56156 in Normal Expanded Mode\n");
PC = 0xe000;
cpustate->PCU.reset_vector = 0xe000;
break;
case 0x03:
cpustate->device->logerror("Dsp56k in Development Expanded Mode\n");
cpustate->device->logerror("Dsp56156 in Development Expanded Mode\n");
/* TODO: Disable internal ROM, etc. Likely a tricky thing for MAME? */
PC = 0x0000;
cpustate->PCU.reset_vector = 0x0000;
@ -232,33 +232,33 @@ void pcu_reset(dsp56k_core* cpustate)
CD_bit_set(cpustate, 0);
/* Clear out the pending interrupt list */
dsp56k_clear_pending_interrupts(cpustate);
dsp56156_clear_pending_interrupts(cpustate);
}
/***************************************************************************
INTERRUPT HANDLING
***************************************************************************/
struct dsp56k_irq_data
struct dsp56156_irq_data
{
uint16_t irq_vector;
char irq_source[128];
};
dsp56k_irq_data dsp56k_interrupt_sources[32];
dsp56156_irq_data dsp56156_interrupt_sources[32];
/* TODO: Figure out how to switch on level versus edge-triggered. */
void pcu_service_interrupts(dsp56k_core* cpustate)
void pcu_service_interrupts(dsp56156_core* cpustate)
{
int i;
/* Count list of pending interrupts */
int num_servicable = dsp56k_count_pending_interrupts(cpustate);
int num_servicable = dsp56156_count_pending_interrupts(cpustate);
if (num_servicable == 0)
return;
/* Sort list according to priority */
dsp56k_sort_pending_interrupts(cpustate, num_servicable);
dsp56156_sort_pending_interrupts(cpustate, num_servicable);
/* Service each interrupt in order */
/* TODO: This just *can't* be right :) */
@ -267,7 +267,7 @@ void pcu_service_interrupts(dsp56k_core* cpustate)
const int interrupt_index = cpustate->PCU.pending_interrupts[i];
/* Get the priority of the interrupt - a return value of -1 means disabled! */
int8_t priority = dsp56k_get_irq_priority(cpustate, interrupt_index);
int8_t priority = dsp56156_get_irq_priority(cpustate, interrupt_index);
/* 1-12 Make sure you're not masked out against the Interrupt Mask Bits (disabled is handled for free here) */
if (priority >= I_bits(cpustate))
@ -279,7 +279,7 @@ void pcu_service_interrupts(dsp56k_core* cpustate)
if (interrupt_index != 22)
{
/* Execute a normal interrupt */
PC = dsp56k_interrupt_sources[interrupt_index].irq_vector;
PC = dsp56156_interrupt_sources[interrupt_index].irq_vector;
}
else
{
@ -294,15 +294,15 @@ void pcu_service_interrupts(dsp56k_core* cpustate)
}
}
dsp56k_clear_pending_interrupts(cpustate);
dsp56156_clear_pending_interrupts(cpustate);
}
/* Register an interrupt */
void dsp56k_add_pending_interrupt(dsp56k_core* cpustate, const char* name)
void dsp56156_add_pending_interrupt(dsp56156_core* cpustate, const char* name)
{
int i;
int irq_index = dsp56k_get_irq_index_by_tag(name);
int irq_index = dsp56156_get_irq_index_by_tag(name);
for (i = 0; i < 32; i++)
{
@ -315,54 +315,54 @@ void dsp56k_add_pending_interrupt(dsp56k_core* cpustate, const char* name)
}
/* Utility function to construct IRQ table */
void dsp56k_set_irq_source(uint8_t irq_num, uint16_t iv, const char* source)
void dsp56156_set_irq_source(uint8_t irq_num, uint16_t iv, const char* source)
{
dsp56k_interrupt_sources[irq_num].irq_vector = iv;
strcpy(dsp56k_interrupt_sources[irq_num].irq_source, source);
dsp56156_interrupt_sources[irq_num].irq_vector = iv;
strcpy(dsp56156_interrupt_sources[irq_num].irq_source, source);
}
/* Construct a table containing pertient IRQ information */
void dsp56k_irq_table_init(void)
void dsp56156_irq_table_init(void)
{
/* 1-14 + 1-18 */
/* TODO: Cull host command stuff appropriately */
/* array index . vector . token */
dsp56k_set_irq_source(0, 0x0000, "Hardware RESET");
dsp56k_set_irq_source(1, 0x0002, "Illegal Instruction");
dsp56k_set_irq_source(2, 0x0004, "Stack Error");
dsp56k_set_irq_source(3, 0x0006, "Reserved");
dsp56k_set_irq_source(4, 0x0008, "SWI");
dsp56k_set_irq_source(5, 0x000a, "IRQA");
dsp56k_set_irq_source(6, 0x000c, "IRQB");
dsp56k_set_irq_source(7, 0x000e, "Reserved");
dsp56k_set_irq_source(8, 0x0010, "SSI0 Receive Data with Exception");
dsp56k_set_irq_source(9, 0x0012, "SSI0 Receive Data");
dsp56k_set_irq_source(10, 0x0014, "SSI0 Transmit Data with Exception");
dsp56k_set_irq_source(11, 0x0016, "SSI0 Transmit Data");
dsp56k_set_irq_source(12, 0x0018, "SSI1 Receive Data with Exception");
dsp56k_set_irq_source(13, 0x001a, "SSI1 Receive Data");
dsp56k_set_irq_source(14, 0x001c, "SSI1 Transmit Data with Exception");
dsp56k_set_irq_source(15, 0x001e, "SSI1 Transmit Data");
dsp56k_set_irq_source(16, 0x0020, "Timer Overflow");
dsp56k_set_irq_source(17, 0x0022, "Timer Compare");
dsp56k_set_irq_source(18, 0x0024, "Host DMA Receive Data");
dsp56k_set_irq_source(19, 0x0026, "Host DMA Transmit Data");
dsp56k_set_irq_source(20, 0x0028, "Host Receive Data");
dsp56k_set_irq_source(21, 0x002a, "Host Transmit Data");
dsp56k_set_irq_source(22, 0x002c, "Host Command"); /* Default vector for the host command */
dsp56k_set_irq_source(23, 0x002e, "Codec Receive/Transmit");
dsp56k_set_irq_source(24, 0x0030, "Host Command 1");
dsp56k_set_irq_source(25, 0x0032, "Host Command 2");
dsp56k_set_irq_source(26, 0x0034, "Host Command 3");
dsp56k_set_irq_source(27, 0x0036, "Host Command 4");
dsp56k_set_irq_source(28, 0x0038, "Host Command 5");
dsp56k_set_irq_source(29, 0x003a, "Host Command 6");
dsp56k_set_irq_source(30, 0x003c, "Host Command 7");
dsp56k_set_irq_source(31, 0x003e, "Host Command 8");
dsp56156_set_irq_source(0, 0x0000, "Hardware RESET");
dsp56156_set_irq_source(1, 0x0002, "Illegal Instruction");
dsp56156_set_irq_source(2, 0x0004, "Stack Error");
dsp56156_set_irq_source(3, 0x0006, "Reserved");
dsp56156_set_irq_source(4, 0x0008, "SWI");
dsp56156_set_irq_source(5, 0x000a, "IRQA");
dsp56156_set_irq_source(6, 0x000c, "IRQB");
dsp56156_set_irq_source(7, 0x000e, "Reserved");
dsp56156_set_irq_source(8, 0x0010, "SSI0 Receive Data with Exception");
dsp56156_set_irq_source(9, 0x0012, "SSI0 Receive Data");
dsp56156_set_irq_source(10, 0x0014, "SSI0 Transmit Data with Exception");
dsp56156_set_irq_source(11, 0x0016, "SSI0 Transmit Data");
dsp56156_set_irq_source(12, 0x0018, "SSI1 Receive Data with Exception");
dsp56156_set_irq_source(13, 0x001a, "SSI1 Receive Data");
dsp56156_set_irq_source(14, 0x001c, "SSI1 Transmit Data with Exception");
dsp56156_set_irq_source(15, 0x001e, "SSI1 Transmit Data");
dsp56156_set_irq_source(16, 0x0020, "Timer Overflow");
dsp56156_set_irq_source(17, 0x0022, "Timer Compare");
dsp56156_set_irq_source(18, 0x0024, "Host DMA Receive Data");
dsp56156_set_irq_source(19, 0x0026, "Host DMA Transmit Data");
dsp56156_set_irq_source(20, 0x0028, "Host Receive Data");
dsp56156_set_irq_source(21, 0x002a, "Host Transmit Data");
dsp56156_set_irq_source(22, 0x002c, "Host Command"); /* Default vector for the host command */
dsp56156_set_irq_source(23, 0x002e, "Codec Receive/Transmit");
dsp56156_set_irq_source(24, 0x0030, "Host Command 1");
dsp56156_set_irq_source(25, 0x0032, "Host Command 2");
dsp56156_set_irq_source(26, 0x0034, "Host Command 3");
dsp56156_set_irq_source(27, 0x0036, "Host Command 4");
dsp56156_set_irq_source(28, 0x0038, "Host Command 5");
dsp56156_set_irq_source(29, 0x003a, "Host Command 6");
dsp56156_set_irq_source(30, 0x003c, "Host Command 7");
dsp56156_set_irq_source(31, 0x003e, "Host Command 8");
}
/* Clear all entries from the pending table */
void dsp56k_clear_pending_interrupts(dsp56k_core* cpustate)
void dsp56156_clear_pending_interrupts(dsp56156_core* cpustate)
{
int i;
for (i = 0; i < 32; i++)
@ -372,7 +372,7 @@ void dsp56k_clear_pending_interrupts(dsp56k_core* cpustate)
}
/* Recover number of pending irqs */
int dsp56k_count_pending_interrupts(dsp56k_core* cpustate)
int dsp56156_count_pending_interrupts(dsp56156_core* cpustate)
{
int numI = 0;
while (cpustate->PCU.pending_interrupts[numI] != -1)
@ -384,7 +384,7 @@ int dsp56k_count_pending_interrupts(dsp56k_core* cpustate)
}
/* Sort the pending irqs by priority */
void dsp56k_sort_pending_interrupts(dsp56k_core* cpustate, int num)
void dsp56156_sort_pending_interrupts(dsp56156_core* cpustate, int num)
{
int i, j;
@ -392,7 +392,7 @@ void dsp56k_sort_pending_interrupts(dsp56k_core* cpustate, int num)
int priority_list[32];
for (i = 0; i < num; i++)
{
priority_list[i] = dsp56k_get_irq_priority(cpustate, cpustate->PCU.pending_interrupts[i]);
priority_list[i] = dsp56156_get_irq_priority(cpustate, cpustate->PCU.pending_interrupts[i]);
}
/* Bubble sort should be good enough for us */
@ -421,7 +421,7 @@ void dsp56k_sort_pending_interrupts(dsp56k_core* cpustate, int num)
}
/* Given an index into the irq table, return the interrupt's current priority */
int8_t dsp56k_get_irq_priority(dsp56k_core* cpustate, int index)
int8_t dsp56156_get_irq_priority(dsp56156_core* cpustate, int index)
{
/* 1-12 */
switch (index)
@ -469,20 +469,20 @@ int8_t dsp56k_get_irq_priority(dsp56k_core* cpustate, int index)
}
/* Given an IRQ name, return its index in the irq table */
int dsp56k_get_irq_index_by_tag(const char* tag)
int dsp56156_get_irq_index_by_tag(const char* tag)
{
int i;
for (i = 0; i < 32; i++)
{
if (strcmp(tag, dsp56k_interrupt_sources[i].irq_source) == 0)
if (strcmp(tag, dsp56156_interrupt_sources[i].irq_source) == 0)
{
return i;
}
}
fatalerror("DSP56K ERROR : IRQ TAG specified incorrectly (get_vector_by_tag) : %s.\n", tag);
fatalerror("DSP56156 ERROR : IRQ TAG specified incorrectly (get_vector_by_tag) : %s.\n", tag);
// never executed
//return -1;
}
} // namespace DSP56K
} // namespace DSP_56156

150
src/devices/cpu/dsp56156/dsp56pcu.h Normal file
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@ -0,0 +1,150 @@
// license:BSD-3-Clause
// copyright-holders:Andrew Gardner
#ifndef DSP56156_PCU_H
#define DSP56156_PCU_H
#include "dsp56156.h"
namespace DSP_56156
{
/***************************************************************************
PCU
***************************************************************************/
void pcu_reset(dsp56156_core* cpustate);
void pcu_init(dsp56156_core* cpustate, device_t *device);
#define PC (cpustate->PCU.pc)
#define LA (cpustate->PCU.la)
#define LC (cpustate->PCU.lc)
#define SR (cpustate->PCU.sr)
#define OMR (cpustate->PCU.omr)
#define SP (cpustate->PCU.sp)
#define SS (cpustate->PCU.ss)
#define SSH (SS[SP].w.h)
#define SSL (SS[SP].w.l)
#define ST0 (SS[0].d)
#define ST1 (SS[1].d)
#define ST2 (SS[2].d)
#define ST3 (SS[3].d)
#define ST4 (SS[4].d)
#define ST5 (SS[5].d)
#define ST6 (SS[6].d)
#define ST7 (SS[7].d)
#define ST8 (SS[8].d)
#define ST9 (SS[9].d)
#define ST10 (SS[10].d)
#define ST11 (SS[11].d)
#define ST12 (SS[12].d)
#define ST13 (SS[13].d)
#define ST14 (SS[14].d)
#define ST15 (SS[15].d)
/* STATUS REGISTER (SR) BITS (1-25) */
/* MR */
uint8_t LF_bit(const dsp56156_core* cpustate);
uint8_t FV_bit(const dsp56156_core* cpustate);
//uint8_t S_bits(const dsp56156_core* cpustate);
uint8_t I_bits(const dsp56156_core* cpustate);
/* CCR - with macros for easy access */
#define S() (S_bit(cpustate))
uint8_t S_bit(const dsp56156_core* cpustate);
#define L() (L_bit(cpustate))
uint8_t L_bit(const dsp56156_core* cpustate);
#define E() (E_bit(cpustate))
uint8_t E_bit(const dsp56156_core* cpustate);
#define U() (U_bit(cpustate))
uint8_t U_bit(const dsp56156_core* cpustate);
#define N() (N_bit(cpustate))
uint8_t N_bit(const dsp56156_core* cpustate);
#define Z() (Z_bit(cpustate))
uint8_t Z_bit(const dsp56156_core* cpustate);
#define V() (V_bit(cpustate))
uint8_t V_bit(const dsp56156_core* cpustate);
#define C() (C_bit(cpustate))
uint8_t C_bit(const dsp56156_core* cpustate);
/* MR setters */
void LF_bit_set(dsp56156_core* cpustate, uint8_t value);
void FV_bit_set(dsp56156_core* cpustate, uint8_t value);
void S_bits_set(dsp56156_core* cpustate, uint8_t value);
void I_bits_set(dsp56156_core* cpustate, uint8_t value);
/* CCR setters - with macros for easy access */
#define DSP56156_S_SET() (S_bit_set(cpustate, 1))
#define DSP56156_S_CLEAR() (S_bit_set(cpustate, 0))
void S_bit_set(dsp56156_core* cpustate, uint8_t value);
#define DSP56156_L_SET() (L_bit_set(cpustate, 1))
#define DSP56156_L_CLEAR() (L_bit_set(cpustate, 0))
void L_bit_set(dsp56156_core* cpustate, uint8_t value);
#define DSP56156_E_SET() (E_bit_set(cpustate, 1))
#define DSP56156_E_CLEAR() (E_bit_set(cpustate, 0))
void E_bit_set(dsp56156_core* cpustate, uint8_t value);
#define DSP56156_U_SET() (U_bit_set(cpustate, 1))
#define DSP56156_U_CLEAR() (U_bit_set(cpustate, 0))
void U_bit_set(dsp56156_core* cpustate, uint8_t value);
#define DSP56156_N_SET() (N_bit_set(cpustate, 1))
#define DSP56156_N_CLEAR() (N_bit_set(cpustate, 0))
void N_bit_set(dsp56156_core* cpustate, uint8_t value);
#define DSP56156_Z_SET() (Z_bit_set(cpustate, 1))
#define DSP56156_Z_CLEAR() (Z_bit_set(cpustate, 0))
void Z_bit_set(dsp56156_core* cpustate, uint8_t value);
#define DSP56156_V_SET() (V_bit_set(cpustate, 1))
#define DSP56156_V_CLEAR() (V_bit_set(cpustate, 0))
void V_bit_set(dsp56156_core* cpustate, uint8_t value);
#define DSP56156_C_SET() (C_bit_set(cpustate, 1))
#define DSP56156_C_CLEAR() (C_bit_set(cpustate, 0))
void C_bit_set(dsp56156_core* cpustate, uint8_t value);
// TODO: Maybe some functions for Interrupt Mask and Scaling Mode go here?
/* 1-28 OPERATING MODE REGISTER (OMR) BITS */
//uint8_t CD_bit(const dsp56156_core* cpustate);
//uint8_t SD_bit(const dsp56156_core* cpustate);
//uint8_t R_bit(const dsp56156_core* cpustate);
//uint8_t SA_bit(const dsp56156_core* cpustate);
//uint8_t MC_bit(const dsp56156_core* cpustate);
uint8_t MB_bit(const dsp56156_core* cpustate);
uint8_t MA_bit(const dsp56156_core* cpustate);
void CD_bit_set(dsp56156_core* cpustate, uint8_t value);
void SD_bit_set(dsp56156_core* cpustate, uint8_t value);
void R_bit_set(dsp56156_core* cpustate, uint8_t value);
void SA_bit_set(dsp56156_core* cpustate, uint8_t value);
void MC_bit_set(dsp56156_core* cpustate, uint8_t value);
void MB_bit_set(dsp56156_core* cpustate, uint8_t value);
void MA_bit_set(dsp56156_core* cpustate, uint8_t value);
/* 1-27 STACK POINTER (SP) BITS */
uint8_t UF_bit(const dsp56156_core* cpustate);
uint8_t SE_bit(const dsp56156_core* cpustate);
//void UF_bit_set(dsp56156_core* cpustate, uint8_t value) {};
//void SE_bit_set(dsp56156_core* cpustate, uint8_t value) {};
// HACK - Bootstrap modes
#define BOOTSTRAP_OFF (0)
#define BOOTSTRAP_SSIX (1)
#define BOOTSTRAP_HI (2)
/* PCU IRQ goodies */
void pcu_service_interrupts(dsp56156_core* cpustate);
void dsp56156_irq_table_init(void);
void dsp56156_set_irq_source(uint8_t irq_num, uint16_t iv, const char* source);
int dsp56156_get_irq_index_by_tag(const char* tag);
void dsp56156_add_pending_interrupt(dsp56156_core* cpustate, const char* name); // Call me to add an interrupt to the queue
void dsp56156_clear_pending_interrupts(dsp56156_core* cpustate);
int dsp56156_count_pending_interrupts(dsp56156_core* cpustate);
void dsp56156_sort_pending_interrupts(dsp56156_core* cpustate, int num);
int8_t dsp56156_get_irq_priority(dsp56156_core* cpustate, int index);
} // namespace DSP_56156
#endif

2
src/devices/cpu/dsp56k/inst.cpp → src/devices/cpu/dsp56156/inst.cpp
View File

@ -4,7 +4,7 @@
#include "inst.h"
#include "emu.h"
namespace DSP56K
namespace DSP_56156
{
// Factory
std::unique_ptr<Instruction> Instruction::decodeInstruction(const Opcode* opc,

258
src/devices/cpu/dsp56k/inst.h → src/devices/cpu/dsp56156/inst.h
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File diff suppressed because it is too large Load Diff

4
src/devices/cpu/dsp56k/opcode.cpp → src/devices/cpu/dsp56156/opcode.cpp
View File

@ -5,7 +5,7 @@
#include "opcode.h"
namespace DSP56K
namespace DSP_56156
{
Opcode::Opcode(uint16_t w0, uint16_t w1) : m_word0(w0)/*, m_word1(w1)*/
{
@ -41,7 +41,7 @@ std::string Opcode::disassemble() const
}
void Opcode::evaluate(dsp56k_core* cpustate) const
void Opcode::evaluate(dsp56156_core* cpustate) const
{
if (m_instruction) m_instruction->evaluate(cpustate);
if (m_parallelMove) m_parallelMove->evaluate();

10
src/devices/cpu/dsp56k/opcode.h → src/devices/cpu/dsp56156/opcode.h
View File

@ -1,17 +1,17 @@
// license:BSD-3-Clause
// copyright-holders:Andrew Gardner
#ifndef __DSP56K_OPCODE_H__
#define __DSP56K_OPCODE_H__
#ifndef DSP56156_OPCODE_H
#define DSP56156_OPCODE_H
#include "inst.h"
#include "pmove.h"
#include "dsp56k.h"
#include "dsp56156.h"
//
// An Opcode contains an instruction and a parallel move operation.
//
namespace DSP56K
namespace DSP_56156
{
class Instruction;
class ParallelMove;
@ -23,7 +23,7 @@ public:
virtual ~Opcode();
std::string disassemble() const;
void evaluate(dsp56k_core* cpustate) const;
void evaluate(dsp56156_core* cpustate) const;
size_t size() const;
size_t evalSize() const;

2
src/devices/cpu/dsp56k/pmove.cpp → src/devices/cpu/dsp56156/pmove.cpp
View File

@ -3,7 +3,7 @@
#include "emu.h"
#include "pmove.h"
namespace DSP56K
namespace DSP_56156
{
const reg_id& ParallelMove::opSource() const { return m_oco->instSource(); }
const reg_id& ParallelMove::opDestination() const { return m_oco->instDestination(); }

6
src/devices/cpu/dsp56k/pmove.h → src/devices/cpu/dsp56156/pmove.h
View File

@ -1,7 +1,7 @@
// license:BSD-3-Clause
// copyright-holders:Andrew Gardner
#ifndef __DSP56K_PARALLEL_MOVE_H__
#define __DSP56K_PARALLEL_MOVE_H__
#ifndef DSP56156_PMOVE_H
#define DSP56156_PMOVE_H
#include "opcode.h"
#include "tables.h"
@ -9,7 +9,7 @@
//
// A ParallelMove Object is what all parallel move classes inherit from.
//
namespace DSP56K
namespace DSP_56156
{
class Opcode;

8
src/devices/cpu/dsp56k/tables.cpp → src/devices/cpu/dsp56156/tables.cpp
View File

@ -8,7 +8,7 @@
#include "tables.h"
#include "dsp56def.h"
namespace DSP56K
namespace DSP_56156
{
/******************/
/* Table decoding */
@ -655,7 +655,7 @@ int8_t get_6_bit_signed_value(uint16_t bits)
/* HELPER FUNCTIONS */
/********************/
uint16_t dsp56k_op_maskn(uint16_t cur, uint16_t mask)
uint16_t dsp56156_op_maskn(uint16_t cur, uint16_t mask)
{
int i;
@ -695,7 +695,7 @@ bool registerOverlap(const reg_id& r0, const size_t bmd, const reg_id& r1)
return false;
}
uint16_t regValue16(dsp56k_core* cpustate, const reg_id& reg)
uint16_t regValue16(dsp56156_core* cpustate, const reg_id& reg)
{
if (reg == iX0) return X0;
if (reg == iX1) return X1;
@ -726,7 +726,7 @@ uint16_t regValue16(dsp56k_core* cpustate, const reg_id& reg)
return 0xdead;
}
void setReg16(dsp56k_core* cpustate, const uint16_t& value, const reg_id& reg)
void setReg16(dsp56156_core* cpustate, const uint16_t& value, const reg_id& reg)
{
if (reg == iX0) X0 = value;
if (reg == iX1) X1 = value;

16
src/devices/cpu/dsp56k/tables.h → src/devices/cpu/dsp56156/tables.h
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@ -1,16 +1,16 @@
// license:BSD-3-Clause
// copyright-holders:Andrew Gardner
#ifndef __DSP56K_OPS_H__
#define __DSP56K_OPS_H__
#ifndef DSP56156_TABLES_H
#define DSP56156_TABLES_H
#include <stdio.h>
#include <stdlib.h>
#include "dsp56k.h"
#include "dsp56156.h"
namespace DSP56K
namespace DSP_56156
{
#define BITSn(CUR,MASK) (dsp56k_op_maskn(CUR,MASK))
#define BITSn(CUR,MASK) (dsp56156_op_maskn(CUR,MASK))
enum bitsModified {BM_NONE = 0x0, BM_LOW = 0x1, BM_MIDDLE = 0x2, BM_HIGH = 0x4};
@ -76,12 +76,12 @@ void assemble_address_from_IO_short_address(uint16_t pp, std::string& ea);
int8_t get_6_bit_signed_value(uint16_t bits);
// Helpers
uint16_t dsp56k_op_maskn(uint16_t cur, uint16_t mask);
uint16_t dsp56156_op_maskn(uint16_t cur, uint16_t mask);
bool registerOverlap(const reg_id& r0, const size_t bmd, const reg_id& r1);
uint16_t regValue16(dsp56k_core* cpustate, const reg_id& reg);
void setReg16(dsp56k_core* cpustate, const uint16_t& value, const reg_id& reg);
uint16_t regValue16(dsp56156_core* cpustate, const reg_id& reg);
void setReg16(dsp56156_core* cpustate, const uint16_t& value, const reg_id& reg);
std::string regIdAsString(const reg_id& regId);
std::string opMnemonicAsString(const op_mnem& mnem);

515
src/devices/cpu/dsp56k/dsp56k.cpp
View File

@ -1,515 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Andrew Gardner
/***************************************************************************
dsp56k.c
Core implementation for the portable DSP56k emulator.
Written by Andrew Gardner
****************************************************************************
Note:
This CPU emulator is very much a work-in-progress.
DONE:
1: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
11, , , , , , ,18, , ,
TODO:
X 1-6 Explore CORE naming scheme.
- 1-9 paragraph 1 : memory access timings
- 1-9 Data ALU arithmetic operations generally use fractional two's complement arithmetic
(Unsigned numbers are only supported by the multiply and multiply-accumulate instruction)
- 1-9 For fractional arithmetic, the 31-bit product is added to the 40-bit contents of A or B. No pipeline!
- 1-10 Two types of rounding: convergent rounding and two's complement rounding. See status register bit R.
- 1-10 Logic unit is 16-bits wide and works on MSP portion of accum register
- 1-10 The AGU can implement three types of arithmetic: linear, modulo, and reverse carry.
- 1-12 "Two external interrupt pins!!!"
- 1-12 Take care of all interrupt priority (IPR) stuff!
- 1-19 Memory WAIT states
- 1-20 The timer's interesting!
- 1-21 Vectored exception requests on the Host Interface!
***************************************************************************/
#include "emu.h"
#include "dsp56k.h"
#include "dsp56dsm.h"
#include "opcode.h"
#include "debugger.h"
#include "dsp56def.h"
/***************************************************************************
COMPONENT FUNCTIONALITY
***************************************************************************/
/* 1-9 ALU */
// #include "dsp56alu.h"
/* 1-10 Address Generation Unit (AGU) */
// #include "dsp56agu.h"
/* 1-11 Program Control Unit (PCU) */
#include "dsp56pcu.h"
/* 5-1 Host Interface (HI) */
//#include "dsp56hi.h"
/* 4-8 Memory handlers for on-chip peripheral memory. */
#include "dsp56mem.h"
DEFINE_DEVICE_TYPE_NS(DSP56156, DSP56K, dsp56k_device, "dsp56156", "Motorola DSP56156")
namespace DSP56K {
enum
{
// PCU
DSP56K_PC=1,
DSP56K_SR,
DSP56K_LC,
DSP56K_LA,
DSP56K_SP,
DSP56K_OMR,
// ALU
DSP56K_X, DSP56K_Y,
DSP56K_A, DSP56K_B,
// AGU
DSP56K_R0,DSP56K_R1,DSP56K_R2,DSP56K_R3,
DSP56K_N0,DSP56K_N1,DSP56K_N2,DSP56K_N3,
DSP56K_M0,DSP56K_M1,DSP56K_M2,DSP56K_M3,
DSP56K_TEMP,
DSP56K_STATUS,
// CPU STACK
DSP56K_ST0,
DSP56K_ST1,
DSP56K_ST2,
DSP56K_ST3,
DSP56K_ST4,
DSP56K_ST5,
DSP56K_ST6,
DSP56K_ST7,
DSP56K_ST8,
DSP56K_ST9,
DSP56K_ST10,
DSP56K_ST11,
DSP56K_ST12,
DSP56K_ST13,
DSP56K_ST14,
DSP56K_ST15
};
/****************************************************************************
* Internal Memory Maps
****************************************************************************/
void dsp56k_device::dsp56156_program_map(address_map &map)
{
map(0x0000, 0x07ff).ram().share("dsk56k_program_ram"); /* 1-5 */
// AM_RANGE(0x2f00,0x2fff) AM_ROM /* 1-5 PROM reserved memory. Is this the right spot for it? */
}
void dsp56k_device::dsp56156_x_data_map(address_map &map)
{
map(0x0000, 0x07ff).ram(); /* 1-5 */
map(0xffc0, 0xffff).rw(FUNC(dsp56k_device::peripheral_register_r), FUNC(dsp56k_device::peripheral_register_w)); /* 1-5 On-chip peripheral registers memory mapped in data space */
}
dsp56k_device::dsp56k_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: cpu_device(mconfig, DSP56156, tag, owner, clock)
, m_program_config("program", ENDIANNESS_LITTLE, 16, 16, -1, address_map_constructor(FUNC(dsp56k_device::dsp56156_program_map), this))
, m_data_config("data", ENDIANNESS_LITTLE, 16, 16, -1, address_map_constructor(FUNC(dsp56k_device::dsp56156_x_data_map), this))
, m_program_ram(*this, "dsk56k_program_ram")
{
}
device_memory_interface::space_config_vector dsp56k_device::memory_space_config() const
{
return space_config_vector {
std::make_pair(AS_PROGRAM, &m_program_config),
std::make_pair(AS_DATA, &m_data_config)
};
}
/***************************************************************************
MEMORY ACCESSORS
***************************************************************************/
#define ROPCODE(pc) cpustate->cache->read_word(pc)
/***************************************************************************
IRQ HANDLING
***************************************************************************/
void dsp56k_device::execute_set_input(int irqline, int state)
{
//logerror("DSP56k set irq line %d %d\n", irqline, state);
switch(irqline)
{
case DSP56K_IRQ_MODA:
// TODO: 1-12 Get this triggering right
if (irqa_trigger(&m_dsp56k_core))
logerror("DSP56k IRQA is set to fire on the \"Negative Edge\".\n");
if (state != CLEAR_LINE)
m_dsp56k_core.modA_state = true;
else
m_dsp56k_core.modA_state = false;
if (m_dsp56k_core.reset_state != true)
dsp56k_add_pending_interrupt(&m_dsp56k_core, "IRQA");
break;
case DSP56K_IRQ_MODB:
// TODO: 1-12 Get this triggering right
if (irqb_trigger(&m_dsp56k_core))
logerror("DSP56k IRQB is set to fire on the \"Negative Edge\".\n");
if (state != CLEAR_LINE)
m_dsp56k_core.modB_state = true;
else
m_dsp56k_core.modB_state = false;
if (m_dsp56k_core.reset_state != true)
dsp56k_add_pending_interrupt(&m_dsp56k_core, "IRQB");
break;
case DSP56K_IRQ_MODC:
if (state != CLEAR_LINE)
m_dsp56k_core.modC_state = true;
else
m_dsp56k_core.modC_state = false;
// TODO : Set bus mode or whatever
break;
case DSP56K_IRQ_RESET:
if (state != CLEAR_LINE)
m_dsp56k_core.reset_state = true;
else
{
/* If it changes state from asserted to cleared. Call the reset function. */
if (m_dsp56k_core.reset_state == true)
device_reset();
m_dsp56k_core.reset_state = false;
}
// dsp56k_add_pending_interrupt("Hardware RESET");
break;
default:
logerror("DSP56k setting some weird irq line : %d", irqline);
break;
}
/* If the reset line isn't asserted, service interrupts */
// TODO: Is it right to immediately service interrupts?
//if (cpustate->reset_state != true)
// pcu_service_interrupts();
}
/***************************************************************************
INITIALIZATION AND SHUTDOWN
***************************************************************************/
void dsp56k_device::agu_init()
{
/* save states - dsp56k_agu members */
save_item(NAME(m_dsp56k_core.AGU.r0));
save_item(NAME(m_dsp56k_core.AGU.r1));
save_item(NAME(m_dsp56k_core.AGU.r2));
save_item(NAME(m_dsp56k_core.AGU.r3));
save_item(NAME(m_dsp56k_core.AGU.n0));
save_item(NAME(m_dsp56k_core.AGU.n1));
save_item(NAME(m_dsp56k_core.AGU.n2));
save_item(NAME(m_dsp56k_core.AGU.n3));
save_item(NAME(m_dsp56k_core.AGU.m0));
save_item(NAME(m_dsp56k_core.AGU.m1));
save_item(NAME(m_dsp56k_core.AGU.m2));
save_item(NAME(m_dsp56k_core.AGU.m3));
save_item(NAME(m_dsp56k_core.AGU.temp));
}
void dsp56k_device::alu_init()
{
/* save states - dsp56k_alu members */
save_item(NAME(m_dsp56k_core.ALU.x));
save_item(NAME(m_dsp56k_core.ALU.y));
save_item(NAME(m_dsp56k_core.ALU.a));
save_item(NAME(m_dsp56k_core.ALU.b));
}
void dsp56k_device::device_start()
{
memset(&m_dsp56k_core, 0, sizeof(m_dsp56k_core));
m_dsp56k_core.device = this;
m_dsp56k_core.program_ram = m_program_ram;
/* Call specific module inits */
pcu_init(&m_dsp56k_core, this);
agu_init();
alu_init();
/* HACK - You're not in bootstrap mode upon bootup */
m_dsp56k_core.bootstrap_mode = BOOTSTRAP_OFF;
/* Clear the irq states */
m_dsp56k_core.modA_state = false;
m_dsp56k_core.modB_state = false;
m_dsp56k_core.modC_state = false;
m_dsp56k_core.reset_state = false;
/* save states - dsp56k_core members */
save_item(NAME(m_dsp56k_core.modA_state));
save_item(NAME(m_dsp56k_core.modB_state));
save_item(NAME(m_dsp56k_core.modC_state));
save_item(NAME(m_dsp56k_core.reset_state));
save_item(NAME(m_dsp56k_core.bootstrap_mode));
save_item(NAME(m_dsp56k_core.repFlag));
save_item(NAME(m_dsp56k_core.repAddr));
save_item(NAME(m_dsp56k_core.ppc));
save_item(NAME(m_dsp56k_core.op));
save_item(NAME(m_dsp56k_core.interrupt_cycles));
/* save states - dsp56k_host_interface members */
save_item(NAME(m_dsp56k_core.HI.icr));
save_item(NAME(m_dsp56k_core.HI.cvr));
save_item(NAME(m_dsp56k_core.HI.isr));
save_item(NAME(m_dsp56k_core.HI.ivr));
save_item(NAME(m_dsp56k_core.HI.trxh));
save_item(NAME(m_dsp56k_core.HI.trxl));
save_item(NAME(m_dsp56k_core.HI.bootstrap_offset));
save_item(NAME(m_dsp56k_core.peripheral_ram));
m_dsp56k_core.program = &space(AS_PROGRAM);
m_dsp56k_core.cache = m_dsp56k_core.program->cache<1, -1, ENDIANNESS_LITTLE>();
m_dsp56k_core.data = &space(AS_DATA);
state_add(DSP56K_PC, "PC", m_dsp56k_core.PCU.pc).formatstr("%04X");
state_add(DSP56K_SR, "SR", m_dsp56k_core.PCU.sr).formatstr("%04X");
state_add(DSP56K_LC, "LC", m_dsp56k_core.PCU.lc).formatstr("%04X");
state_add(DSP56K_LA, "LA", m_dsp56k_core.PCU.la).formatstr("%04X");
state_add(DSP56K_SP, "SP", m_dsp56k_core.PCU.sp).formatstr("%02X");
state_add(DSP56K_OMR, "OMR", m_dsp56k_core.PCU.omr).formatstr("%02X");
state_add(DSP56K_X, "X", m_dsp56k_core.ALU.x.d).mask(0xffffffff).formatstr("%9s");
state_add(DSP56K_Y, "Y", m_dsp56k_core.ALU.y.d).mask(0xffffffff).formatstr("%9s");
state_add(DSP56K_A, "A", m_dsp56k_core.ALU.a.q).mask(u64(0xffffffffffffffffU)).formatstr("%12s"); /* could benefit from a better mask? */
state_add(DSP56K_B, "B", m_dsp56k_core.ALU.b.q).mask(u64(0xffffffffffffffffU)).formatstr("%12s"); /* could benefit from a better mask? */
state_add(DSP56K_R0, "R0", m_dsp56k_core.AGU.r0).formatstr("%04X");
state_add(DSP56K_R1, "R1", m_dsp56k_core.AGU.r1).formatstr("%04X");
state_add(DSP56K_R2, "R2", m_dsp56k_core.AGU.r2).formatstr("%04X");
state_add(DSP56K_R3, "R3", m_dsp56k_core.AGU.r3).formatstr("%04X");
state_add(DSP56K_N0, "N0", m_dsp56k_core.AGU.n0).formatstr("%04X");
state_add(DSP56K_N1, "N1", m_dsp56k_core.AGU.n1).formatstr("%04X");
state_add(DSP56K_N2, "N2", m_dsp56k_core.AGU.n2).formatstr("%04X");
state_add(DSP56K_N3, "N3", m_dsp56k_core.AGU.n3).formatstr("%04X");
state_add(DSP56K_M0, "M0", m_dsp56k_core.AGU.m0).formatstr("%04X");
state_add(DSP56K_M1, "M1", m_dsp56k_core.AGU.m1).formatstr("%04X");
state_add(DSP56K_M2, "M2", m_dsp56k_core.AGU.m2).formatstr("%04X");
state_add(DSP56K_M3, "M3", m_dsp56k_core.AGU.m3).formatstr("%04X");
state_add(DSP56K_TEMP, "TMP", m_dsp56k_core.AGU.temp).formatstr("%04X").noshow();
//state_add(DSP56K_STATUS, "STS", STATUS).formatstr("%02X");
state_add(DSP56K_ST0, "ST0", m_dsp56k_core.PCU.ss[0].d).formatstr("%08X");
state_add(DSP56K_ST1, "ST1", m_dsp56k_core.PCU.ss[1].d).formatstr("%08X");
state_add(DSP56K_ST2, "ST2", m_dsp56k_core.PCU.ss[2].d).formatstr("%08X");
state_add(DSP56K_ST3, "ST3", m_dsp56k_core.PCU.ss[3].d).formatstr("%08X");
state_add(DSP56K_ST4, "ST4", m_dsp56k_core.PCU.ss[4].d).formatstr("%08X");
state_add(DSP56K_ST5, "ST5", m_dsp56k_core.PCU.ss[5].d).formatstr("%08X");
state_add(DSP56K_ST6, "ST6", m_dsp56k_core.PCU.ss[6].d).formatstr("%08X");
state_add(DSP56K_ST7, "ST7", m_dsp56k_core.PCU.ss[7].d).formatstr("%08X");
state_add(DSP56K_ST8, "ST8", m_dsp56k_core.PCU.ss[8].d).formatstr("%08X");
state_add(DSP56K_ST9, "ST9", m_dsp56k_core.PCU.ss[9].d).formatstr("%08X");
state_add(DSP56K_ST10, "ST10", m_dsp56k_core.PCU.ss[10].d).formatstr("%08X");
state_add(DSP56K_ST11, "ST11", m_dsp56k_core.PCU.ss[11].d).formatstr("%08X");
state_add(DSP56K_ST12, "ST12", m_dsp56k_core.PCU.ss[12].d).formatstr("%08X");
state_add(DSP56K_ST13, "ST13", m_dsp56k_core.PCU.ss[13].d).formatstr("%08X");
state_add(DSP56K_ST14, "ST14", m_dsp56k_core.PCU.ss[14].d).formatstr("%08X");
state_add(DSP56K_ST15, "ST15", m_dsp56k_core.PCU.ss[15].d).formatstr("%08X");
state_add(STATE_GENPC, "GENPC", m_dsp56k_core.PCU.pc).noshow();
state_add(STATE_GENPCBASE, "CURPC", m_dsp56k_core.ppc).noshow();
state_add(STATE_GENSP, "GENSP", m_dsp56k_core.PCU.sp).noshow();
state_add(STATE_GENFLAGS, "GENFLAGS", m_dsp56k_core.PCU.sr).formatstr("%14s").noshow();
set_icountptr(m_dsp56k_core.icount);
}
void dsp56k_device::state_string_export(const device_state_entry &entry, std::string &str) const
{
const dsp56k_core *cpustate = &m_dsp56k_core;
switch (entry.index())
{
case STATE_GENFLAGS:
str = string_format("%s%s %s%s%s%s%s%s%s%s %s%s",
/* Status Register */
LF_bit(cpustate) ? "L" : ".",
FV_bit(cpustate) ? "F" : ".",
S_bit(cpustate) ? "S" : ".",
L_bit(cpustate) ? "L" : ".",
E_bit(cpustate) ? "E" : ".",
U_bit(cpustate) ? "U" : ".",
N_bit(cpustate) ? "N" : ".",
Z_bit(cpustate) ? "Z" : ".",
V_bit(cpustate) ? "V" : ".",
C_bit(cpustate) ? "C" : ".",
/* Stack Pointer */
UF_bit(cpustate) ? "U" : ".",
SE_bit(cpustate) ? "S" : ".");
break;
case DSP56K_X:
str = string_format("%04x %04x", X1, X0);
break;
case DSP56K_Y:
str = string_format("%04x %04x", Y1, Y0);
break;
case DSP56K_A:
str = string_format("%02x %04x %04x", A2, A1, A0);
break;
case DSP56K_B:
str = string_format("%02x %04x %04x", B2, B1, B0);
break;
}
}
/***************************************************************************
RESET BEHAVIOR
***************************************************************************/
static void agu_reset(dsp56k_core* cpustate)
{
/* FM.4-3 */
R0 = 0x0000;
R1 = 0x0000;
R2 = 0x0000;
R3 = 0x0000;
N0 = 0x0000;
N1 = 0x0000;
N2 = 0x0000;
N3 = 0x0000;
M0 = 0xffff;
M1 = 0xffff;
M2 = 0xffff;
M3 = 0xffff;
TEMP = 0x0000;
}
static void alu_reset(dsp56k_core* cpustate)
{
X = 0x00000000;
Y = 0x00000000;
A = 0x0000000000;
B = 0x0000000000;
}
void dsp56k_device::device_reset()
{
logerror("Dsp56k reset\n");
m_dsp56k_core.interrupt_cycles = 0;
m_dsp56k_core.repFlag = 0;
m_dsp56k_core.repAddr = 0x0000;
pcu_reset(&m_dsp56k_core);
mem_reset(&m_dsp56k_core);
agu_reset(&m_dsp56k_core);
alu_reset(&m_dsp56k_core);
m_dsp56k_core.ppc = m_dsp56k_core.PCU.pc;
/* HACK - Put a jump to 0x0000 at 0x0000 - this keeps the CPU locked to the instruction at address 0x0000 */
m_dsp56k_core.program->write_word(0x0000, 0x0124);
}
/***************************************************************************
CORE INCLUDE
***************************************************************************/
#include "dsp56ops.hxx"
/***************************************************************************
CORE EXECUTION LOOP
***************************************************************************/
// Execute a single opcode and return how many cycles it took.
static size_t execute_one_new(dsp56k_core* cpustate)
{
// For MAME
cpustate->ppc = PC;
if (cpustate->device->machine().debug_flags & DEBUG_FLAG_CALL_HOOK) // FIXME: if this was a member, the helper would work
cpustate->device->debug()->instruction_hook(PC);
cpustate->op = ROPCODE(PC);
uint16_t w0 = ROPCODE(PC);
uint16_t w1 = ROPCODE(PC + 1);
Opcode op(w0, w1);
op.evaluate(cpustate);
PC += op.evalSize(); // Special size function needed to handle jmps, etc.
// TODO: Currently all operations take up 4 cycles (inst->cycles()).
return 4;
}
void dsp56k_device::execute_run()
{
/* If reset line is asserted, do nothing */
if (m_dsp56k_core.reset_state)
{
m_dsp56k_core.icount = 0;
return;
}
/* HACK - if you're in bootstrap mode, simply pretend you ate up all your cycles waiting for data. */
if (m_dsp56k_core.bootstrap_mode != BOOTSTRAP_OFF)
{
m_dsp56k_core.icount = 0;
return;
}
//m_dsp56k_core.icount -= m_dsp56k_core.interrupt_cycles;
//m_dsp56k_core.interrupt_cycles = 0;
while(m_dsp56k_core.icount > 0)
{
execute_one(&m_dsp56k_core);
if (0) m_dsp56k_core.icount -= execute_one_new(&m_dsp56k_core);
pcu_service_interrupts(&m_dsp56k_core); // TODO: Is it incorrect to service after each instruction?
}
}
std::unique_ptr<util::disasm_interface> dsp56k_device::create_disassembler()
{
return std::make_unique<dsp56k_disassembler>();
}
} // namespace DSP56K

241
src/devices/cpu/dsp56k/dsp56mem.h
View File

@ -1,241 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Andrew Gardner
#ifndef MAME_CPU_DSP56K_DSP56MEM_H
#define MAME_CPU_DSP56K_DSP56MEM_H
#include "dsp56k.h"
namespace DSP56K {
/***************************************************************************
MEMORY
***************************************************************************/
void mem_reset(dsp56k_core* cpustate);
// Adjusts the documented address to match the offset in peripheral RAM
#define A2O(a) (a - 0xffc0)
// Adjusts the offset in peripheral RAM to match the documented address
#define O2A(a) (a + 0xffc0)
// The memory 'registers'
#define PBC (cpustate->peripheral_ram[A2O(0xffc0)])
#define PCC (cpustate->peripheral_ram[A2O(0xffc1)])
#define PBDDR (cpustate->peripheral_ram[A2O(0xffc2)])
#define PCDDR (cpustate->peripheral_ram[A2O(0xffc3)])
#define HCR (cpustate->peripheral_ram[A2O(0xffc4)])
#define COCR (cpustate->peripheral_ram[A2O(0xffc8)])
#define CRASSI0 (cpustate->peripheral_ram[A2O(0xffd0)])
#define CRBSSI0 (cpustate->peripheral_ram[A2O(0xffd1)])
#define CRASSI1 (cpustate->peripheral_ram[A2O(0xffd8)])
#define CRBSSI1 (cpustate->peripheral_ram[A2O(0xffd9)])
#define PLCR (cpustate->peripheral_ram[A2O(0xffdc)])
#define BCR (cpustate->peripheral_ram[A2O(0xffde)])
#define IPR (cpustate->peripheral_ram[A2O(0xffdf)])
#define PBD (cpustate->peripheral_ram[A2O(0xffe2)])
#define PCD (cpustate->peripheral_ram[A2O(0xffe3)])
#define HSR (cpustate->peripheral_ram[A2O(0xffe4)])
#define HTXHRX (cpustate->peripheral_ram[A2O(0xffe5)])
#define COSR (cpustate->peripheral_ram[A2O(0xffe8)])
#define CRXCTX (cpustate->peripheral_ram[A2O(0xffe9)])
#define TCR (cpustate->peripheral_ram[A2O(0xffec)])
#define TCTR (cpustate->peripheral_ram[A2O(0xffed)])
#define TCPR (cpustate->peripheral_ram[A2O(0xffee)])
#define TPR (cpustate->peripheral_ram[A2O(0xffef)])
#define TSRSSI0 (cpustate->peripheral_ram[A2O(0xfff0)])
#define TRXSSI0 (cpustate->peripheral_ram[A2O(0xfff1)])
#define RSMA0 (cpustate->peripheral_ram[A2O(0xfff2)])
#define RSMB0 (cpustate->peripheral_ram[A2O(0xfff3)])
#define TSMA0 (cpustate->peripheral_ram[A2O(0xfff4)])
#define TSMB0 (cpustate->peripheral_ram[A2O(0xfff5)])
#define TSRSSI1 (cpustate->peripheral_ram[A2O(0xfff8)])
#define TRXSSI1 (cpustate->peripheral_ram[A2O(0xfff9)])
#define RSMA1 (cpustate->peripheral_ram[A2O(0xfffa)])
#define RSMB1 (cpustate->peripheral_ram[A2O(0xfffb)])
#define TSMA1 (cpustate->peripheral_ram[A2O(0xfffc)])
#define TSMB1 (cpustate->peripheral_ram[A2O(0xfffd)])
/* Interrupt priority register (IPR) bits */
void IPR_set(dsp56k_core* cpustate, uint16_t value);
/* A return value of -1 means disabled */
int8_t irqa_ipl(dsp56k_core* cpustate);
int8_t irqb_ipl(dsp56k_core* cpustate);
uint8_t irqa_trigger(dsp56k_core* cpustate);
uint8_t irqb_trigger(dsp56k_core* cpustate);
int8_t codec_ipl(dsp56k_core* cpustate);
int8_t host_ipl(dsp56k_core* cpustate);
int8_t ssi0_ipl(dsp56k_core* cpustate);
int8_t ssi1_ipl(dsp56k_core* cpustate);
int8_t tm_ipl(dsp56k_core* cpustate);
/***************************************************************************
HOST INTERFACE
***************************************************************************/
void dsp56k_host_interface_reset(dsp56k_core* cpustate);
#define HTX (HTXHRX)
#define HRX (HTXHRX)
#define ICR (cpustate->HI.icr)
#define CVR (cpustate->HI.cvr)
#define ISR (cpustate->HI.isr)
#define IVR (cpustate->HI.ivr)
#define TXH (cpustate->HI.trxh)
#define TXL (cpustate->HI.trxl)
#define RXH (cpustate->HI.trxh)
#define RXL (cpustate->HI.trxl)
/***************/
/* DSP56k SIDE */
/***************/
/* Host Control Register (HCR) Bits */
void HCR_set(dsp56k_core* cpustate, uint16_t value);
//uint16_t HF3_bit(dsp56k_core* cpustate); #define hf3BIT ((HCR & 0x0010) != 0)
//uint16_t HF2_bit(dsp56k_core* cpustate); #define hf2BIT ((HCR & 0x0008) != 0)
uint16_t HCIE_bit(dsp56k_core* cpustate);
uint16_t HTIE_bit(dsp56k_core* cpustate);
uint16_t HRIE_bit(dsp56k_core* cpustate);
void HF3_bit_set(dsp56k_core* cpustate, uint16_t value);
void HF2_bit_set(dsp56k_core* cpustate, uint16_t value);
void HCIE_bit_set(dsp56k_core* cpustate, uint16_t value);
void HTIE_bit_set(dsp56k_core* cpustate, uint16_t value);
void HRIE_bit_set(dsp56k_core* cpustate, uint16_t value);
/* Host Status Register (HSR) Bits */
//void HSR_set(dsp56k_core* cpustate, uint16_t value);
//uint16_t DMA_bit(dsp56k_core* cpustate); #define dmaBIT ((HSR & 0x0080) != 0)
//uint16_t HF1_bit(dsp56k_core* cpustate); #define hf1BIT ((HSR & 0x0010) != 0)
//uint16_t HF0_bit(dsp56k_core* cpustate); #define hf0BIT ((HSR & 0x0008) != 0)
//uint16_t HCP_bit(dsp56k_core* cpustate); #define hcpBIT ((HSR & 0x0004) != 0)
uint16_t HTDE_bit(dsp56k_core* cpustate);
uint16_t HRDF_bit(dsp56k_core* cpustate);
void DMA_bit_set(dsp56k_core* cpustate, uint16_t value);
void HF1_bit_set(dsp56k_core* cpustate, uint16_t value);
void HF0_bit_set(dsp56k_core* cpustate, uint16_t value);
void HCP_bit_set(dsp56k_core* cpustate, uint16_t value);
void HTDE_bit_set(dsp56k_core* cpustate, uint16_t value);
void HRDF_bit_set(dsp56k_core* cpustate, uint16_t value);
/*************/
/* HOST SIDE */
/*************/
/* Interrupt Control Register (ICR) Bits */
void ICR_set(dsp56k_core* cpustate, uint8_t value);
//uint8_t INIT_bit(dsp56k_core* cpustate); #define x_initBIT ((dsp56k.HI.ICR & 0x0080) != 0)
//uint8_t HM1_bit(dsp56k_core* cpustate); #define x_hm1BIT ((dsp56k.HI.ICR & 0x0040) != 0)
//uint8_t HM0_bit(dsp56k_core* cpustate); #define x_hm0BIT ((dsp56k.HI.ICR & 0x0020) != 0)
//uint8_t HF1_bit_host(dsp56k_core* cpustate); #define x_hf1BIT ((dsp56k.HI.ICR & 0x0010) != 0)
//uint8_t HF0_bit_host(dsp56k_core* cpustate); #define x_hf0BIT ((dsp56k.HI.ICR & 0x0008) != 0)
//uint8_t TREQ_bit(dsp56k_core* cpustate); #define x_treqBIT ((dsp56k.HI.ICR & 0x0002) != 0)
//uint8_t RREQ_bit(dsp56k_core* cpustate); #define x_rreqBIT ((dsp56k.HI.ICR & 0x0001) != 0)
//void INIT_bit_set(dsp56k_core* cpustate, uint8_t value); #define CLEAR_x_initBIT() (dsp56k.HI.ICR &= (~0x0080))
//void HM1_bit_set(dsp56k_core* cpustate, uint8_t value); #define CLEAR_x_hm1BIT() (dsp56k.HI.ICR &= (~0x0040))
//void HM0_bit_set(dsp56k_core* cpustate, uint8_t value); #define CLEAR_x_hm0BIT() (dsp56k.HI.ICR &= (~0x0020))
void HF1_bit_host_set(dsp56k_core* cpustate, uint8_t value);
void HF0_bit_host_set(dsp56k_core* cpustate, uint8_t value);
void TREQ_bit_set(dsp56k_core* cpustate, uint8_t value);
void RREQ_bit_set(dsp56k_core* cpustate, uint8_t value);
/* Command Vector Register (CVR) Bits */
void CVR_set(dsp56k_core* cpustate, uint8_t value);
//uint8_t HC_bit();
uint8_t HV_bits(dsp56k_core* cpustate);
void HC_bit_set(dsp56k_core* cpustate, uint8_t value);
void HV_bits_set(dsp56k_core* cpustate, uint8_t value);
/* Interrupt Status Register (ISR) Bits */
// void ISR_set(dsp56k_core* cpustate, uint8_t value);
//uint8_t HREQ_bit(dsp56k_core* cpustate); #define x_hreqBIT ((dsp56k.HI.ISR & 0x0080) != 0)
//uint8_t DMA_bit(dsp56k_core* cpustate); #define x_dmaBIT ((dsp56k.HI.ISR & 0x0040) != 0)
//uint8_t HF3_bit_host(dsp56k_core* cpustate); #define x_hf3BIT ((dsp56k.HI.ISR & 0x0010) != 0)
//uint8_t HF2_bit_host(dsp56k_core* cpustate); #define x_hf2BIT ((dsp56k.HI.ISR & 0x0008) != 0)
//uint8_t TRDY_bit(dsp56k_core* cpustate); #define x_trdyBIT ((dsp56k.HI.ISR & 0x0004) != 0)
uint8_t TXDE_bit(dsp56k_core* cpustate);
uint8_t RXDF_bit(dsp56k_core* cpustate);
//void HREQ_bit_set(dsp56k_core* cpustate, uint8_t value); #define CLEAR_x_hreqBIT() (dsp56k.HI.ISR &= (~0x0080))
//void DMA_bit_set(dsp56k_core* cpustate, uint8_t value); #define CLEAR_x_dmaBIT() (dsp56k.HI.ISR &= (~0x0040))
void HF3_bit_host_set(dsp56k_core* cpustate, uint8_t value);
void HF2_bit_host_set(dsp56k_core* cpustate, uint8_t value);
//void TRDY_bit_set(dsp56k_core* cpustate, uint8_t value); #define CLEAR_x_trdyBIT() (dsp56k.HI.ISR &= (~0x0004))
void TXDE_bit_set(dsp56k_core* cpustate, uint8_t value);
void RXDF_bit_set(dsp56k_core* cpustate, uint8_t value);
/* Interrupt Vector Register (IVR) Bits */
//void IVR_set(dsp56k_core* cpustate, uint8_t value);
//uint8_t IV7_bit(dsp56k_core* cpustate);
//uint8_t IV6_bit(dsp56k_core* cpustate);
//uint8_t IV5_bit(dsp56k_core* cpustate);
//uint8_t IV4_bit(dsp56k_core* cpustate);
//uint8_t IV3_bit(dsp56k_core* cpustate);
//uint8_t IV2_bit(dsp56k_core* cpustate);
//uint8_t IV1_bit(dsp56k_core* cpustate);
//uint8_t IV0_bit(dsp56k_core* cpustate);
//void IV7_bit_set(dsp56k_core* cpustate, uint8_t value);
//void IV6_bit_set(dsp56k_core* cpustate, uint8_t value);
//void IV5_bit_set(dsp56k_core* cpustate, uint8_t value);
//void IV4_bit_set(dsp56k_core* cpustate, uint8_t value);
//void IV3_bit_set(dsp56k_core* cpustate, uint8_t value);
//void IV2_bit_set(dsp56k_core* cpustate, uint8_t value);
//void IV1_bit_set(dsp56k_core* cpustate, uint8_t value);
//void IV0_bit_set(dsp56k_core* cpustate, uint8_t value);
/* PROTOTYPES */
void dsp56k_host_interface_HTX_to_host(dsp56k_core* cpustate);
void dsp56k_host_interface_host_to_HTX(dsp56k_core* cpustate);
/***************************************************************************
I/O INTERFACE
***************************************************************************/
void dsp56k_io_reset(dsp56k_core* cpustate);
/* Port A Bus Control Register (BCR) */
void BCR_set(dsp56k_core* cpustate, uint16_t value);
//uint16_t RH_bit(dsp56k_core* cpustate);
//uint16_t BS_bit(dsp56k_core* cpustate);
//uint16_t external_x_wait_states(dsp56k_core* cpustate);
//uint16_t external_p_wait_states(dsp56k_core* cpustate);
void RH_bit_set(dsp56k_core* cpustate, uint16_t value);
void BS_bit_set(dsp56k_core* cpustate, uint16_t value);
void external_x_wait_states_set(dsp56k_core* cpustate, uint16_t value);
void external_p_wait_states_set(dsp56k_core* cpustate, uint16_t value);
/* Port B Control Register (PBC) */
void PBC_set(dsp56k_core* cpustate, uint16_t value);
//int host_interface_active(dsp56k_core* cpustate);
/* Port B Data Direction Register (PBDDR) */
void PBDDR_set(dsp56k_core* cpustate, uint16_t value);
/* Port B Data Register (PBD) */
void PBD_set(dsp56k_core* cpustate, uint16_t value);
/* Port C Control Register (PCC) */
void PCC_set(dsp56k_core* cpustate, uint16_t value);
/* Port C Data Direction Register (PCDDR) */
void PCDDR_set(dsp56k_core* cpustate, uint16_t value);
/* Port C Dtaa Register (PCD) */
void PCD_set(dsp56k_core* cpustate, uint16_t value);
} // namespace DSP56K
#endif // MAME_CPU_DSP56K_DSP56MEM_H

150
src/devices/cpu/dsp56k/dsp56pcu.h
View File

@ -1,150 +0,0 @@
// license:BSD-3-Clause
// copyright-holders:Andrew Gardner
#ifndef __DSP56_PCU_H__
#define __DSP56_PCU_H__
#include "dsp56k.h"
namespace DSP56K
{
/***************************************************************************
PCU
***************************************************************************/
void pcu_reset(dsp56k_core* cpustate);
void pcu_init(dsp56k_core* cpustate, device_t *device);
#define PC (cpustate->PCU.pc)
#define LA (cpustate->PCU.la)
#define LC (cpustate->PCU.lc)
#define SR (cpustate->PCU.sr)
#define OMR (cpustate->PCU.omr)
#define SP (cpustate->PCU.sp)
#define SS (cpustate->PCU.ss)
#define SSH (SS[SP].w.h)
#define SSL (SS[SP].w.l)
#define ST0 (SS[0].d)
#define ST1 (SS[1].d)
#define ST2 (SS[2].d)
#define ST3 (SS[3].d)
#define ST4 (SS[4].d)
#define ST5 (SS[5].d)
#define ST6 (SS[6].d)
#define ST7 (SS[7].d)
#define ST8 (SS[8].d)
#define ST9 (SS[9].d)
#define ST10 (SS[10].d)
#define ST11 (SS[11].d)
#define ST12 (SS[12].d)
#define ST13 (SS[13].d)
#define ST14 (SS[14].d)
#define ST15 (SS[15].d)
/* STATUS REGISTER (SR) BITS (1-25) */
/* MR */
uint8_t LF_bit(const dsp56k_core* cpustate);
uint8_t FV_bit(const dsp56k_core* cpustate);
//uint8_t S_bits(const dsp56k_core* cpustate);
uint8_t I_bits(const dsp56k_core* cpustate);
/* CCR - with macros for easy access */
#define S() (S_bit(cpustate))
uint8_t S_bit(const dsp56k_core* cpustate);
#define L() (L_bit(cpustate))
uint8_t L_bit(const dsp56k_core* cpustate);
#define E() (E_bit(cpustate))
uint8_t E_bit(const dsp56k_core* cpustate);
#define U() (U_bit(cpustate))
uint8_t U_bit(const dsp56k_core* cpustate);
#define N() (N_bit(cpustate))
uint8_t N_bit(const dsp56k_core* cpustate);
#define Z() (Z_bit(cpustate))
uint8_t Z_bit(const dsp56k_core* cpustate);
#define V() (V_bit(cpustate))
uint8_t V_bit(const dsp56k_core* cpustate);
#define C() (C_bit(cpustate))
uint8_t C_bit(const dsp56k_core* cpustate);
/* MR setters */
void LF_bit_set(dsp56k_core* cpustate, uint8_t value);
void FV_bit_set(dsp56k_core* cpustate, uint8_t value);
void S_bits_set(dsp56k_core* cpustate, uint8_t value);
void I_bits_set(dsp56k_core* cpustate, uint8_t value);
/* CCR setters - with macros for easy access */
#define DSP56K_S_SET() (S_bit_set(cpustate, 1))
#define DSP56K_S_CLEAR() (S_bit_set(cpustate, 0))
void S_bit_set(dsp56k_core* cpustate, uint8_t value);
#define DSP56K_L_SET() (L_bit_set(cpustate, 1))
#define DSP56K_L_CLEAR() (L_bit_set(cpustate, 0))
void L_bit_set(dsp56k_core* cpustate, uint8_t value);
#define DSP56K_E_SET() (E_bit_set(cpustate, 1))
#define DSP56K_E_CLEAR() (E_bit_set(cpustate, 0))
void E_bit_set(dsp56k_core* cpustate, uint8_t value);
#define DSP56K_U_SET() (U_bit_set(cpustate, 1))
#define DSP56K_U_CLEAR() (U_bit_set(cpustate, 0))
void U_bit_set(dsp56k_core* cpustate, uint8_t value);
#define DSP56K_N_SET() (N_bit_set(cpustate, 1))
#define DSP56K_N_CLEAR() (N_bit_set(cpustate, 0))
void N_bit_set(dsp56k_core* cpustate, uint8_t value);
#define DSP56K_Z_SET() (Z_bit_set(cpustate, 1))
#define DSP56K_Z_CLEAR() (Z_bit_set(cpustate, 0))
void Z_bit_set(dsp56k_core* cpustate, uint8_t value);
#define DSP56K_V_SET() (V_bit_set(cpustate, 1))
#define DSP56K_V_CLEAR() (V_bit_set(cpustate, 0))
void V_bit_set(dsp56k_core* cpustate, uint8_t value);
#define DSP56K_C_SET() (C_bit_set(cpustate, 1))
#define DSP56K_C_CLEAR() (C_bit_set(cpustate, 0))
void C_bit_set(dsp56k_core* cpustate, uint8_t value);
// TODO: Maybe some functions for Interrupt Mask and Scaling Mode go here?
/* 1-28 OPERATING MODE REGISTER (OMR) BITS */
//uint8_t CD_bit(const dsp56k_core* cpustate);
//uint8_t SD_bit(const dsp56k_core* cpustate);
//uint8_t R_bit(const dsp56k_core* cpustate);
//uint8_t SA_bit(const dsp56k_core* cpustate);
//uint8_t MC_bit(const dsp56k_core* cpustate);
uint8_t MB_bit(const dsp56k_core* cpustate);
uint8_t MA_bit(const dsp56k_core* cpustate);
void CD_bit_set(dsp56k_core* cpustate, uint8_t value);
void SD_bit_set(dsp56k_core* cpustate, uint8_t value);
void R_bit_set(dsp56k_core* cpustate, uint8_t value);
void SA_bit_set(dsp56k_core* cpustate, uint8_t value);
void MC_bit_set(dsp56k_core* cpustate, uint8_t value);
void MB_bit_set(dsp56k_core* cpustate, uint8_t value);
void MA_bit_set(dsp56k_core* cpustate, uint8_t value);
/* 1-27 STACK POINTER (SP) BITS */
uint8_t UF_bit(const dsp56k_core* cpustate);
uint8_t SE_bit(const dsp56k_core* cpustate);
//void UF_bit_set(dsp56k_core* cpustate, uint8_t value) {};
//void SE_bit_set(dsp56k_core* cpustate, uint8_t value) {};
// HACK - Bootstrap modes
#define BOOTSTRAP_OFF (0)
#define BOOTSTRAP_SSIX (1)
#define BOOTSTRAP_HI (2)
/* PCU IRQ goodies */
void pcu_service_interrupts(dsp56k_core* cpustate);
void dsp56k_irq_table_init(void);
void dsp56k_set_irq_source(uint8_t irq_num, uint16_t iv, const char* source);
int dsp56k_get_irq_index_by_tag(const char* tag);
void dsp56k_add_pending_interrupt(dsp56k_core* cpustate, const char* name); // Call me to add an interrupt to the queue
void dsp56k_clear_pending_interrupts(dsp56k_core* cpustate);
int dsp56k_count_pending_interrupts(dsp56k_core* cpustate);
void dsp56k_sort_pending_interrupts(dsp56k_core* cpustate, int num);
int8_t dsp56k_get_irq_priority(dsp56k_core* cpustate, int index);
} // namespace DSP56K
#endif

2
src/mame/drivers/indigo.cpp
View File

@ -16,7 +16,7 @@
**********************************************************************/
#include "emu.h"
//#include "cpu/dsp56k/dsp56k.h"
//#include "cpu/dsp56156/dsp56156.h"
#include "cpu/mips/mips1.h"
#include "cpu/mips/mips3.h"
#include "machine/eepromser.h"

178
src/mame/drivers/plygonet.cpp
View File

@ -186,16 +186,16 @@ WRITE32_MEMBER(polygonet_state::shared_ram_write)
m_maincpu->pc());
}
/* write to the current dsp56k word */
/* write to the current DSP word */
if (ACCESSING_BITS_16_31)
{
m_dsp56k_shared_ram_16[(offset<<1)] = (m_shared_ram[offset] & 0xffff0000) >> 16 ;
m_dsp56156_shared_ram_16[(offset<<1)] = (m_shared_ram[offset] & 0xffff0000) >> 16 ;
}
/* write to the next dsp56k word */
/* write to the next DSP word */
if (ACCESSING_BITS_0_15)
{
m_dsp56k_shared_ram_16[(offset<<1)+1] = (m_shared_ram[offset] & 0x0000ffff) ;
m_dsp56156_shared_ram_16[(offset<<1)+1] = (m_shared_ram[offset] & 0x0000ffff) ;
}
}
@ -207,12 +207,12 @@ WRITE32_MEMBER(polygonet_state::dsp_w_lines)
if ((data >> 24) & 0x01)
{
// logerror("RESET CLEARED\n");
m_dsp->set_input_line(DSP56K_IRQ_RESET, CLEAR_LINE);
m_dsp->set_input_line(DSP56156_IRQ_RESET, CLEAR_LINE);
}
else
{
// logerror("RESET ASSERTED\n");
m_dsp->set_input_line(DSP56K_IRQ_RESET, ASSERT_LINE);
m_dsp->set_input_line(DSP56156_IRQ_RESET, ASSERT_LINE);
}
/* 0x04000000 is the COMBNK line - it switches who has access to the shared RAM - the dsp or the 68020 */
@ -241,16 +241,16 @@ READ32_MEMBER(polygonet_state::network_r)
/**********************************************************************************/
/******* DSP56k maps *******/
/******* DSP56156 maps *******/
/**********************************************************************************/
/* It's believed this is hard-wired to return (at least) bit 15 as 0 - causes a host interface bootup */
READ16_MEMBER(polygonet_state::dsp56k_bootload_r)
READ16_MEMBER(polygonet_state::dsp56156_bootload_r)
{
return 0x7fff;
}
/* The dsp56k's Port C Data register (0xffe3) :
/* The dsp56156's Port C Data register (0xffe3) :
Program code (function 4e) configures it as general purpose output I/O pins (ffc1 = 0000 & ffc3 = 0fff).
XXXX ---- ---- ---- . Reserved bits
@ -265,9 +265,9 @@ READ16_MEMBER(polygonet_state::dsp56k_bootload_r)
bit 0002 turns on *just* before this happens.
*/
static uint8_t dsp56k_bank_group(device_t* cpu)
static uint8_t dsp56156_bank_group(device_t* cpu)
{
uint16_t portC = downcast<dsp56k_device *>(cpu)->get_peripheral_memory(0xffe3);
uint16_t portC = downcast<dsp56156_device *>(cpu)->get_peripheral_memory(0xffe3);
/* If bank group B is on, it overrides bank group A */
if (portC & 0x0002)
@ -278,9 +278,9 @@ static uint8_t dsp56k_bank_group(device_t* cpu)
return INVALID_BANK_GROUP;
}
static uint8_t dsp56k_bank_num(device_t* cpu, uint8_t bank_group)
static uint8_t dsp56156_bank_num(device_t* cpu, uint8_t bank_group)
{
uint16_t portC = downcast<dsp56k_device *>(cpu)->get_peripheral_memory(0xffe3);
uint16_t portC = downcast<dsp56156_device *>(cpu)->get_peripheral_memory(0xffe3);
if (bank_group == BANK_GROUP_A)
{
@ -296,7 +296,7 @@ static uint8_t dsp56k_bank_num(device_t* cpu, uint8_t bank_group)
}
else if (bank_group == INVALID_BANK_GROUP)
{
fatalerror("Plygonet: dsp56k bank num invalid.\n");
fatalerror("Plygonet: dsp56156 bank num invalid.\n");
}
return 0;
@ -304,110 +304,110 @@ static uint8_t dsp56k_bank_num(device_t* cpu, uint8_t bank_group)
/* BANK HANDLERS */
READ16_MEMBER(polygonet_state::dsp56k_ram_bank00_read)
READ16_MEMBER(polygonet_state::dsp56156_ram_bank00_read)
{
uint8_t en_group = dsp56k_bank_group(m_dsp.target());
uint8_t bank_num = dsp56k_bank_num(m_dsp.target(), en_group);
uint32_t driver_bank_offset = (en_group * dsp56k_bank00_size * 8) + (bank_num * dsp56k_bank00_size);
uint8_t en_group = dsp56156_bank_group(m_dsp.target());
uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group);
uint32_t driver_bank_offset = (en_group * dsp56156_bank00_size * 8) + (bank_num * dsp56156_bank00_size);
return m_dsp56k_bank00_ram[driver_bank_offset + offset];
return m_dsp56156_bank00_ram[driver_bank_offset + offset];
}
WRITE16_MEMBER(polygonet_state::dsp56k_ram_bank00_write)
WRITE16_MEMBER(polygonet_state::dsp56156_ram_bank00_write)
{
uint8_t en_group = dsp56k_bank_group(m_dsp.target());
uint8_t bank_num = dsp56k_bank_num(m_dsp.target(), en_group);
uint32_t driver_bank_offset = (en_group * dsp56k_bank00_size * 8) + (bank_num * dsp56k_bank00_size);
uint8_t en_group = dsp56156_bank_group(m_dsp.target());
uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group);
uint32_t driver_bank_offset = (en_group * dsp56156_bank00_size * 8) + (bank_num * dsp56156_bank00_size);
COMBINE_DATA(&m_dsp56k_bank00_ram[driver_bank_offset + offset]);
COMBINE_DATA(&m_dsp56156_bank00_ram[driver_bank_offset + offset]);
}
READ16_MEMBER(polygonet_state::dsp56k_ram_bank01_read)
READ16_MEMBER(polygonet_state::dsp56156_ram_bank01_read)
{
uint8_t en_group = dsp56k_bank_group(m_dsp.target());
uint8_t bank_num = dsp56k_bank_num(m_dsp.target(), en_group);
uint32_t driver_bank_offset = (en_group * dsp56k_bank01_size * 8) + (bank_num * dsp56k_bank01_size);
uint8_t en_group = dsp56156_bank_group(m_dsp.target());
uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group);
uint32_t driver_bank_offset = (en_group * dsp56156_bank01_size * 8) + (bank_num * dsp56156_bank01_size);
return m_dsp56k_bank01_ram[driver_bank_offset + offset];
return m_dsp56156_bank01_ram[driver_bank_offset + offset];
}
WRITE16_MEMBER(polygonet_state::dsp56k_ram_bank01_write)
WRITE16_MEMBER(polygonet_state::dsp56156_ram_bank01_write)
{
uint8_t en_group = dsp56k_bank_group(m_dsp.target());
uint8_t bank_num = dsp56k_bank_num(m_dsp.target(), en_group);
uint32_t driver_bank_offset = (en_group * dsp56k_bank01_size * 8) + (bank_num * dsp56k_bank01_size);
uint8_t en_group = dsp56156_bank_group(m_dsp.target());
uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group);
uint32_t driver_bank_offset = (en_group * dsp56156_bank01_size * 8) + (bank_num * dsp56156_bank01_size);
COMBINE_DATA(&m_dsp56k_bank01_ram[driver_bank_offset + offset]);
COMBINE_DATA(&m_dsp56156_bank01_ram[driver_bank_offset + offset]);
/* For now, *always* combine P:0x7000-0x7fff with bank01 with no regard to the banking hardware. */
m_dsp56k_p_mirror[offset] = data;
m_dsp56156_p_mirror[offset] = data;
}
READ16_MEMBER(polygonet_state::dsp56k_ram_bank02_read)
READ16_MEMBER(polygonet_state::dsp56156_ram_bank02_read)
{
uint8_t en_group = dsp56k_bank_group(m_dsp.target());
uint8_t bank_num = dsp56k_bank_num(m_dsp.target(), en_group);
uint32_t driver_bank_offset = (en_group * dsp56k_bank02_size * 8) + (bank_num * dsp56k_bank02_size);
uint8_t en_group = dsp56156_bank_group(m_dsp.target());
uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group);
uint32_t driver_bank_offset = (en_group * dsp56156_bank02_size * 8) + (bank_num * dsp56156_bank02_size);
return m_dsp56k_bank02_ram[driver_bank_offset + offset];
return m_dsp56156_bank02_ram[driver_bank_offset + offset];
}
WRITE16_MEMBER(polygonet_state::dsp56k_ram_bank02_write)
WRITE16_MEMBER(polygonet_state::dsp56156_ram_bank02_write)
{
uint8_t en_group = dsp56k_bank_group(m_dsp.target());
uint8_t bank_num = dsp56k_bank_num(m_dsp.target(), en_group);
uint32_t driver_bank_offset = (en_group * dsp56k_bank02_size * 8) + (bank_num * dsp56k_bank02_size);
uint8_t en_group = dsp56156_bank_group(m_dsp.target());
uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group);
uint32_t driver_bank_offset = (en_group * dsp56156_bank02_size * 8) + (bank_num * dsp56156_bank02_size);
COMBINE_DATA(&m_dsp56k_bank02_ram[driver_bank_offset + offset]);
COMBINE_DATA(&m_dsp56156_bank02_ram[driver_bank_offset + offset]);
}
READ16_MEMBER(polygonet_state::dsp56k_shared_ram_read)
READ16_MEMBER(polygonet_state::dsp56156_shared_ram_read)
{
uint8_t en_group = dsp56k_bank_group(m_dsp.target());
uint8_t bank_num = dsp56k_bank_num(m_dsp.target(), en_group);
uint32_t driver_bank_offset = (en_group * dsp56k_shared_ram_16_size * 8) + (bank_num * dsp56k_shared_ram_16_size);
uint8_t en_group = dsp56156_bank_group(m_dsp.target());
uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group);
uint32_t driver_bank_offset = (en_group * dsp56156_shared_ram_16_size * 8) + (bank_num * dsp56156_shared_ram_16_size);
return m_dsp56k_shared_ram_16[driver_bank_offset + offset];
return m_dsp56156_shared_ram_16[driver_bank_offset + offset];
}
WRITE16_MEMBER(polygonet_state::dsp56k_shared_ram_write)
WRITE16_MEMBER(polygonet_state::dsp56156_shared_ram_write)
{
uint8_t en_group = dsp56k_bank_group(m_dsp.target());
uint8_t bank_num = dsp56k_bank_num(m_dsp.target(), en_group);
uint32_t driver_bank_offset = (en_group * dsp56k_shared_ram_16_size * 8) + (bank_num * dsp56k_shared_ram_16_size);
uint8_t en_group = dsp56156_bank_group(m_dsp.target());
uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group);
uint32_t driver_bank_offset = (en_group * dsp56156_shared_ram_16_size * 8) + (bank_num * dsp56156_shared_ram_16_size);
COMBINE_DATA(&m_dsp56k_shared_ram_16[driver_bank_offset + offset]);
COMBINE_DATA(&m_dsp56156_shared_ram_16[driver_bank_offset + offset]);
/* Bank group A with offset 0 is believed to be the shared region */
if (en_group == BANK_GROUP_A && bank_num == 0)
{
if (offset % 2)
m_shared_ram[offset>>1] = ((m_dsp56k_shared_ram_16[offset-1]) << 16) | m_dsp56k_shared_ram_16[offset];
m_shared_ram[offset>>1] = ((m_dsp56156_shared_ram_16[offset-1]) << 16) | m_dsp56156_shared_ram_16[offset];
else
m_shared_ram[offset>>1] = ((m_dsp56k_shared_ram_16[offset]) << 16) | m_dsp56k_shared_ram_16[offset+1];
m_shared_ram[offset>>1] = ((m_dsp56156_shared_ram_16[offset]) << 16) | m_dsp56156_shared_ram_16[offset+1];
}
}
READ16_MEMBER(polygonet_state::dsp56k_ram_bank04_read)
READ16_MEMBER(polygonet_state::dsp56156_ram_bank04_read)
{
uint8_t en_group = dsp56k_bank_group(m_dsp.target());
uint8_t bank_num = dsp56k_bank_num(m_dsp.target(), en_group);
uint32_t driver_bank_offset = (en_group * dsp56k_bank04_size * 8) + (bank_num * dsp56k_bank04_size);
uint8_t en_group = dsp56156_bank_group(m_dsp.target());
uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group);
uint32_t driver_bank_offset = (en_group * dsp56156_bank04_size * 8) + (bank_num * dsp56156_bank04_size);
return m_dsp56k_bank04_ram[driver_bank_offset + offset];
return m_dsp56156_bank04_ram[driver_bank_offset + offset];
}
WRITE16_MEMBER(polygonet_state::dsp56k_ram_bank04_write)
WRITE16_MEMBER(polygonet_state::dsp56156_ram_bank04_write)
{
uint8_t en_group = dsp56k_bank_group(m_dsp.target());
uint8_t bank_num = dsp56k_bank_num(m_dsp.target(), en_group);
uint32_t driver_bank_offset = (en_group * dsp56k_bank04_size * 8) + (bank_num * dsp56k_bank04_size);
uint8_t en_group = dsp56156_bank_group(m_dsp.target());
uint8_t bank_num = dsp56156_bank_num(m_dsp.target(), en_group);
uint32_t driver_bank_offset = (en_group * dsp56156_bank04_size * 8) + (bank_num * dsp56156_bank04_size);
COMBINE_DATA(&m_dsp56k_bank04_ram[driver_bank_offset + offset]);
COMBINE_DATA(&m_dsp56156_bank04_ram[driver_bank_offset + offset]);
}
@ -440,19 +440,19 @@ void polygonet_state::main_map(address_map &map)
void polygonet_state::dsp_program_map(address_map &map)
{
map(0x7000, 0x7fff).ram().share("dsp56k_p_mirror"); /* Unsure of size, but 0x1000 matches bank01 */
map(0x8000, 0x87ff).ram().share("dsp56k_p_8000");
map(0xc000, 0xc000).r(FUNC(polygonet_state::dsp56k_bootload_r));
map(0x7000, 0x7fff).ram().share("dsp56156_p_mirror"); /* Unsure of size, but 0x1000 matches bank01 */
map(0x8000, 0x87ff).ram().share("dsp56156_p_8000");
map(0xc000, 0xc000).r(FUNC(polygonet_state::dsp56156_bootload_r));
}
void polygonet_state::dsp_data_map(address_map &map)
{
map(0x0800, 0x5fff).ram(); /* Appears to not be affected by banking? */
map(0x6000, 0x6fff).rw(FUNC(polygonet_state::dsp56k_ram_bank00_read), FUNC(polygonet_state::dsp56k_ram_bank00_write));
map(0x7000, 0x7fff).rw(FUNC(polygonet_state::dsp56k_ram_bank01_read), FUNC(polygonet_state::dsp56k_ram_bank01_write)); /* Mirrored in program space @ 0x7000 */
map(0x8000, 0xbfff).rw(FUNC(polygonet_state::dsp56k_ram_bank02_read), FUNC(polygonet_state::dsp56k_ram_bank02_write));
map(0xc000, 0xdfff).rw(FUNC(polygonet_state::dsp56k_shared_ram_read), FUNC(polygonet_state::dsp56k_shared_ram_write));
map(0xe000, 0xffbf).rw(FUNC(polygonet_state::dsp56k_ram_bank04_read), FUNC(polygonet_state::dsp56k_ram_bank04_write));
map(0x6000, 0x6fff).rw(FUNC(polygonet_state::dsp56156_ram_bank00_read), FUNC(polygonet_state::dsp56156_ram_bank00_write));
map(0x7000, 0x7fff).rw(FUNC(polygonet_state::dsp56156_ram_bank01_read), FUNC(polygonet_state::dsp56156_ram_bank01_write)); /* Mirrored in program space @ 0x7000 */
map(0x8000, 0xbfff).rw(FUNC(polygonet_state::dsp56156_ram_bank02_read), FUNC(polygonet_state::dsp56156_ram_bank02_write));
map(0xc000, 0xdfff).rw(FUNC(polygonet_state::dsp56156_shared_ram_read), FUNC(polygonet_state::dsp56156_shared_ram_write));
map(0xe000, 0xffbf).rw(FUNC(polygonet_state::dsp56156_ram_bank04_read), FUNC(polygonet_state::dsp56156_ram_bank04_write));
}
/**********************************************************************************/
@ -519,9 +519,9 @@ void polygonet_state::machine_reset()
m_sound_ctrl = 0;
/* It's presumed the hardware has hard-wired operating mode 1 (MODA = 1, MODB = 0) */
m_dsp->set_input_line(DSP56K_IRQ_RESET, ASSERT_LINE);
m_dsp->set_input_line(DSP56K_IRQ_MODA, ASSERT_LINE);
m_dsp->set_input_line(DSP56K_IRQ_MODB, CLEAR_LINE);
m_dsp->set_input_line(DSP56156_IRQ_RESET, ASSERT_LINE);
m_dsp->set_input_line(DSP56156_IRQ_MODA, ASSERT_LINE);
m_dsp->set_input_line(DSP56156_IRQ_MODB, CLEAR_LINE);
}
void polygonet_state::machine_start()
@ -532,11 +532,11 @@ void polygonet_state::machine_start()
m_inputs[3] = ioport("IN3");
/* save states */
save_item(NAME(m_dsp56k_bank00_ram));
save_item(NAME(m_dsp56k_bank01_ram));
save_item(NAME(m_dsp56k_bank02_ram));
save_item(NAME(m_dsp56k_shared_ram_16));
save_item(NAME(m_dsp56k_bank04_ram));
save_item(NAME(m_dsp56156_bank00_ram));
save_item(NAME(m_dsp56156_bank01_ram));
save_item(NAME(m_dsp56156_bank02_ram));
save_item(NAME(m_dsp56156_shared_ram_16));
save_item(NAME(m_dsp56156_bank04_ram));
save_item(NAME(m_sys0));
save_item(NAME(m_sys1));
save_item(NAME(m_sound_ctrl));
@ -667,12 +667,12 @@ void polygonet_state::init_polygonet()
{
membank("bank1")->configure_entries(0, 8, memregion("audiocpu")->base(), 0x4000);
/* Allocate space for the dsp56k banking */
memset(m_dsp56k_bank00_ram, 0, sizeof(m_dsp56k_bank00_ram));
memset(m_dsp56k_bank01_ram, 0, sizeof(m_dsp56k_bank01_ram));
memset(m_dsp56k_bank02_ram, 0, sizeof(m_dsp56k_bank02_ram));
memset(m_dsp56k_shared_ram_16, 0, sizeof(m_dsp56k_shared_ram_16));
memset(m_dsp56k_bank04_ram, 0, sizeof(m_dsp56k_bank04_ram));
/* Allocate space for the dsp56156 banking */
memset(m_dsp56156_bank00_ram, 0, sizeof(m_dsp56156_bank00_ram));
memset(m_dsp56156_bank01_ram, 0, sizeof(m_dsp56156_bank01_ram));
memset(m_dsp56156_bank02_ram, 0, sizeof(m_dsp56156_bank02_ram));
memset(m_dsp56156_shared_ram_16, 0, sizeof(m_dsp56156_shared_ram_16));
memset(m_dsp56156_bank04_ram, 0, sizeof(m_dsp56156_bank04_ram));
}

54
src/mame/includes/plygonet.h
View File

@ -8,15 +8,15 @@
#include "machine/eepromser.h"
#include "machine/k054321.h"
#include "video/k053936.h"
#include "cpu/dsp56k/dsp56k.h"
#include "cpu/dsp56156/dsp56156.h"
#include "emupal.h"
static const uint16_t dsp56k_bank00_size = 0x1000;
static const uint16_t dsp56k_bank01_size = 0x1000;
static const uint16_t dsp56k_bank02_size = 0x4000;
static const uint16_t dsp56k_shared_ram_16_size = 0x2000;
static const uint16_t dsp56k_bank04_size = 0x1fc0;
static const uint16_t dsp56156_bank00_size = 0x1000;
static const uint16_t dsp56156_bank01_size = 0x1000;
static const uint16_t dsp56156_bank02_size = 0x4000;
static const uint16_t dsp56156_shared_ram_16_size = 0x2000;
static const uint16_t dsp56156_bank04_size = 0x1fc0;
class polygonet_state : public driver_device
{
@ -32,8 +32,8 @@ public:
m_palette(*this, "palette"),
m_k054321(*this, "k054321"),
m_shared_ram(*this, "shared_ram"),
m_dsp56k_p_mirror(*this, "dsp56k_p_mirror"),
m_dsp56k_p_8000(*this, "dsp56k_p_8000")
m_dsp56156_p_mirror(*this, "dsp56156_p_mirror"),
m_dsp56156_p_8000(*this, "dsp56156_p_8000")
{ }
void plygonet(machine_config &config);
@ -43,7 +43,7 @@ public:
private:
required_device<cpu_device> m_maincpu;
required_device<cpu_device> m_audiocpu;
required_device<dsp56k_device> m_dsp;
required_device<dsp56156_device> m_dsp;
required_device<eeprom_serial_er5911_device> m_eeprom;
required_device<k053936_device> m_k053936;
required_device<gfxdecode_device> m_gfxdecode;
@ -53,8 +53,8 @@ private:
/* 68k-side shared ram */
required_shared_ptr<uint32_t> m_shared_ram;
required_shared_ptr<uint16_t> m_dsp56k_p_mirror;
required_shared_ptr<uint16_t> m_dsp56k_p_8000;
required_shared_ptr<uint16_t> m_dsp56156_p_mirror;
required_shared_ptr<uint16_t> m_dsp56156_p_8000;
ioport_port *m_inputs[4];
uint8_t m_sys0;
@ -72,11 +72,11 @@ private:
uint8_t m_sound_intck;
/* memory buffers */
uint16_t m_dsp56k_bank00_ram[2 * 8 * dsp56k_bank00_size]; /* 2 bank sets, 8 potential banks each */
uint16_t m_dsp56k_bank01_ram[2 * 8 * dsp56k_bank01_size];
uint16_t m_dsp56k_bank02_ram[2 * 8 * dsp56k_bank02_size];
uint16_t m_dsp56k_shared_ram_16[2 * 8 * dsp56k_shared_ram_16_size];
uint16_t m_dsp56k_bank04_ram[2 * 8 * dsp56k_bank04_size];
uint16_t m_dsp56156_bank00_ram[2 * 8 * dsp56156_bank00_size]; /* 2 bank sets, 8 potential banks each */
uint16_t m_dsp56156_bank01_ram[2 * 8 * dsp56156_bank01_size];
uint16_t m_dsp56156_bank02_ram[2 * 8 * dsp56156_bank02_size];
uint16_t m_dsp56156_shared_ram_16[2 * 8 * dsp56156_shared_ram_16_size];
uint16_t m_dsp56156_bank04_ram[2 * 8 * dsp56156_bank04_size];
DECLARE_WRITE8_MEMBER(polygonet_sys_w);
DECLARE_READ8_MEMBER(polygonet_inputs_r);
@ -86,17 +86,17 @@ private:
DECLARE_WRITE32_MEMBER(dsp_w_lines);
DECLARE_WRITE32_MEMBER(dsp_host_interface_w);
DECLARE_READ32_MEMBER(network_r);
DECLARE_READ16_MEMBER(dsp56k_bootload_r);
DECLARE_READ16_MEMBER(dsp56k_ram_bank00_read);
DECLARE_WRITE16_MEMBER(dsp56k_ram_bank00_write);
DECLARE_READ16_MEMBER(dsp56k_ram_bank01_read);
DECLARE_WRITE16_MEMBER(dsp56k_ram_bank01_write);
DECLARE_READ16_MEMBER(dsp56k_ram_bank02_read);
DECLARE_WRITE16_MEMBER(dsp56k_ram_bank02_write);
DECLARE_READ16_MEMBER(dsp56k_shared_ram_read);
DECLARE_WRITE16_MEMBER(dsp56k_shared_ram_write);
DECLARE_READ16_MEMBER(dsp56k_ram_bank04_read);
DECLARE_WRITE16_MEMBER(dsp56k_ram_bank04_write);
DECLARE_READ16_MEMBER(dsp56156_bootload_r);
DECLARE_READ16_MEMBER(dsp56156_ram_bank00_read);
DECLARE_WRITE16_MEMBER(dsp56156_ram_bank00_write);
DECLARE_READ16_MEMBER(dsp56156_ram_bank01_read);
DECLARE_WRITE16_MEMBER(dsp56156_ram_bank01_write);
DECLARE_READ16_MEMBER(dsp56156_ram_bank02_read);
DECLARE_WRITE16_MEMBER(dsp56156_ram_bank02_write);
DECLARE_READ16_MEMBER(dsp56156_shared_ram_read);
DECLARE_WRITE16_MEMBER(dsp56156_shared_ram_write);
DECLARE_READ16_MEMBER(dsp56156_ram_bank04_read);
DECLARE_WRITE16_MEMBER(dsp56156_ram_bank04_write);
DECLARE_WRITE8_MEMBER(sound_ctrl_w);
DECLARE_READ32_MEMBER(polygonet_ttl_ram_r);
DECLARE_WRITE32_MEMBER(polygonet_ttl_ram_w);