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cosmetics

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This commit is contained in:
Laurent Desnogues 2008-02-16 16:35:07 +00:00
parent e921749bc1
commit 4839044063
3 changed files with 1018 additions and 1018 deletions
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533
src/emu/cpu/arm7/arm7.c
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@ -42,17 +42,17 @@
/* Example for showing how Co-Proc functions work */
#define TEST_COPROC_FUNCS 1
/*prototypes*/
/* prototypes */
#if TEST_COPROC_FUNCS
static WRITE32_HANDLER(test_do_callback);
static READ32_HANDLER(test_rt_r_callback);
static WRITE32_HANDLER(test_rt_w_callback);
static void test_dt_r_callback (UINT32 insn, UINT32* prn, UINT32 (*read32)(int addr));
static void test_dt_w_callback (UINT32 insn, UINT32* prn, void (*write32)(int addr, UINT32 data));
static void test_dt_r_callback(UINT32 insn, UINT32 *prn, UINT32 (*read32)(UINT32 addr));
static void test_dt_w_callback(UINT32 insn, UINT32 *prn, void (*write32)(UINT32 addr, UINT32 data));
#ifdef ENABLE_DEBUGGER
static char *Spec_RT( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
static char *Spec_DT( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
static char *Spec_DO( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
static char *Spec_RT(char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
static char *Spec_DT(char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
static char *Spec_DO(char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
#endif
#endif
@ -76,7 +76,7 @@ static char *Spec_DO( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBu
/* CPU Registers */
typedef struct
{
ARM7CORE_REGS //these must be included in your cpu specific register implementation
ARM7CORE_REGS // these must be included in your cpu specific register implementation
} ARM7_REGS;
static ARM7_REGS arm7;
@ -90,80 +90,78 @@ static int ARM7_ICOUNT;
**************************************************************************/
static void arm7_init(int index, int clock, const void *config, int (*irqcallback)(int))
{
//must call core
arm7_core_init("arm7", index);
// must call core
arm7_core_init("arm7", index);
ARM7.irq_callback = irqcallback;
ARM7.irq_callback = irqcallback;
#if TEST_COPROC_FUNCS
//setup co-proc callbacks example
arm7_coproc_do_callback = test_do_callback;
arm7_coproc_rt_r_callback = test_rt_r_callback;
arm7_coproc_rt_w_callback = test_rt_w_callback;
arm7_coproc_dt_r_callback = test_dt_r_callback;
arm7_coproc_dt_w_callback = test_dt_w_callback;
// setup co-proc callbacks example
arm7_coproc_do_callback = test_do_callback;
arm7_coproc_rt_r_callback = test_rt_r_callback;
arm7_coproc_rt_w_callback = test_rt_w_callback;
arm7_coproc_dt_r_callback = test_dt_r_callback;
arm7_coproc_dt_w_callback = test_dt_w_callback;
#ifdef ENABLE_DEBUGGER
//setup dasm callbacks - direct method example
arm7_dasm_cop_dt_callback = Spec_DT;
arm7_dasm_cop_rt_callback = Spec_RT;
arm7_dasm_cop_do_callback = Spec_DO;
// setup dasm callbacks - direct method example
arm7_dasm_cop_dt_callback = Spec_DT;
arm7_dasm_cop_rt_callback = Spec_RT;
arm7_dasm_cop_do_callback = Spec_DO;
#endif
#endif
return;
}
static void arm7_reset(void)
{
//must call core reset
arm7_core_reset();
// must call core reset
arm7_core_reset();
}
static void arm7_exit(void)
{
/* nothing to do here */
/* nothing to do here */
}
static int arm7_execute( int cycles )
static int arm7_execute(int cycles)
{
/*include the arm7 core execute code*/
/* include the arm7 core execute code */
#include "arm7exec.c"
} /* arm7_execute */
}
static void set_irq_line(int irqline, int state)
{
//must call core
arm7_core_set_irq_line(irqline,state);
// must call core
arm7_core_set_irq_line(irqline,state);
}
static void arm7_get_context(void *dst)
{
if( dst )
{
memcpy( dst, &ARM7, sizeof(ARM7) );
}
if (dst)
{
memcpy(dst, &ARM7, sizeof(ARM7));
}
}
static void arm7_set_context(void *src)
{
if (src)
{
memcpy( &ARM7, src, sizeof(ARM7) );
}
if (src)
{
memcpy(&ARM7, src, sizeof(ARM7));
}
}
#ifdef ENABLE_DEBUGGER
static offs_t arm7_dasm(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram)
{
if( T_IS_SET(GET_CPSR) )
{
return thumb_disasm( buffer, pc, oprom[0] | (oprom[1] << 8)) | 2;
}
else
{
return arm7_disasm( buffer, pc, oprom[0] | (oprom[1] << 8) | (oprom[2] << 16) | (oprom[3] << 24)) | 4;
}
if (T_IS_SET(GET_CPSR))
{
return thumb_disasm(buffer, pc, oprom[0] | (oprom[1] << 8)) | 2;
}
else
{
return arm7_disasm(buffer, pc, oprom[0] | (oprom[1] << 8) | (oprom[2] << 16) | (oprom[3] << 24)) | 4;
}
}
#endif /* ENABLE_DEBUGGER */
@ -174,70 +172,70 @@ static offs_t arm7_dasm(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8
static void arm7_set_info(UINT32 state, cpuinfo *info)
{
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
/* interrupt lines/exceptions */
case CPUINFO_INT_INPUT_STATE + ARM7_IRQ_LINE: set_irq_line(ARM7_IRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + ARM7_FIRQ_LINE: set_irq_line(ARM7_FIRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_EXCEPTION: set_irq_line(ARM7_ABORT_EXCEPTION, info->i); break;
case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_PREFETCH_EXCEPTION: set_irq_line(ARM7_ABORT_PREFETCH_EXCEPTION, info->i); break;
case CPUINFO_INT_INPUT_STATE + ARM7_UNDEFINE_EXCEPTION: set_irq_line(ARM7_UNDEFINE_EXCEPTION, info->i); break;
/* interrupt lines/exceptions */
case CPUINFO_INT_INPUT_STATE + ARM7_IRQ_LINE: set_irq_line(ARM7_IRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + ARM7_FIRQ_LINE: set_irq_line(ARM7_FIRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_EXCEPTION: set_irq_line(ARM7_ABORT_EXCEPTION, info->i); break;
case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_PREFETCH_EXCEPTION: set_irq_line(ARM7_ABORT_PREFETCH_EXCEPTION, info->i); break;
case CPUINFO_INT_INPUT_STATE + ARM7_UNDEFINE_EXCEPTION: set_irq_line(ARM7_UNDEFINE_EXCEPTION, info->i); break;
/* registers shared by all operating modes */
case CPUINFO_INT_REGISTER + ARM7_R0: ARM7REG( 0) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R1: ARM7REG( 1) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R2: ARM7REG( 2) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R3: ARM7REG( 3) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R4: ARM7REG( 4) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R5: ARM7REG( 5) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R6: ARM7REG( 6) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R7: ARM7REG( 7) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R8: ARM7REG( 8) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R9: ARM7REG( 9) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R10: ARM7REG(10) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R11: ARM7REG(11) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R12: ARM7REG(12) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R13: ARM7REG(13) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R14: ARM7REG(14) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R15: ARM7REG(15) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_CPSR: SET_CPSR(info->i); break;
/* registers shared by all operating modes */
case CPUINFO_INT_REGISTER + ARM7_R0: ARM7REG( 0) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R1: ARM7REG( 1) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R2: ARM7REG( 2) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R3: ARM7REG( 3) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R4: ARM7REG( 4) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R5: ARM7REG( 5) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R6: ARM7REG( 6) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R7: ARM7REG( 7) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R8: ARM7REG( 8) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R9: ARM7REG( 9) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R10: ARM7REG(10) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R11: ARM7REG(11) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R12: ARM7REG(12) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R13: ARM7REG(13) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R14: ARM7REG(14) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_R15: ARM7REG(15) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_CPSR: SET_CPSR(info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + ARM7_PC: R15 = info->i; break;
case CPUINFO_INT_SP: SetRegister(13,info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + ARM7_PC: R15 = info->i; break;
case CPUINFO_INT_SP: SetRegister(13,info->i); break;
/* FIRQ Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_FR8: ARM7REG(eR8_FIQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_FR9: ARM7REG(eR9_FIQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_FR10: ARM7REG(eR10_FIQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_FR11: ARM7REG(eR11_FIQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_FR12: ARM7REG(eR12_FIQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_FR13: ARM7REG(eR13_FIQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_FR14: ARM7REG(eR14_FIQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_FSPSR: ARM7REG(eSPSR_FIQ) = info->i; break;
/* FIRQ Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_FR8: ARM7REG(eR8_FIQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_FR9: ARM7REG(eR9_FIQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_FR10: ARM7REG(eR10_FIQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_FR11: ARM7REG(eR11_FIQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_FR12: ARM7REG(eR12_FIQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_FR13: ARM7REG(eR13_FIQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_FR14: ARM7REG(eR14_FIQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_FSPSR: ARM7REG(eSPSR_FIQ) = info->i; break;
/* IRQ Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_IR13: ARM7REG(eR13_IRQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_IR14: ARM7REG(eR14_IRQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_ISPSR: ARM7REG(eSPSR_IRQ) = info->i; break;
/* IRQ Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_IR13: ARM7REG(eR13_IRQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_IR14: ARM7REG(eR14_IRQ) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_ISPSR: ARM7REG(eSPSR_IRQ) = info->i; break;
/* Supervisor Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_SR13: ARM7REG(eR13_SVC) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_SR14: ARM7REG(eR14_SVC) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_SSPSR: ARM7REG(eSPSR_SVC) = info->i; break;
/* Supervisor Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_SR13: ARM7REG(eR13_SVC) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_SR14: ARM7REG(eR14_SVC) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_SSPSR: ARM7REG(eSPSR_SVC) = info->i; break;
/* Abort Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_AR13: ARM7REG(eR13_ABT) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_AR14: ARM7REG(eR14_ABT) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_ASPSR: ARM7REG(eSPSR_ABT) = info->i; break;
/* Abort Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_AR13: ARM7REG(eR13_ABT) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_AR14: ARM7REG(eR14_ABT) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_ASPSR: ARM7REG(eSPSR_ABT) = info->i; break;
/* Undefined Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_UR13: ARM7REG(eR13_UND) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_UR14: ARM7REG(eR14_UND) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_USPSR: ARM7REG(eSPSR_UND) = info->i; break;
}
/* Undefined Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_UR13: ARM7REG(eR13_UND) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_UR14: ARM7REG(eR14_UND) = info->i; break;
case CPUINFO_INT_REGISTER + ARM7_USPSR: ARM7REG(eSPSR_UND) = info->i; break;
}
}
@ -248,174 +246,174 @@ static void arm7_set_info(UINT32 state, cpuinfo *info)
void arm7_get_info(UINT32 state, cpuinfo *info)
{
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
/* cpu implementation data */
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(ARM7); break;
case CPUINFO_INT_INPUT_LINES: info->i = ARM7_NUM_LINES; break;
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break;
case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break;
case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break;
case CPUINFO_INT_MIN_CYCLES: info->i = 3; break;
case CPUINFO_INT_MAX_CYCLES: info->i = 4; break;
/* cpu implementation data */
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(ARM7); break;
case CPUINFO_INT_INPUT_LINES: info->i = ARM7_NUM_LINES; break;
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break;
case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break;
case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break;
case CPUINFO_INT_MIN_CYCLES: info->i = 3; break;
case CPUINFO_INT_MAX_CYCLES: info->i = 4; break;
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 32; break;
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 32; break;
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = 0; break;
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = 0; break;
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 32; break;
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_PROGRAM: info->i = 32; break;
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_PROGRAM: info->i = 0; break;
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_DATA: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_DATA: info->i = 0; break;
case CPUINFO_INT_DATABUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
/* interrupt lines/exceptions */
case CPUINFO_INT_INPUT_STATE + ARM7_IRQ_LINE: info->i = ARM7.pendingIrq; break;
case CPUINFO_INT_INPUT_STATE + ARM7_FIRQ_LINE: info->i = ARM7.pendingFiq; break;
case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_EXCEPTION: info->i = ARM7.pendingAbtD; break;
case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_PREFETCH_EXCEPTION: info->i = ARM7.pendingAbtP; break;
case CPUINFO_INT_INPUT_STATE + ARM7_UNDEFINE_EXCEPTION: info->i = ARM7.pendingUnd; break;
/* interrupt lines/exceptions */
case CPUINFO_INT_INPUT_STATE + ARM7_IRQ_LINE: info->i = ARM7.pendingIrq; break;
case CPUINFO_INT_INPUT_STATE + ARM7_FIRQ_LINE: info->i = ARM7.pendingFiq; break;
case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_EXCEPTION: info->i = ARM7.pendingAbtD; break;
case CPUINFO_INT_INPUT_STATE + ARM7_ABORT_PREFETCH_EXCEPTION: info->i = ARM7.pendingAbtP; break;
case CPUINFO_INT_INPUT_STATE + ARM7_UNDEFINE_EXCEPTION: info->i = ARM7.pendingUnd; break;
/* registers shared by all operating modes */
case CPUINFO_INT_REGISTER + ARM7_R0: info->i = ARM7REG( 0); break;
case CPUINFO_INT_REGISTER + ARM7_R1: info->i = ARM7REG( 1); break;
case CPUINFO_INT_REGISTER + ARM7_R2: info->i = ARM7REG( 2); break;
case CPUINFO_INT_REGISTER + ARM7_R3: info->i = ARM7REG( 3); break;
case CPUINFO_INT_REGISTER + ARM7_R4: info->i = ARM7REG( 4); break;
case CPUINFO_INT_REGISTER + ARM7_R5: info->i = ARM7REG( 5); break;
case CPUINFO_INT_REGISTER + ARM7_R6: info->i = ARM7REG( 6); break;
case CPUINFO_INT_REGISTER + ARM7_R7: info->i = ARM7REG( 7); break;
case CPUINFO_INT_REGISTER + ARM7_R8: info->i = ARM7REG( 8); break;
case CPUINFO_INT_REGISTER + ARM7_R9: info->i = ARM7REG( 9); break;
case CPUINFO_INT_REGISTER + ARM7_R10: info->i = ARM7REG(10); break;
case CPUINFO_INT_REGISTER + ARM7_R11: info->i = ARM7REG(11); break;
case CPUINFO_INT_REGISTER + ARM7_R12: info->i = ARM7REG(12); break;
case CPUINFO_INT_REGISTER + ARM7_R13: info->i = ARM7REG(13); break;
case CPUINFO_INT_REGISTER + ARM7_R14: info->i = ARM7REG(14); break;
case CPUINFO_INT_REGISTER + ARM7_R15: info->i = ARM7REG(15); break;
/* registers shared by all operating modes */
case CPUINFO_INT_REGISTER + ARM7_R0: info->i = ARM7REG( 0); break;
case CPUINFO_INT_REGISTER + ARM7_R1: info->i = ARM7REG( 1); break;
case CPUINFO_INT_REGISTER + ARM7_R2: info->i = ARM7REG( 2); break;
case CPUINFO_INT_REGISTER + ARM7_R3: info->i = ARM7REG( 3); break;
case CPUINFO_INT_REGISTER + ARM7_R4: info->i = ARM7REG( 4); break;
case CPUINFO_INT_REGISTER + ARM7_R5: info->i = ARM7REG( 5); break;
case CPUINFO_INT_REGISTER + ARM7_R6: info->i = ARM7REG( 6); break;
case CPUINFO_INT_REGISTER + ARM7_R7: info->i = ARM7REG( 7); break;
case CPUINFO_INT_REGISTER + ARM7_R8: info->i = ARM7REG( 8); break;
case CPUINFO_INT_REGISTER + ARM7_R9: info->i = ARM7REG( 9); break;
case CPUINFO_INT_REGISTER + ARM7_R10: info->i = ARM7REG(10); break;
case CPUINFO_INT_REGISTER + ARM7_R11: info->i = ARM7REG(11); break;
case CPUINFO_INT_REGISTER + ARM7_R12: info->i = ARM7REG(12); break;
case CPUINFO_INT_REGISTER + ARM7_R13: info->i = ARM7REG(13); break;
case CPUINFO_INT_REGISTER + ARM7_R14: info->i = ARM7REG(14); break;
case CPUINFO_INT_REGISTER + ARM7_R15: info->i = ARM7REG(15); break;
case CPUINFO_INT_PREVIOUSPC: info->i = 0; /* not implemented */ break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + ARM7_PC: info->i = R15; break;
case CPUINFO_INT_SP: info->i = GetRegister(13); break;
case CPUINFO_INT_PREVIOUSPC: info->i = 0; /* not implemented */ break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + ARM7_PC: info->i = R15; break;
case CPUINFO_INT_SP: info->i = GetRegister(13); break;
/* FIRQ Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_FR8: info->i = ARM7REG(eR8_FIQ); break;
case CPUINFO_INT_REGISTER + ARM7_FR9: info->i = ARM7REG(eR9_FIQ); break;
case CPUINFO_INT_REGISTER + ARM7_FR10: info->i = ARM7REG(eR10_FIQ); break;
case CPUINFO_INT_REGISTER + ARM7_FR11: info->i = ARM7REG(eR11_FIQ); break;
case CPUINFO_INT_REGISTER + ARM7_FR12: info->i = ARM7REG(eR12_FIQ); break;
case CPUINFO_INT_REGISTER + ARM7_FR13: info->i = ARM7REG(eR13_FIQ); break;
case CPUINFO_INT_REGISTER + ARM7_FR14: info->i = ARM7REG(eR14_FIQ); break;
case CPUINFO_INT_REGISTER + ARM7_FSPSR: info->i = ARM7REG(eSPSR_FIQ); break;
/* FIRQ Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_FR8: info->i = ARM7REG(eR8_FIQ); break;
case CPUINFO_INT_REGISTER + ARM7_FR9: info->i = ARM7REG(eR9_FIQ); break;
case CPUINFO_INT_REGISTER + ARM7_FR10: info->i = ARM7REG(eR10_FIQ); break;
case CPUINFO_INT_REGISTER + ARM7_FR11: info->i = ARM7REG(eR11_FIQ); break;
case CPUINFO_INT_REGISTER + ARM7_FR12: info->i = ARM7REG(eR12_FIQ); break;
case CPUINFO_INT_REGISTER + ARM7_FR13: info->i = ARM7REG(eR13_FIQ); break;
case CPUINFO_INT_REGISTER + ARM7_FR14: info->i = ARM7REG(eR14_FIQ); break;
case CPUINFO_INT_REGISTER + ARM7_FSPSR: info->i = ARM7REG(eSPSR_FIQ); break;
/* IRQ Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_IR13: info->i = ARM7REG(eR13_IRQ); break;
case CPUINFO_INT_REGISTER + ARM7_IR14: info->i = ARM7REG(eR14_IRQ); break;
case CPUINFO_INT_REGISTER + ARM7_ISPSR: info->i = ARM7REG(eSPSR_IRQ); break;
/* IRQ Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_IR13: info->i = ARM7REG(eR13_IRQ); break;
case CPUINFO_INT_REGISTER + ARM7_IR14: info->i = ARM7REG(eR14_IRQ); break;
case CPUINFO_INT_REGISTER + ARM7_ISPSR: info->i = ARM7REG(eSPSR_IRQ); break;
/* Supervisor Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_SR13: info->i = ARM7REG(eR13_SVC); break;
case CPUINFO_INT_REGISTER + ARM7_SR14: info->i = ARM7REG(eR14_SVC); break;
case CPUINFO_INT_REGISTER + ARM7_SSPSR: info->i = ARM7REG(eSPSR_SVC); break;
/* Supervisor Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_SR13: info->i = ARM7REG(eR13_SVC); break;
case CPUINFO_INT_REGISTER + ARM7_SR14: info->i = ARM7REG(eR14_SVC); break;
case CPUINFO_INT_REGISTER + ARM7_SSPSR: info->i = ARM7REG(eSPSR_SVC); break;
/* Abort Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_AR13: info->i = ARM7REG(eR13_ABT); break;
case CPUINFO_INT_REGISTER + ARM7_AR14: info->i = ARM7REG(eR14_ABT); break;
case CPUINFO_INT_REGISTER + ARM7_ASPSR: info->i = ARM7REG(eSPSR_ABT); break;
/* Abort Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_AR13: info->i = ARM7REG(eR13_ABT); break;
case CPUINFO_INT_REGISTER + ARM7_AR14: info->i = ARM7REG(eR14_ABT); break;
case CPUINFO_INT_REGISTER + ARM7_ASPSR: info->i = ARM7REG(eSPSR_ABT); break;
/* Undefined Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_UR13: info->i = ARM7REG(eR13_UND); break;
case CPUINFO_INT_REGISTER + ARM7_UR14: info->i = ARM7REG(eR14_UND); break;
case CPUINFO_INT_REGISTER + ARM7_USPSR: info->i = ARM7REG(eSPSR_UND); break;
/* Undefined Mode Shadowed Registers */
case CPUINFO_INT_REGISTER + ARM7_UR13: info->i = ARM7REG(eR13_UND); break;
case CPUINFO_INT_REGISTER + ARM7_UR14: info->i = ARM7REG(eR14_UND); break;
case CPUINFO_INT_REGISTER + ARM7_USPSR: info->i = ARM7REG(eSPSR_UND); break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_PTR_SET_INFO: info->setinfo = arm7_set_info; break;
case CPUINFO_PTR_GET_CONTEXT: info->getcontext = arm7_get_context; break;
case CPUINFO_PTR_SET_CONTEXT: info->setcontext = arm7_set_context; break;
case CPUINFO_PTR_INIT: info->init = arm7_init; break;
case CPUINFO_PTR_RESET: info->reset = arm7_reset; break;
case CPUINFO_PTR_EXIT: info->exit = arm7_exit; break;
case CPUINFO_PTR_EXECUTE: info->execute = arm7_execute; break;
case CPUINFO_PTR_BURN: info->burn = NULL; break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_PTR_SET_INFO: info->setinfo = arm7_set_info; break;
case CPUINFO_PTR_GET_CONTEXT: info->getcontext = arm7_get_context; break;
case CPUINFO_PTR_SET_CONTEXT: info->setcontext = arm7_set_context; break;
case CPUINFO_PTR_INIT: info->init = arm7_init; break;
case CPUINFO_PTR_RESET: info->reset = arm7_reset; break;
case CPUINFO_PTR_EXIT: info->exit = arm7_exit; break;
case CPUINFO_PTR_EXECUTE: info->execute = arm7_execute; break;
case CPUINFO_PTR_BURN: info->burn = NULL; break;
#ifdef ENABLE_DEBUGGER
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = arm7_dasm; break;
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = arm7_dasm; break;
#endif /* ENABLE_DEBUGGER */
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &ARM7_ICOUNT; break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &ARM7_ICOUNT; break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "ARM7"); break;
case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "Acorn Risc Machine"); break;
case CPUINFO_STR_CORE_VERSION: strcpy(info->s, "1.3"); break;
case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break;
case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Copyright Steve Ellenoff, sellenoff@hotmail.com"); break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "ARM7"); break;
case CPUINFO_STR_CORE_FAMILY: strcpy(info->s, "Acorn Risc Machine"); break;
case CPUINFO_STR_CORE_VERSION: strcpy(info->s, "1.3"); break;
case CPUINFO_STR_CORE_FILE: strcpy(info->s, __FILE__); break;
case CPUINFO_STR_CORE_CREDITS: strcpy(info->s, "Copyright Steve Ellenoff, sellenoff@hotmail.com"); break;
case CPUINFO_STR_FLAGS:
sprintf(info->s, "%c%c%c%c%c%c%c %s",
(ARM7REG(eCPSR) & N_MASK) ? 'N' : '-',
(ARM7REG(eCPSR) & Z_MASK) ? 'Z' : '-',
(ARM7REG(eCPSR) & C_MASK) ? 'C' : '-',
(ARM7REG(eCPSR) & V_MASK) ? 'V' : '-',
(ARM7REG(eCPSR) & I_MASK) ? 'I' : '-',
(ARM7REG(eCPSR) & F_MASK) ? 'F' : '-',
(ARM7REG(eCPSR) & T_MASK) ? 'T' : '-',
GetModeText(ARM7REG(eCPSR)));
break;
case CPUINFO_STR_FLAGS:
sprintf(info->s, "%c%c%c%c%c%c%c %s",
(ARM7REG(eCPSR) & N_MASK) ? 'N' : '-',
(ARM7REG(eCPSR) & Z_MASK) ? 'Z' : '-',
(ARM7REG(eCPSR) & C_MASK) ? 'C' : '-',
(ARM7REG(eCPSR) & V_MASK) ? 'V' : '-',
(ARM7REG(eCPSR) & I_MASK) ? 'I' : '-',
(ARM7REG(eCPSR) & F_MASK) ? 'F' : '-',
(ARM7REG(eCPSR) & T_MASK) ? 'T' : '-',
GetModeText(ARM7REG(eCPSR)));
break;
/* registers shared by all operating modes */
case CPUINFO_STR_REGISTER + ARM7_PC: sprintf(info->s, "PC :%08x", R15 ); break;
case CPUINFO_STR_REGISTER + ARM7_R0: sprintf(info->s, "R0 :%08x", ARM7REG( 0) ); break;
case CPUINFO_STR_REGISTER + ARM7_R1: sprintf(info->s, "R1 :%08x", ARM7REG( 1) ); break;
case CPUINFO_STR_REGISTER + ARM7_R2: sprintf(info->s, "R2 :%08x", ARM7REG( 2) ); break;
case CPUINFO_STR_REGISTER + ARM7_R3: sprintf(info->s, "R3 :%08x", ARM7REG( 3) ); break;
case CPUINFO_STR_REGISTER + ARM7_R4: sprintf(info->s, "R4 :%08x", ARM7REG( 4) ); break;
case CPUINFO_STR_REGISTER + ARM7_R5: sprintf(info->s, "R5 :%08x", ARM7REG( 5) ); break;
case CPUINFO_STR_REGISTER + ARM7_R6: sprintf(info->s, "R6 :%08x", ARM7REG( 6) ); break;
case CPUINFO_STR_REGISTER + ARM7_R7: sprintf(info->s, "R7 :%08x", ARM7REG( 7) ); break;
case CPUINFO_STR_REGISTER + ARM7_R8: sprintf(info->s, "R8 :%08x", ARM7REG( 8) ); break;
case CPUINFO_STR_REGISTER + ARM7_R9: sprintf(info->s, "R9 :%08x", ARM7REG( 9) ); break;
case CPUINFO_STR_REGISTER + ARM7_R10: sprintf(info->s, "R10 :%08x", ARM7REG(10) ); break;
case CPUINFO_STR_REGISTER + ARM7_R11: sprintf(info->s, "R11 :%08x", ARM7REG(11) ); break;
case CPUINFO_STR_REGISTER + ARM7_R12: sprintf(info->s, "R12 :%08x", ARM7REG(12) ); break;
case CPUINFO_STR_REGISTER + ARM7_R13: sprintf(info->s, "R13 :%08x", ARM7REG(13) ); break;
case CPUINFO_STR_REGISTER + ARM7_R14: sprintf(info->s, "R14 :%08x", ARM7REG(14) ); break;
case CPUINFO_STR_REGISTER + ARM7_R15: sprintf(info->s, "R15 :%08x", ARM7REG(15) ); break;
/* registers shared by all operating modes */
case CPUINFO_STR_REGISTER + ARM7_PC: sprintf(info->s, "PC :%08x", R15); break;
case CPUINFO_STR_REGISTER + ARM7_R0: sprintf(info->s, "R0 :%08x", ARM7REG( 0)); break;
case CPUINFO_STR_REGISTER + ARM7_R1: sprintf(info->s, "R1 :%08x", ARM7REG( 1)); break;
case CPUINFO_STR_REGISTER + ARM7_R2: sprintf(info->s, "R2 :%08x", ARM7REG( 2)); break;
case CPUINFO_STR_REGISTER + ARM7_R3: sprintf(info->s, "R3 :%08x", ARM7REG( 3)); break;
case CPUINFO_STR_REGISTER + ARM7_R4: sprintf(info->s, "R4 :%08x", ARM7REG( 4)); break;
case CPUINFO_STR_REGISTER + ARM7_R5: sprintf(info->s, "R5 :%08x", ARM7REG( 5)); break;
case CPUINFO_STR_REGISTER + ARM7_R6: sprintf(info->s, "R6 :%08x", ARM7REG( 6)); break;
case CPUINFO_STR_REGISTER + ARM7_R7: sprintf(info->s, "R7 :%08x", ARM7REG( 7)); break;
case CPUINFO_STR_REGISTER + ARM7_R8: sprintf(info->s, "R8 :%08x", ARM7REG( 8)); break;
case CPUINFO_STR_REGISTER + ARM7_R9: sprintf(info->s, "R9 :%08x", ARM7REG( 9)); break;
case CPUINFO_STR_REGISTER + ARM7_R10: sprintf(info->s, "R10 :%08x", ARM7REG(10)); break;
case CPUINFO_STR_REGISTER + ARM7_R11: sprintf(info->s, "R11 :%08x", ARM7REG(11)); break;
case CPUINFO_STR_REGISTER + ARM7_R12: sprintf(info->s, "R12 :%08x", ARM7REG(12)); break;
case CPUINFO_STR_REGISTER + ARM7_R13: sprintf(info->s, "R13 :%08x", ARM7REG(13)); break;
case CPUINFO_STR_REGISTER + ARM7_R14: sprintf(info->s, "R14 :%08x", ARM7REG(14)); break;
case CPUINFO_STR_REGISTER + ARM7_R15: sprintf(info->s, "R15 :%08x", ARM7REG(15)); break;
/* FIRQ Mode Shadowed Registers */
case CPUINFO_STR_REGISTER + ARM7_FR8: sprintf(info->s, "FR8 :%08x", ARM7REG(eR8_FIQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_FR9: sprintf(info->s, "FR9 :%08x", ARM7REG(eR9_FIQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_FR10: sprintf(info->s, "FR10:%08x", ARM7REG(eR10_FIQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_FR11: sprintf(info->s, "FR11:%08x", ARM7REG(eR11_FIQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_FR12: sprintf(info->s, "FR12:%08x", ARM7REG(eR12_FIQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_FR13: sprintf(info->s, "FR13:%08x", ARM7REG(eR13_FIQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_FR14: sprintf(info->s, "FR14:%08x", ARM7REG(eR14_FIQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_FSPSR: sprintf(info->s, "FR16:%08x", ARM7REG(eSPSR_FIQ)); break;
/* FIRQ Mode Shadowed Registers */
case CPUINFO_STR_REGISTER + ARM7_FR8: sprintf(info->s, "FR8 :%08x", ARM7REG(eR8_FIQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_FR9: sprintf(info->s, "FR9 :%08x", ARM7REG(eR9_FIQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_FR10: sprintf(info->s, "FR10:%08x", ARM7REG(eR10_FIQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_FR11: sprintf(info->s, "FR11:%08x", ARM7REG(eR11_FIQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_FR12: sprintf(info->s, "FR12:%08x", ARM7REG(eR12_FIQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_FR13: sprintf(info->s, "FR13:%08x", ARM7REG(eR13_FIQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_FR14: sprintf(info->s, "FR14:%08x", ARM7REG(eR14_FIQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_FSPSR: sprintf(info->s, "FR16:%08x", ARM7REG(eSPSR_FIQ)); break;
/* IRQ Mode Shadowed Registers */
case CPUINFO_STR_REGISTER + ARM7_IR13: sprintf(info->s, "IR13:%08x", ARM7REG(eR13_IRQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_IR14: sprintf(info->s, "IR14:%08x", ARM7REG(eR14_IRQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_ISPSR: sprintf(info->s, "IR16:%08x", ARM7REG(eSPSR_IRQ)); break;
/* IRQ Mode Shadowed Registers */
case CPUINFO_STR_REGISTER + ARM7_IR13: sprintf(info->s, "IR13:%08x", ARM7REG(eR13_IRQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_IR14: sprintf(info->s, "IR14:%08x", ARM7REG(eR14_IRQ) ); break;
case CPUINFO_STR_REGISTER + ARM7_ISPSR: sprintf(info->s, "IR16:%08x", ARM7REG(eSPSR_IRQ)); break;
/* Supervisor Mode Shadowed Registers */
case CPUINFO_STR_REGISTER + ARM7_SR13: sprintf(info->s, "SR13:%08x", ARM7REG(eR13_SVC) ); break;
case CPUINFO_STR_REGISTER + ARM7_SR14: sprintf(info->s, "SR14:%08x", ARM7REG(eR14_SVC) ); break;
case CPUINFO_STR_REGISTER + ARM7_SSPSR: sprintf(info->s, "SR16:%08x", ARM7REG(eSPSR_SVC)); break;
/* Supervisor Mode Shadowed Registers */
case CPUINFO_STR_REGISTER + ARM7_SR13: sprintf(info->s, "SR13:%08x", ARM7REG(eR13_SVC) ); break;
case CPUINFO_STR_REGISTER + ARM7_SR14: sprintf(info->s, "SR14:%08x", ARM7REG(eR14_SVC) ); break;
case CPUINFO_STR_REGISTER + ARM7_SSPSR: sprintf(info->s, "SR16:%08x", ARM7REG(eSPSR_SVC)); break;
/* Abort Mode Shadowed Registers */
case CPUINFO_STR_REGISTER + ARM7_AR13: sprintf(info->s, "AR13:%08x", ARM7REG(eR13_ABT) ); break;
case CPUINFO_STR_REGISTER + ARM7_AR14: sprintf(info->s, "AR14:%08x", ARM7REG(eR14_ABT) ); break;
case CPUINFO_STR_REGISTER + ARM7_ASPSR: sprintf(info->s, "AR16:%08x", ARM7REG(eSPSR_ABT)); break;
/* Abort Mode Shadowed Registers */
case CPUINFO_STR_REGISTER + ARM7_AR13: sprintf(info->s, "AR13:%08x", ARM7REG(eR13_ABT) ); break;
case CPUINFO_STR_REGISTER + ARM7_AR14: sprintf(info->s, "AR14:%08x", ARM7REG(eR14_ABT) ); break;
case CPUINFO_STR_REGISTER + ARM7_ASPSR: sprintf(info->s, "AR16:%08x", ARM7REG(eSPSR_ABT)); break;
/* Undefined Mode Shadowed Registers */
case CPUINFO_STR_REGISTER + ARM7_UR13: sprintf(info->s, "UR13:%08x", ARM7REG(eR13_UND) ); break;
case CPUINFO_STR_REGISTER + ARM7_UR14: sprintf(info->s, "UR14:%08x", ARM7REG(eR14_UND) ); break;
case CPUINFO_STR_REGISTER + ARM7_USPSR: sprintf(info->s, "UR16:%08x", ARM7REG(eSPSR_UND)); break;
}
/* Undefined Mode Shadowed Registers */
case CPUINFO_STR_REGISTER + ARM7_UR13: sprintf(info->s, "UR13:%08x", ARM7REG(eR13_UND) ); break;
case CPUINFO_STR_REGISTER + ARM7_UR14: sprintf(info->s, "UR14:%08x", ARM7REG(eR14_UND) ); break;
case CPUINFO_STR_REGISTER + ARM7_USPSR: sprintf(info->s, "UR16:%08x", ARM7REG(eSPSR_UND)); break;
}
}
/* TEST COPROC CALLBACK HANDLERS - Used for example on how to implement only */
@ -423,44 +421,43 @@ void arm7_get_info(UINT32 state, cpuinfo *info)
static WRITE32_HANDLER(test_do_callback)
{
LOG(("test_do_callback opcode=%x, =%x\n",offset,data));
LOG(("test_do_callback opcode=%x, =%x\n", offset, data));
}
static READ32_HANDLER(test_rt_r_callback)
{
UINT32 data=0;
LOG(("test_rt_r_callback opcode=%x\n",offset));
return data;
UINT32 data=0;
LOG(("test_rt_r_callback opcode=%x\n", offset));
return data;
}
static WRITE32_HANDLER(test_rt_w_callback)
{
LOG(("test_rt_w_callback opcode=%x, data from ARM7 register=%x\n",offset,data));
LOG(("test_rt_w_callback opcode=%x, data from ARM7 register=%x\n", offset, data));
}
static void test_dt_r_callback (UINT32 insn, UINT32* prn, UINT32 (*read32)(int addr))
static void test_dt_r_callback(UINT32 insn, UINT32 *prn, UINT32 (*read32)(UINT32 addr))
{
LOG(("test_dt_r_callback: insn = %x\n",insn));
LOG(("test_dt_r_callback: insn = %x\n", insn));
}
static void test_dt_w_callback (UINT32 insn, UINT32* prn, void (*write32)(int addr, UINT32 data))
static void test_dt_w_callback(UINT32 insn, UINT32 *prn, void (*write32)(UINT32 addr, UINT32 data))
{
LOG(("test_dt_w_callback: opcode = %x\n",insn));
LOG(("test_dt_w_callback: opcode = %x\n", insn));
}
/* Custom Co-proc DASM handlers */
#ifdef ENABLE_DEBUGGER
static char *Spec_RT( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0)
static char *Spec_RT(char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0)
{
pBuf += sprintf( pBuf, "SPECRT");
return pBuf;
pBuf += sprintf(pBuf, "SPECRT");
return pBuf;
}
static char *Spec_DT( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0)
static char *Spec_DT(char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0)
{
pBuf += sprintf( pBuf, "SPECDT");
return pBuf;
pBuf += sprintf(pBuf, "SPECDT");
return pBuf;
}
static char *Spec_DO( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0)
static char *Spec_DO(char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0)
{
pBuf += sprintf( pBuf, "SPECDO");
return pBuf;
pBuf += sprintf(pBuf, "SPECDO");
return pBuf;
}
#endif
#endif

1126
src/emu/cpu/arm7/arm7core.c
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File diff suppressed because it is too large Load Diff

377
src/emu/cpu/arm7/arm7core.h
View File

@ -28,8 +28,6 @@
******************************************************************************/
#ifndef ARM7CORE_H
#define ARM7CORE_H
@ -44,14 +42,14 @@ enum
ARM7_ABORT_EXCEPTION, ARM7_ABORT_PREFETCH_EXCEPTION, ARM7_UNDEFINE_EXCEPTION,
ARM7_NUM_LINES
};
//Really there's only 1 ABORT Line.. and cpu decides whether it's during data fetch or prefetch, but we let the user specify
// Really there's only 1 ABORT Line.. and cpu decides whether it's during data fetch or prefetch, but we let the user specify
/****************************************************************************************************
* ARM7 CORE REGISTERS
***************************************************************************************************/
enum
{
ARM7_PC=0,
ARM7_PC = 0,
ARM7_R0, ARM7_R1, ARM7_R2, ARM7_R3, ARM7_R4, ARM7_R5, ARM7_R6, ARM7_R7,
ARM7_R8, ARM7_R9, ARM7_R10, ARM7_R11, ARM7_R12, ARM7_R13, ARM7_R14, ARM7_R15,
ARM7_FR8, ARM7_FR9, ARM7_FR10, ARM7_FR11, ARM7_FR12, ARM7_FR13, ARM7_FR14,
@ -59,14 +57,14 @@ enum
ARM7_CPSR, ARM7_AR13, ARM7_AR14, ARM7_ASPSR, ARM7_UR13, ARM7_UR14, ARM7_USPSR
};
#define ARM7CORE_REGS \
#define ARM7CORE_REGS \
UINT32 sArmRegister[kNumRegisters]; \
UINT8 pendingIrq; \
UINT8 pendingFiq; \
UINT8 pendingAbtD; \
UINT8 pendingAbtP; \
UINT8 pendingUnd; \
UINT8 pendingSwi; \
UINT8 pendingIrq; \
UINT8 pendingFiq; \
UINT8 pendingAbtD; \
UINT8 pendingAbtP; \
UINT8 pendingUnd; \
UINT8 pendingSwi; \
int (*irq_callback)(int);
@ -93,27 +91,27 @@ enum
enum
{
/* All modes have the following */
eR0=0,eR1,eR2,eR3,eR4,eR5,eR6,eR7,
eR8,eR9,eR10,eR11,eR12,
eR0 = 0, eR1, eR2, eR3, eR4, eR5, eR6, eR7,
eR8, eR9, eR10, eR11, eR12,
eR13, /* Stack Pointer */
eR14, /* Link Register (holds return address) */
eR15, /* Program Counter */
eCPSR, /* Current Status Program Register */
/* Fast Interrupt - Bank switched registers */
eR8_FIQ,eR9_FIQ,eR10_FIQ,eR11_FIQ,eR12_FIQ,eR13_FIQ,eR14_FIQ,eSPSR_FIQ,
eR8_FIQ, eR9_FIQ, eR10_FIQ, eR11_FIQ, eR12_FIQ, eR13_FIQ, eR14_FIQ, eSPSR_FIQ,
/* IRQ - Bank switched registers*/
eR13_IRQ,eR14_IRQ,eSPSR_IRQ,
/* IRQ - Bank switched registers */
eR13_IRQ, eR14_IRQ, eSPSR_IRQ,
/* Supervisor/Service Mode - Bank switched registers*/
eR13_SVC,eR14_SVC,eSPSR_SVC,
/* Supervisor/Service Mode - Bank switched registers */
eR13_SVC, eR14_SVC, eSPSR_SVC,
/* Abort Mode - Bank switched registers*/
eR13_ABT,eR14_ABT,eSPSR_ABT,
/* Abort Mode - Bank switched registers */
eR13_ABT, eR14_ABT, eSPSR_ABT,
/* Undefined Mode - Bank switched registers*/
eR13_UND,eR14_UND,eSPSR_UND,
/* Undefined Mode - Bank switched registers */
eR13_UND, eR14_UND, eSPSR_UND,
kNumRegisters
};
@ -145,49 +143,49 @@ static const int thumbCycles[256] =
static const int sRegisterTable[ARM7_NUM_MODES][18] =
{
{ /* USR */
eR0,eR1,eR2,eR3,eR4,eR5,eR6,eR7,
eR8,eR9,eR10,eR11,eR12,
eR13,eR14,
eR15,eCPSR //No SPSR in this mode
eR0, eR1, eR2, eR3, eR4, eR5, eR6, eR7,
eR8, eR9, eR10, eR11, eR12,
eR13, eR14,
eR15, eCPSR // No SPSR in this mode
},
{ /* FIQ */
eR0,eR1,eR2,eR3,eR4,eR5,eR6,eR7,
eR8_FIQ,eR9_FIQ,eR10_FIQ,eR11_FIQ,eR12_FIQ,
eR13_FIQ,eR14_FIQ,
eR15,eCPSR,eSPSR_FIQ
eR0, eR1, eR2, eR3, eR4, eR5, eR6, eR7,
eR8_FIQ, eR9_FIQ, eR10_FIQ, eR11_FIQ, eR12_FIQ,
eR13_FIQ, eR14_FIQ,
eR15, eCPSR, eSPSR_FIQ
},
{ /* IRQ */
eR0,eR1,eR2,eR3,eR4,eR5,eR6,eR7,
eR8,eR9,eR10,eR11,eR12,
eR13_IRQ,eR14_IRQ,
eR15,eCPSR,eSPSR_IRQ
eR0, eR1, eR2, eR3, eR4, eR5, eR6, eR7,
eR8, eR9, eR10, eR11, eR12,
eR13_IRQ, eR14_IRQ,
eR15, eCPSR, eSPSR_IRQ
},
{ /* SVC */
eR0,eR1,eR2,eR3,eR4,eR5,eR6,eR7,
eR8,eR9,eR10,eR11,eR12,
eR13_SVC,eR14_SVC,
eR15,eCPSR,eSPSR_SVC
eR0, eR1, eR2, eR3, eR4, eR5, eR6, eR7,
eR8, eR9, eR10, eR11, eR12,
eR13_SVC, eR14_SVC,
eR15, eCPSR, eSPSR_SVC
},
{0},{0},{0}, //values for modes 4,5,6 are not valid
{0}, {0}, {0}, // values for modes 4,5,6 are not valid
{ /* ABT */
eR0,eR1,eR2,eR3,eR4,eR5,eR6,eR7,
eR8,eR9,eR10,eR11,eR12,
eR13_ABT,eR14_ABT,
eR15,eCPSR,eSPSR_ABT
eR0, eR1, eR2, eR3, eR4, eR5, eR6, eR7,
eR8, eR9, eR10, eR11, eR12,
eR13_ABT, eR14_ABT,
eR15, eCPSR, eSPSR_ABT
},
{0},{0},{0}, //values for modes 8,9,a are not valid!
{0}, {0}, {0}, // values for modes 8,9,a are not valid!
{ /* UND */
eR0,eR1,eR2,eR3,eR4,eR5,eR6,eR7,
eR8,eR9,eR10,eR11,eR12,
eR13_UND,eR14_UND,
eR15,eCPSR,eSPSR_UND
eR0, eR1, eR2, eR3, eR4, eR5, eR6, eR7,
eR8, eR9, eR10, eR11, eR12,
eR13_UND, eR14_UND,
eR15, eCPSR, eSPSR_UND
},
{0},{0},{0}, //values for modes c,d,e are not valid!
{0}, {0}, {0}, // values for modes c,d, e are not valid!
{ /* SYS */
eR0,eR1,eR2,eR3,eR4,eR5,eR6,eR7,
eR8,eR9,eR10,eR11,eR12,
eR13,eR14,
eR15,eCPSR //No SPSR in this mode
eR0, eR1, eR2, eR3, eR4, eR5, eR6, eR7,
eR8, eR9, eR10, eR11, eR12,
eR13, eR14,
eR15, eCPSR // No SPSR in this mode
}
};
@ -197,15 +195,15 @@ static const int sRegisterTable[ARM7_NUM_MODES][18] =
#define V_BIT 28
#define I_BIT 7
#define F_BIT 6
#define T_BIT 5 //Thumb mode
#define T_BIT 5 // Thumb mode
#define N_MASK ((UINT32)(1<<N_BIT)) /* Negative flag */
#define Z_MASK ((UINT32)(1<<Z_BIT)) /* Zero flag */
#define C_MASK ((UINT32)(1<<C_BIT)) /* Carry flag */
#define V_MASK ((UINT32)(1<<V_BIT)) /* oVerflow flag */
#define I_MASK ((UINT32)(1<<I_BIT)) /* Interrupt request disable */
#define F_MASK ((UINT32)(1<<F_BIT)) /* Fast interrupt request disable */
#define T_MASK ((UINT32)(1<<T_BIT)) /* Thumb Mode flag */
#define N_MASK ((UINT32)(1 << N_BIT)) /* Negative flag */
#define Z_MASK ((UINT32)(1 << Z_BIT)) /* Zero flag */
#define C_MASK ((UINT32)(1 << C_BIT)) /* Carry flag */
#define V_MASK ((UINT32)(1 << V_BIT)) /* oVerflow flag */
#define I_MASK ((UINT32)(1 << I_BIT)) /* Interrupt request disable */
#define F_MASK ((UINT32)(1 << F_BIT)) /* Fast interrupt request disable */
#define T_MASK ((UINT32)(1 << T_BIT)) /* Thumb Mode flag */
#define N_IS_SET(pc) ((pc) & N_MASK)
#define Z_IS_SET(pc) ((pc) & Z_MASK)
@ -224,39 +222,39 @@ static const int sRegisterTable[ARM7_NUM_MODES][18] =
#define T_IS_CLEAR(pc) (!T_IS_SET(pc))
/* Deconstructing an instruction */
//todo: use these in all places (including dasm file)
#define INSN_COND ((UINT32) 0xf0000000u)
#define INSN_SDT_L ((UINT32) 0x00100000u)
#define INSN_SDT_W ((UINT32) 0x00200000u)
#define INSN_SDT_B ((UINT32) 0x00400000u)
#define INSN_SDT_U ((UINT32) 0x00800000u)
#define INSN_SDT_P ((UINT32) 0x01000000u)
#define INSN_BDT_L ((UINT32) 0x00100000u)
#define INSN_BDT_W ((UINT32) 0x00200000u)
#define INSN_BDT_S ((UINT32) 0x00400000u)
#define INSN_BDT_U ((UINT32) 0x00800000u)
#define INSN_BDT_P ((UINT32) 0x01000000u)
#define INSN_BDT_REGS ((UINT32) 0x0000ffffu)
#define INSN_SDT_IMM ((UINT32) 0x00000fffu)
#define INSN_MUL_A ((UINT32) 0x00200000u)
#define INSN_MUL_RM ((UINT32) 0x0000000fu)
#define INSN_MUL_RS ((UINT32) 0x00000f00u)
#define INSN_MUL_RN ((UINT32) 0x0000f000u)
#define INSN_MUL_RD ((UINT32) 0x000f0000u)
#define INSN_I ((UINT32) 0x02000000u)
#define INSN_OPCODE ((UINT32) 0x01e00000u)
#define INSN_S ((UINT32) 0x00100000u)
#define INSN_BL ((UINT32) 0x01000000u)
#define INSN_BRANCH ((UINT32) 0x00ffffffu)
#define INSN_SWI ((UINT32) 0x00ffffffu)
#define INSN_RN ((UINT32) 0x000f0000u)
#define INSN_RD ((UINT32) 0x0000f000u)
#define INSN_OP2 ((UINT32) 0x00000fffu)
#define INSN_OP2_SHIFT ((UINT32) 0x00000f80u)
#define INSN_OP2_SHIFT_TYPE ((UINT32) 0x00000070u)
#define INSN_OP2_RM ((UINT32) 0x0000000fu)
#define INSN_OP2_ROTATE ((UINT32) 0x00000f00u)
#define INSN_OP2_IMM ((UINT32) 0x000000ffu)
// todo: use these in all places (including dasm file)
#define INSN_COND ((UINT32)0xf0000000u)
#define INSN_SDT_L ((UINT32)0x00100000u)
#define INSN_SDT_W ((UINT32)0x00200000u)
#define INSN_SDT_B ((UINT32)0x00400000u)
#define INSN_SDT_U ((UINT32)0x00800000u)
#define INSN_SDT_P ((UINT32)0x01000000u)
#define INSN_BDT_L ((UINT32)0x00100000u)
#define INSN_BDT_W ((UINT32)0x00200000u)
#define INSN_BDT_S ((UINT32)0x00400000u)
#define INSN_BDT_U ((UINT32)0x00800000u)
#define INSN_BDT_P ((UINT32)0x01000000u)
#define INSN_BDT_REGS ((UINT32)0x0000ffffu)
#define INSN_SDT_IMM ((UINT32)0x00000fffu)
#define INSN_MUL_A ((UINT32)0x00200000u)
#define INSN_MUL_RM ((UINT32)0x0000000fu)
#define INSN_MUL_RS ((UINT32)0x00000f00u)
#define INSN_MUL_RN ((UINT32)0x0000f000u)
#define INSN_MUL_RD ((UINT32)0x000f0000u)
#define INSN_I ((UINT32)0x02000000u)
#define INSN_OPCODE ((UINT32)0x01e00000u)
#define INSN_S ((UINT32)0x00100000u)
#define INSN_BL ((UINT32)0x01000000u)
#define INSN_BRANCH ((UINT32)0x00ffffffu)
#define INSN_SWI ((UINT32)0x00ffffffu)
#define INSN_RN ((UINT32)0x000f0000u)
#define INSN_RD ((UINT32)0x0000f000u)
#define INSN_OP2 ((UINT32)0x00000fffu)
#define INSN_OP2_SHIFT ((UINT32)0x00000f80u)
#define INSN_OP2_SHIFT_TYPE ((UINT32)0x00000070u)
#define INSN_OP2_RM ((UINT32)0x0000000fu)
#define INSN_OP2_ROTATE ((UINT32)0x00000f00u)
#define INSN_OP2_IMM ((UINT32)0x000000ffu)
#define INSN_OP2_SHIFT_TYPE_SHIFT 4
#define INSN_OP2_SHIFT_SHIFT 7
#define INSN_OP2_ROTATE_SHIFT 8
@ -268,67 +266,67 @@ static const int sRegisterTable[ARM7_NUM_MODES][18] =
#define INSN_RD_SHIFT 12
#define INSN_COND_SHIFT 28
#define THUMB_INSN_TYPE ((UINT16) 0xf000)
#define THUMB_COND_TYPE ((UINT16) 0x0f00)
#define THUMB_GROUP4_TYPE ((UINT16) 0x0c00)
#define THUMB_GROUP5_TYPE ((UINT16) 0x0e00)
#define THUMB_GROUP5_RM ((UINT16) 0x01c0)
#define THUMB_GROUP5_RN ((UINT16) 0x0038)
#define THUMB_GROUP5_RD ((UINT16) 0x0007)
#define THUMB_ADDSUB_RNIMM ((UINT16) 0x01c0)
#define THUMB_ADDSUB_RS ((UINT16) 0x0038)
#define THUMB_ADDSUB_RD ((UINT16) 0x0007)
#define THUMB_INSN_ADDSUB ((UINT16) 0x0800)
#define THUMB_INSN_CMP ((UINT16) 0x0800)
#define THUMB_INSN_SUB ((UINT16) 0x0800)
#define THUMB_INSN_IMM_RD ((UINT16) 0x0700)
#define THUMB_INSN_IMM_S ((UINT16) 0x0080)
#define THUMB_INSN_IMM ((UINT16) 0x00ff)
#define THUMB_ADDSUB_TYPE ((UINT16) 0x0600)
#define THUMB_HIREG_OP ((UINT16) 0x0300)
#define THUMB_HIREG_H ((UINT16) 0x00c0)
#define THUMB_HIREG_RS ((UINT16) 0x0038)
#define THUMB_HIREG_RD ((UINT16) 0x0007)
#define THUMB_STACKOP_TYPE ((UINT16) 0x0f00)
#define THUMB_STACKOP_L ((UINT16) 0x0800)
#define THUMB_STACKOP_RD ((UINT16) 0x0700)
#define THUMB_ALUOP_TYPE ((UINT16) 0x03c0)
#define THUMB_BLOP_LO ((UINT16) 0x0800)
#define THUMB_BLOP_OFFS ((UINT16) 0x07ff)
#define THUMB_SHIFT_R ((UINT16) 0x0800)
#define THUMB_SHIFT_AMT ((UINT16) 0x07c0)
#define THUMB_HALFOP_L ((UINT16) 0x0800)
#define THUMB_HALFOP_OFFS ((UINT16) 0x07c0)
#define THUMB_BRANCH_OFFS ((UINT16) 0x07ff)
#define THUMB_LSOP_L ((UINT16) 0x0800)
#define THUMB_LSOP_OFFS ((UINT16) 0x07c0)
#define THUMB_MULTLS ((UINT16) 0x0800)
#define THUMB_MULTLS_BASE ((UINT16) 0x0700)
#define THUMB_RELADDR_SP ((UINT16) 0x0800)
#define THUMB_RELADDR_RD ((UINT16) 0x0700)
#define THUMB_INSN_TYPE_SHIFT 12
#define THUMB_COND_TYPE_SHIFT 8
#define THUMB_GROUP4_TYPE_SHIFT 10
#define THUMB_GROUP5_TYPE_SHIFT 9
#define THUMB_ADDSUB_TYPE_SHIFT 9
#define THUMB_INSN_IMM_RD_SHIFT 8
#define THUMB_STACKOP_TYPE_SHIFT 8
#define THUMB_HIREG_OP_SHIFT 8
#define THUMB_STACKOP_RD_SHIFT 8
#define THUMB_MULTLS_BASE_SHIFT 8
#define THUMB_RELADDR_RD_SHIFT 8
#define THUMB_HIREG_H_SHIFT 6
#define THUMB_HIREG_RS_SHIFT 3
#define THUMB_ALUOP_TYPE_SHIFT 6
#define THUMB_SHIFT_AMT_SHIFT 6
#define THUMB_HALFOP_OFFS_SHIFT 6
#define THUMB_LSOP_OFFS_SHIFT 6
#define THUMB_GROUP5_RM_SHIFT 6
#define THUMB_GROUP5_RN_SHIFT 3
#define THUMB_GROUP5_RD_SHIFT 0
#define THUMB_ADDSUB_RNIMM_SHIFT 6
#define THUMB_ADDSUB_RS_SHIFT 3
#define THUMB_ADDSUB_RD_SHIFT 0
#define THUMB_INSN_TYPE ((UINT16)0xf000)
#define THUMB_COND_TYPE ((UINT16)0x0f00)
#define THUMB_GROUP4_TYPE ((UINT16)0x0c00)
#define THUMB_GROUP5_TYPE ((UINT16)0x0e00)
#define THUMB_GROUP5_RM ((UINT16)0x01c0)
#define THUMB_GROUP5_RN ((UINT16)0x0038)
#define THUMB_GROUP5_RD ((UINT16)0x0007)
#define THUMB_ADDSUB_RNIMM ((UINT16)0x01c0)
#define THUMB_ADDSUB_RS ((UINT16)0x0038)
#define THUMB_ADDSUB_RD ((UINT16)0x0007)
#define THUMB_INSN_ADDSUB ((UINT16)0x0800)
#define THUMB_INSN_CMP ((UINT16)0x0800)
#define THUMB_INSN_SUB ((UINT16)0x0800)
#define THUMB_INSN_IMM_RD ((UINT16)0x0700)
#define THUMB_INSN_IMM_S ((UINT16)0x0080)
#define THUMB_INSN_IMM ((UINT16)0x00ff)
#define THUMB_ADDSUB_TYPE ((UINT16)0x0600)
#define THUMB_HIREG_OP ((UINT16)0x0300)
#define THUMB_HIREG_H ((UINT16)0x00c0)
#define THUMB_HIREG_RS ((UINT16)0x0038)
#define THUMB_HIREG_RD ((UINT16)0x0007)
#define THUMB_STACKOP_TYPE ((UINT16)0x0f00)
#define THUMB_STACKOP_L ((UINT16)0x0800)
#define THUMB_STACKOP_RD ((UINT16)0x0700)
#define THUMB_ALUOP_TYPE ((UINT16)0x03c0)
#define THUMB_BLOP_LO ((UINT16)0x0800)
#define THUMB_BLOP_OFFS ((UINT16)0x07ff)
#define THUMB_SHIFT_R ((UINT16)0x0800)
#define THUMB_SHIFT_AMT ((UINT16)0x07c0)
#define THUMB_HALFOP_L ((UINT16)0x0800)
#define THUMB_HALFOP_OFFS ((UINT16)0x07c0)
#define THUMB_BRANCH_OFFS ((UINT16)0x07ff)
#define THUMB_LSOP_L ((UINT16)0x0800)
#define THUMB_LSOP_OFFS ((UINT16)0x07c0)
#define THUMB_MULTLS ((UINT16)0x0800)
#define THUMB_MULTLS_BASE ((UINT16)0x0700)
#define THUMB_RELADDR_SP ((UINT16)0x0800)
#define THUMB_RELADDR_RD ((UINT16)0x0700)
#define THUMB_INSN_TYPE_SHIFT 12
#define THUMB_COND_TYPE_SHIFT 8
#define THUMB_GROUP4_TYPE_SHIFT 10
#define THUMB_GROUP5_TYPE_SHIFT 9
#define THUMB_ADDSUB_TYPE_SHIFT 9
#define THUMB_INSN_IMM_RD_SHIFT 8
#define THUMB_STACKOP_TYPE_SHIFT 8
#define THUMB_HIREG_OP_SHIFT 8
#define THUMB_STACKOP_RD_SHIFT 8
#define THUMB_MULTLS_BASE_SHIFT 8
#define THUMB_RELADDR_RD_SHIFT 8
#define THUMB_HIREG_H_SHIFT 6
#define THUMB_HIREG_RS_SHIFT 3
#define THUMB_ALUOP_TYPE_SHIFT 6
#define THUMB_SHIFT_AMT_SHIFT 6
#define THUMB_HALFOP_OFFS_SHIFT 6
#define THUMB_LSOP_OFFS_SHIFT 6
#define THUMB_GROUP5_RM_SHIFT 6
#define THUMB_GROUP5_RN_SHIFT 3
#define THUMB_GROUP5_RD_SHIFT 0
#define THUMB_ADDSUB_RNIMM_SHIFT 6
#define THUMB_ADDSUB_RS_SHIFT 3
#define THUMB_ADDSUB_RD_SHIFT 0
enum
{
@ -352,61 +350,60 @@ enum
enum
{
COND_EQ = 0, /* Z: equal */
COND_NE, /* ~Z: not equal */
COND_CS, COND_HS = 2, /* C: unsigned higher or same */
COND_CC, COND_LO = 3, /* ~C: unsigned lower */
COND_MI, /* N: negative */
COND_PL, /* ~N: positive or zero */
COND_VS, /* V: overflow */
COND_VC, /* ~V: no overflow */
COND_HI, /* C && ~Z: unsigned higher */
COND_LS, /* ~C || Z: unsigned lower or same */
COND_GE, /* N == V: greater or equal */
COND_LT, /* N != V: less than */
COND_GT, /* ~Z && (N == V): greater than */
COND_LE, /* Z || (N != V): less than or equal */
COND_AL, /* always */
COND_NV /* never */
COND_EQ = 0, /* Z equal */
COND_NE, /* ~Z not equal */
COND_CS, COND_HS = 2, /* C unsigned higher or same */
COND_CC, COND_LO = 3, /* ~C unsigned lower */
COND_MI, /* N negative */
COND_PL, /* ~N positive or zero */
COND_VS, /* V overflow */
COND_VC, /* ~V no overflow */
COND_HI, /* C && ~Z unsigned higher */
COND_LS, /* ~C || Z unsigned lower or same */
COND_GE, /* N == V greater or equal */
COND_LT, /* N != V less than */
COND_GT, /* ~Z && N == V greater than */
COND_LE, /* Z || N != V less than or equal */
COND_AL, /* 1 always */
COND_NV /* 0 never */
};
#define LSL(v,s) ((v) << (s))
#define LSR(v,s) ((v) >> (s))
#define ROL(v,s) (LSL((v),(s)) | (LSR((v),32u - (s))))
#define ROR(v,s) (LSR((v),(s)) | (LSL((v),32u - (s))))
#define LSL(v, s) ((v) << (s))
#define LSR(v, s) ((v) >> (s))
#define ROL(v, s) (LSL((v), (s)) | (LSR((v), 32u - (s))))
#define ROR(v, s) (LSR((v), (s)) | (LSL((v), 32u - (s))))
/* Convenience Macros */
#define R15 ARM7REG(eR15)
#define SPSR 17 //SPSR is always the 18th register in our 0 based array sRegisterTable[][18]
#define SPSR 17 // SPSR is always the 18th register in our 0 based array sRegisterTable[][18]
#define GET_CPSR ARM7REG(eCPSR)
#define SET_CPSR(v) (GET_CPSR = (v))
#define MODE_FLAG 0xF //Mode bits are 4:0 of CPSR, but we ignore bit 4.
#define MODE_FLAG 0xF // Mode bits are 4:0 of CPSR, but we ignore bit 4.
#define GET_MODE (GET_CPSR & MODE_FLAG)
#define SIGN_BIT ((UINT32)(1<<31))
#define SIGN_BITS_DIFFER(a,b) (((a)^(b)) >> 31)
#define SIGN_BIT ((UINT32)(1 << 31))
#define SIGN_BITS_DIFFER(a, b) (((a) ^ (b)) >> 31)
/* I really don't know why these were set to 16-bit, the thumb registers are still 32-bit ... */
#define THUMB_SIGN_BIT ((UINT32)(1<<31))
#define THUMB_SIGN_BITS_DIFFER(a,b) (((a)^(b)) >> 31)
#define THUMB_SIGN_BIT ((UINT32)(1 << 31))
#define THUMB_SIGN_BITS_DIFFER(a, b) (((a)^(b)) >> 31)
/* At one point I thought these needed to be cpu implementation specific, but they don't.. */
#define GET_REGISTER(reg) GetRegister(reg)
#define SET_REGISTER(reg,val) SetRegister(reg,val)
#define SET_REGISTER(reg, val) SetRegister(reg, val)
#define ARM7_CHECKIRQ arm7_check_irq_state()
extern WRITE32_HANDLER((*arm7_coproc_do_callback));
extern READ32_HANDLER((*arm7_coproc_rt_r_callback));
extern WRITE32_HANDLER((*arm7_coproc_rt_w_callback));
extern void (*arm7_coproc_dt_r_callback)(UINT32 insn, UINT32* prn, UINT32 (*read32)(int addr));
extern void (*arm7_coproc_dt_w_callback)(UINT32 insn, UINT32* prn, void (*write32)(int addr, UINT32 data));
extern void (*arm7_coproc_dt_r_callback)(UINT32 insn, UINT32* prn, UINT32 (*read32)(UINT32 addr));
extern void (*arm7_coproc_dt_w_callback)(UINT32 insn, UINT32* prn, void (*write32)(UINT32 addr, UINT32 data));
#ifdef ENABLE_DEBUGGER
extern UINT32 arm7_disasm( char *pBuf, UINT32 pc, UINT32 opcode );
extern UINT32 thumb_disasm( char *pBuf, UINT32 pc, UINT16 opcode );
extern UINT32 arm7_disasm(char *pBuf, UINT32 pc, UINT32 opcode);
extern UINT32 thumb_disasm(char *pBuf, UINT32 pc, UINT16 opcode);
extern char *(*arm7_dasm_cop_dt_callback)( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0 );
extern char *(*arm7_dasm_cop_rt_callback)( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0 );
extern char *(*arm7_dasm_cop_do_callback)( char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0 );
extern char *(*arm7_dasm_cop_dt_callback)(char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
extern char *(*arm7_dasm_cop_rt_callback)(char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
extern char *(*arm7_dasm_cop_do_callback)(char *pBuf, UINT32 opcode, char *pConditionCode, char *pBuf0);
#endif
#endif /* ARM7CORE_H */