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ncr5380n, ncr5385, ncr5390, ncr539x: Simplify read/write handlers (nw)

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This commit is contained in:
AJR 2019-03-07 08:41:05 -05:00
parent 8e3543b398
commit 4849160644
12 changed files with 184 additions and 184 deletions
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4
src/devices/bus/a2bus/a2hsscsi.cpp
View File

@ -163,7 +163,7 @@ uint8_t a2bus_hsscsi_device::read_c0nx(uint8_t offset)
case 6:
case 7:
// logerror("Read 5380 @ %x\n", offset);
return m_ncr5380->read(machine().dummy_space(), offset);
return m_ncr5380->read(offset);
case 0xc:
return 0x00; // indicate watchdog?
@ -200,7 +200,7 @@ void a2bus_hsscsi_device::write_c0nx(uint8_t offset, uint8_t data)
case 6:
case 7:
// logerror("%02x to 5380 reg %x\n", data, offset);
m_ncr5380->write(machine().dummy_space(), offset, data);
m_ncr5380->write(offset, data);
break;
#if 0
case 8: // DMA address low

4
src/devices/bus/a2bus/a2scsi.cpp
View File

@ -154,7 +154,7 @@ uint8_t a2bus_scsi_device::read_c0nx(uint8_t offset)
case 6:
case 7:
// logerror("Read 5380 @ %x\n", offset);
return m_ncr5380->read(machine().dummy_space(), offset);
return m_ncr5380->read(offset);
case 8: // read and DACK
return m_ncr5380->dma_r();
@ -194,7 +194,7 @@ void a2bus_scsi_device::write_c0nx(uint8_t offset, uint8_t data)
case 6:
case 7:
// logerror("%02x to 5380 reg %x\n", data, offset);
m_ncr5380->write(machine().dummy_space(), offset, data);
m_ncr5380->write(offset, data);
break;
case 8: // write and DACK

116
src/devices/machine/ncr5380n.cpp
View File

@ -288,12 +288,12 @@ void ncr5380n_device::delay_cycles(int cycles)
tm->adjust(clocks_to_attotime(cycles));
}
READ8_MEMBER(ncr5380n_device::scsidata_r)
uint8_t ncr5380n_device::scsidata_r()
{
return scsi_bus->data_r();
}
WRITE8_MEMBER(ncr5380n_device::outdata_w)
void ncr5380n_device::outdata_w(uint8_t data)
{
m_outdata = data;
@ -304,12 +304,12 @@ WRITE8_MEMBER(ncr5380n_device::outdata_w)
}
}
READ8_MEMBER(ncr5380n_device::icmd_r)
uint8_t ncr5380n_device::icmd_r()
{
return m_icommand;
}
WRITE8_MEMBER(ncr5380n_device::icmd_w)
void ncr5380n_device::icmd_w(uint8_t data)
{
// asserting to drive the data bus?
if ((data & IC_DBUS) && !(m_icommand & IC_DBUS))
@ -340,12 +340,12 @@ WRITE8_MEMBER(ncr5380n_device::icmd_w)
delay(2);
}
READ8_MEMBER(ncr5380n_device::mode_r)
uint8_t ncr5380n_device::mode_r()
{
return m_mode;
}
WRITE8_MEMBER(ncr5380n_device::mode_w)
void ncr5380n_device::mode_w(uint8_t data)
{
// logerror("%s: mode_w %02x (%s)\n", tag(), data, machine().describe_context());
// arbitration bit being set?
@ -373,13 +373,13 @@ WRITE8_MEMBER(ncr5380n_device::mode_w)
m_mode = data;
}
READ8_MEMBER(ncr5380n_device::command_r)
uint8_t ncr5380n_device::command_r()
{
// logerror("%s: command_r %02x (%s)\n", tag(), m_tcommand, machine().describe_context());
return m_tcommand;
}
WRITE8_MEMBER(ncr5380n_device::command_w)
void ncr5380n_device::command_w(uint8_t data)
{
// logerror("%s: command_w %02x (%s)\n", tag(), data, machine().describe_context());
m_tcommand = data;
@ -413,7 +413,7 @@ void ncr5380n_device::check_irq()
#endif
}
READ8_MEMBER(ncr5380n_device::status_r)
uint8_t ncr5380n_device::status_r()
{
uint32_t ctrl = scsi_bus->ctrl_r();
uint8_t res = status |
@ -429,11 +429,11 @@ READ8_MEMBER(ncr5380n_device::status_r)
return res;
}
WRITE8_MEMBER(ncr5380n_device::selenable_w)
void ncr5380n_device::selenable_w(uint8_t data)
{
}
READ8_MEMBER(ncr5380n_device::busandstatus_r)
uint8_t ncr5380n_device::busandstatus_r()
{
uint32_t ctrl = scsi_bus->ctrl_r();
uint8_t res = m_busstatus |
@ -445,28 +445,28 @@ READ8_MEMBER(ncr5380n_device::busandstatus_r)
return res;
}
WRITE8_MEMBER(ncr5380n_device::startdmasend_w)
void ncr5380n_device::startdmasend_w(uint8_t data)
{
logerror("%02x to start dma send\n", data);
drq_set();
}
READ8_MEMBER(ncr5380n_device::indata_r)
uint8_t ncr5380n_device::indata_r()
{
return dma_r();
}
WRITE8_MEMBER(ncr5380n_device::startdmatargetrx_w)
void ncr5380n_device::startdmatargetrx_w(uint8_t data)
{
logerror("%02x to start dma target Rx\n", data);
}
READ8_MEMBER(ncr5380n_device::resetparityirq_r)
uint8_t ncr5380n_device::resetparityirq_r()
{
return 0;
}
WRITE8_MEMBER(ncr5380n_device::startdmainitrx_w)
void ncr5380n_device::startdmainitrx_w(uint8_t data)
{
// logerror("%02x to start dma initiator Rx\n", data);
recv_byte();
@ -518,73 +518,73 @@ void ncr5380n_device::drq_clear()
}
}
READ8_MEMBER(ncr5380n_device::read)
uint8_t ncr5380n_device::read(offs_t offset)
{
switch (offset & 7)
{
case 0:
return scsidata_r(space, offset);
case 0:
return scsidata_r();
case 1:
return icmd_r(space, offset);
case 1:
return icmd_r();
case 2:
return mode_r(space, offset);
case 2:
return mode_r();
case 3:
return command_r(space, offset);
case 3:
return command_r();
case 4:
return status_r(space, offset);
case 4:
return status_r();
case 5:
return busandstatus_r(space, offset);
case 5:
return busandstatus_r();
case 6:
return indata_r(space, offset);
case 6:
return indata_r();
case 7:
return resetparityirq_r(space, offset);
case 7:
return resetparityirq_r();
}
return 0xff;
}
WRITE8_MEMBER(ncr5380n_device::write)
void ncr5380n_device::write(offs_t offset, uint8_t data)
{
// logerror("%x to 5380 @ %x\n", data, offset);
switch (offset & 7)
{
case 0:
outdata_w(space, offset, data);
break;
case 0:
outdata_w(data);
break;
case 1:
icmd_w(space, offset, data);
break;
case 1:
icmd_w(data);
break;
case 2:
mode_w(space, offset, data);
break;
case 2:
mode_w(data);
break;
case 3:
command_w(space, offset, data);
break;
case 3:
command_w(data);
break;
case 4:
selenable_w(space, offset, data);
break;
case 4:
selenable_w(data);
break;
case 5:
startdmasend_w(space, offset, data);
break;
case 5:
startdmasend_w(data);
break;
case 6:
startdmatargetrx_w(space, offset, data);
break;
case 6:
startdmatargetrx_w(data);
break;
case 7:
startdmainitrx_w(space, offset, data);
break;
case 7:
startdmainitrx_w(data);
break;
}
}

36
src/devices/machine/ncr5380n.h
View File

@ -25,8 +25,8 @@ public:
auto irq_handler() { return m_irq_handler.bind(); }
auto drq_handler() { return m_drq_handler.bind(); }
DECLARE_READ8_MEMBER(read);
DECLARE_WRITE8_MEMBER(write);
uint8_t read(offs_t offset);
void write(offs_t offset, uint8_t data);
uint8_t dma_r();
void dma_w(uint8_t val);
@ -198,22 +198,22 @@ private:
void map(address_map &map);
DECLARE_READ8_MEMBER(scsidata_r);
DECLARE_WRITE8_MEMBER(outdata_w);
DECLARE_READ8_MEMBER(icmd_r);
DECLARE_WRITE8_MEMBER(icmd_w);
DECLARE_READ8_MEMBER(mode_r);
DECLARE_WRITE8_MEMBER(mode_w);
DECLARE_READ8_MEMBER(command_r);
DECLARE_WRITE8_MEMBER(command_w);
DECLARE_READ8_MEMBER(status_r);
DECLARE_WRITE8_MEMBER(selenable_w);
DECLARE_READ8_MEMBER(busandstatus_r);
DECLARE_WRITE8_MEMBER(startdmasend_w);
DECLARE_READ8_MEMBER(indata_r);
DECLARE_WRITE8_MEMBER(startdmatargetrx_w);
DECLARE_READ8_MEMBER(resetparityirq_r);
DECLARE_WRITE8_MEMBER(startdmainitrx_w);
uint8_t scsidata_r();
void outdata_w(uint8_t data);
uint8_t icmd_r();
void icmd_w(uint8_t data);
uint8_t mode_r();
void mode_w(uint8_t data);
uint8_t command_r();
void command_w(uint8_t data);
uint8_t status_r();
void selenable_w(uint8_t data);
uint8_t busandstatus_r();
void startdmasend_w(uint8_t data);
uint8_t indata_r();
void startdmatargetrx_w(uint8_t data);
uint8_t resetparityirq_r();
void startdmainitrx_w(uint8_t data);
devcb_write_line m_irq_handler;
devcb_write_line m_drq_handler;

4
src/devices/machine/ncr5385.cpp
View File

@ -34,7 +34,7 @@ void ncr5385_device::device_reset()
m_diag_status_reg = DIAG_COMPLETE;
}
WRITE8_MEMBER(ncr5385_device::write)
void ncr5385_device::write(offs_t offset, uint8_t data)
{
switch (offset)
{
@ -96,7 +96,7 @@ WRITE8_MEMBER(ncr5385_device::write)
}
}
READ8_MEMBER(ncr5385_device::read)
uint8_t ncr5385_device::read(offs_t offset)
{
switch (offset)
{

4
src/devices/machine/ncr5385.h
View File

@ -58,8 +58,8 @@ public:
auto irq() { return m_int.bind(); }
DECLARE_WRITE8_MEMBER(write);
DECLARE_READ8_MEMBER(read);
void write(offs_t offset, uint8_t data);
uint8_t read(offs_t offset);
protected:
// device-level overrides

112
src/devices/machine/ncr5390.cpp
View File

@ -39,38 +39,38 @@ void ncr5390_device::map(address_map &map)
map(0x9, 0x9).w(FUNC(ncr5390_device::clock_w));
}
READ8_MEMBER(ncr5390_device::read)
uint8_t ncr5390_device::read(offs_t offset)
{
switch (offset)
{
case 0: return tcounter_lo_r(space, 0);
case 1: return tcounter_hi_r(space, 0);
case 2: return fifo_r(space, 0);
case 3: return command_r(space, 0);
case 4: return status_r(space, 0);
case 5: return istatus_r(space, 0);
case 6: return seq_step_r(space, 0);
case 7: return fifo_flags_r(space, 0);
case 8: return conf_r(space, 0);
case 0: return tcounter_lo_r();
case 1: return tcounter_hi_r();
case 2: return fifo_r();
case 3: return command_r();
case 4: return status_r();
case 5: return istatus_r();
case 6: return seq_step_r();
case 7: return fifo_flags_r();
case 8: return conf_r();
default: return 0xff;
}
}
WRITE8_MEMBER(ncr5390_device::write)
void ncr5390_device::write(offs_t offset, uint8_t data)
{
switch (offset)
{
case 0: tcount_lo_w(space, 0, data); break;
case 1: tcount_hi_w(space, 0, data); break;
case 2: fifo_w(space, 0, data); break;
case 3: command_w(space, 0, data); break;
case 4: bus_id_w(space, 0, data); break;
case 5: timeout_w(space, 0, data); break;
case 6: sync_period_w(space, 0, data); break;
case 7: sync_offset_w(space, 0, data); break;
case 8: conf_w(space, 0, data); break;
case 9: clock_w(space, 0, data); break;
case 10: test_w(space, 0, data); break;
case 0: tcount_lo_w(data); break;
case 1: tcount_hi_w(data); break;
case 2: fifo_w(data); break;
case 3: command_w(data); break;
case 4: bus_id_w(data); break;
case 5: timeout_w(data); break;
case 6: sync_period_w(data); break;
case 7: sync_offset_w(data); break;
case 8: conf_w(data); break;
case 9: clock_w(data); break;
case 10: test_w(data); break;
default: break;
}
}
@ -82,18 +82,18 @@ void ncr53c90a_device::map(address_map &map)
map(0xb, 0xb).rw(FUNC(ncr53c90a_device::conf2_r), FUNC(ncr53c90a_device::conf2_w));
}
READ8_MEMBER(ncr53c90a_device::read)
uint8_t ncr53c90a_device::read(offs_t offset)
{
if (offset == 11)
return conf2_r(space, 0);
return ncr5390_device::read(space, offset);
return conf2_r();
return ncr5390_device::read(offset);
}
WRITE8_MEMBER(ncr53c90a_device::write)
void ncr53c90a_device::write(offs_t offset, uint8_t data)
{
if (offset == 11)
return conf2_w(space, 0, data);
ncr5390_device::write(space, offset, data);
return conf2_w(data);
ncr5390_device::write(offset, data);
}
void ncr53c94_device::map(address_map &map)
@ -104,21 +104,21 @@ void ncr53c94_device::map(address_map &map)
map(0xf, 0xf).w(FUNC(ncr53c94_device::fifo_align_w));
}
READ8_MEMBER(ncr53c94_device::read)
uint8_t ncr53c94_device::read(offs_t offset)
{
if (offset == 12)
return conf3_r(space, 0);
return ncr53c90a_device::read(space, offset);
return conf3_r();
return ncr53c90a_device::read(offset);
}
WRITE8_MEMBER(ncr53c94_device::write)
void ncr53c94_device::write(offs_t offset, uint8_t data)
{
if (offset == 11)
conf3_w(space, 0, data);
conf3_w(data);
else if (offset == 15)
fifo_align_w(space, 0, data);
fifo_align_w(data);
else
ncr53c90a_device::write(space, offset, data);
ncr53c90a_device::write(offset, data);
}
ncr5390_device::ncr5390_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
@ -733,25 +733,25 @@ void ncr5390_device::delay_cycles(int cycles)
tm->adjust(clocks_to_attotime(cycles));
}
READ8_MEMBER(ncr5390_device::tcounter_lo_r)
uint8_t ncr5390_device::tcounter_lo_r()
{
LOG("tcounter_lo_r %02x (%s)\n", tcounter & 0xff, machine().describe_context());
return tcounter;
}
WRITE8_MEMBER(ncr5390_device::tcount_lo_w)
void ncr5390_device::tcount_lo_w(uint8_t data)
{
tcount = (tcount & 0xff00) | data;
LOG("tcount_lo_w %02x (%s)\n", data, machine().describe_context());
}
READ8_MEMBER(ncr5390_device::tcounter_hi_r)
uint8_t ncr5390_device::tcounter_hi_r()
{
LOG("tcounter_hi_r %02x (%s)\n", tcounter >> 8, machine().describe_context());
return tcounter >> 8;
}
WRITE8_MEMBER(ncr5390_device::tcount_hi_w)
void ncr5390_device::tcount_hi_w(uint8_t data)
{
tcount = (tcount & 0x00ff) | (data << 8);
LOG("tcount_hi_w %02x (%s)\n", data, machine().describe_context());
@ -772,7 +772,7 @@ void ncr5390_device::fifo_push(uint8_t val)
check_drq();
}
READ8_MEMBER(ncr5390_device::fifo_r)
uint8_t ncr5390_device::fifo_r()
{
uint8_t r;
if(fifo_pos) {
@ -785,20 +785,20 @@ READ8_MEMBER(ncr5390_device::fifo_r)
return r;
}
WRITE8_MEMBER(ncr5390_device::fifo_w)
void ncr5390_device::fifo_w(uint8_t data)
{
LOGMASKED(LOG_FIFO, "fifo_w 0x%02x fifo_pos %d (%s)\n", data, fifo_pos, machine().describe_context());
if(fifo_pos != 16)
fifo[fifo_pos++] = data;
}
READ8_MEMBER(ncr5390_device::command_r)
uint8_t ncr5390_device::command_r()
{
LOG("command_r (%s)\n", machine().describe_context());
return command[0];
}
WRITE8_MEMBER(ncr5390_device::command_w)
void ncr5390_device::command_w(uint8_t data)
{
LOG("command_w %02x command_pos %d (%s)\n", data, command_pos, machine().describe_context());
if(command_pos == 2) {
@ -990,7 +990,7 @@ void ncr5390_device::check_irq()
}
READ8_MEMBER(ncr5390_device::status_r)
uint8_t ncr5390_device::status_r()
{
uint32_t ctrl = scsi_bus->ctrl_r();
uint8_t res = status | (ctrl & S_MSG ? 4 : 0) | (ctrl & S_CTL ? 2 : 0) | (ctrl & S_INP ? 1 : 0);
@ -999,13 +999,13 @@ READ8_MEMBER(ncr5390_device::status_r)
return res;
}
WRITE8_MEMBER(ncr5390_device::bus_id_w)
void ncr5390_device::bus_id_w(uint8_t data)
{
bus_id = data & 7;
LOG("bus_id=%d\n", bus_id);
}
READ8_MEMBER(ncr5390_device::istatus_r)
uint8_t ncr5390_device::istatus_r()
{
uint8_t res = istatus;
@ -1023,39 +1023,39 @@ READ8_MEMBER(ncr5390_device::istatus_r)
return res;
}
WRITE8_MEMBER(ncr5390_device::timeout_w)
void ncr5390_device::timeout_w(uint8_t data)
{
LOG("timeout_w 0x%02x\n", data);
select_timeout = data;
}
READ8_MEMBER(ncr5390_device::seq_step_r)
uint8_t ncr5390_device::seq_step_r()
{
LOG("seq_step_r %d (%s)\n", seq, machine().describe_context());
return seq;
}
WRITE8_MEMBER(ncr5390_device::sync_period_w)
void ncr5390_device::sync_period_w(uint8_t data)
{
sync_period = data & 0x1f;
}
READ8_MEMBER(ncr5390_device::fifo_flags_r)
uint8_t ncr5390_device::fifo_flags_r()
{
return fifo_pos;
}
WRITE8_MEMBER(ncr5390_device::sync_offset_w)
void ncr5390_device::sync_offset_w(uint8_t data)
{
sync_offset = data & 0x0f;
}
READ8_MEMBER(ncr5390_device::conf_r)
uint8_t ncr5390_device::conf_r()
{
return config;
}
WRITE8_MEMBER(ncr5390_device::conf_w)
void ncr5390_device::conf_w(uint8_t data)
{
config = data;
scsi_id = data & 7;
@ -1065,13 +1065,13 @@ WRITE8_MEMBER(ncr5390_device::conf_w)
test_mode = true;
}
WRITE8_MEMBER(ncr5390_device::test_w)
void ncr5390_device::test_w(uint8_t data)
{
if (test_mode)
logerror("test_w %d (%s) - test mode not implemented\n", data, machine().describe_context());
}
WRITE8_MEMBER(ncr5390_device::clock_w)
void ncr5390_device::clock_w(uint8_t data)
{
clock_conv = data & 0x07;
}
@ -1171,7 +1171,7 @@ void ncr53c90a_device::device_reset()
ncr5390_device::device_reset();
}
READ8_MEMBER(ncr53c90a_device::status_r)
uint8_t ncr53c90a_device::status_r()
{
uint32_t ctrl = scsi_bus->ctrl_r();
uint8_t res = (irq ? S_INTERRUPT : 0) | status | (ctrl & S_MSG ? 4 : 0) | (ctrl & S_CTL ? 2 : 0) | (ctrl & S_INP ? 1 : 0);

64
src/devices/machine/ncr5390.h
View File

@ -18,29 +18,29 @@ public:
virtual void map(address_map &map);
DECLARE_READ8_MEMBER(tcounter_lo_r);
DECLARE_WRITE8_MEMBER(tcount_lo_w);
DECLARE_READ8_MEMBER(tcounter_hi_r);
DECLARE_WRITE8_MEMBER(tcount_hi_w);
DECLARE_READ8_MEMBER(fifo_r);
DECLARE_WRITE8_MEMBER(fifo_w);
DECLARE_READ8_MEMBER(command_r);
DECLARE_WRITE8_MEMBER(command_w);
virtual DECLARE_READ8_MEMBER(status_r);
DECLARE_WRITE8_MEMBER(bus_id_w);
DECLARE_READ8_MEMBER(istatus_r);
DECLARE_WRITE8_MEMBER(timeout_w);
DECLARE_READ8_MEMBER(seq_step_r);
DECLARE_WRITE8_MEMBER(sync_period_w);
DECLARE_READ8_MEMBER(fifo_flags_r);
DECLARE_WRITE8_MEMBER(sync_offset_w);
DECLARE_READ8_MEMBER(conf_r);
DECLARE_WRITE8_MEMBER(conf_w);
DECLARE_WRITE8_MEMBER(test_w);
DECLARE_WRITE8_MEMBER(clock_w);
uint8_t tcounter_lo_r();
void tcount_lo_w(uint8_t data);
uint8_t tcounter_hi_r();
void tcount_hi_w(uint8_t data);
uint8_t fifo_r();
void fifo_w(uint8_t data);
uint8_t command_r();
void command_w(uint8_t data);
virtual uint8_t status_r();
void bus_id_w(uint8_t data);
uint8_t istatus_r();
void timeout_w(uint8_t data);
uint8_t seq_step_r();
void sync_period_w(uint8_t data);
uint8_t fifo_flags_r();
void sync_offset_w(uint8_t data);
uint8_t conf_r();
void conf_w(uint8_t data);
void test_w(uint8_t data);
void clock_w(uint8_t data);
virtual DECLARE_READ8_MEMBER(read);
virtual DECLARE_WRITE8_MEMBER(write);
virtual uint8_t read(offs_t offset);
virtual void write(offs_t offset, uint8_t data);
virtual void scsi_ctrl_changed() override;
@ -243,13 +243,13 @@ public:
virtual void map(address_map &map) override;
virtual DECLARE_READ8_MEMBER(status_r) override;
virtual uint8_t status_r() override;
DECLARE_READ8_MEMBER(conf2_r) { return config2; };
DECLARE_WRITE8_MEMBER(conf2_w) { config2 = data; };
uint8_t conf2_r() { return config2; };
void conf2_w(uint8_t data) { config2 = data; };
virtual DECLARE_READ8_MEMBER(read) override;
virtual DECLARE_WRITE8_MEMBER(write) override;
virtual uint8_t read(offs_t offset) override;
virtual void write(offs_t offset, uint8_t data) override;
protected:
ncr53c90a_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
@ -296,12 +296,12 @@ public:
virtual void map(address_map &map) override;
DECLARE_READ8_MEMBER(conf3_r) { return config3; };
DECLARE_WRITE8_MEMBER(conf3_w) { config3 = data; };
DECLARE_WRITE8_MEMBER(fifo_align_w) { fifo_align = data; };
uint8_t conf3_r() { return config3; };
void conf3_w(uint8_t data) { config3 = data; };
void fifo_align_w(uint8_t data) { fifo_align = data; };
virtual DECLARE_READ8_MEMBER(read) override;
virtual DECLARE_WRITE8_MEMBER(write) override;
virtual uint8_t read(offs_t offset) override;
virtual void write(offs_t offset, uint8_t data) override;
u16 dma16_r();
void dma16_w(u16 data);

4
src/devices/machine/ncr539x.cpp
View File

@ -280,7 +280,7 @@ void ncr539x_device::device_timer(emu_timer &timer, device_timer_id tid, int par
}
}
READ8_MEMBER( ncr539x_device::read )
uint8_t ncr539x_device::read(offs_t offset)
{
uint8_t rv = 0;
@ -412,7 +412,7 @@ READ8_MEMBER( ncr539x_device::read )
return rv;
}
WRITE8_MEMBER( ncr539x_device::write )
void ncr539x_device::write(offs_t offset, uint8_t data)
{
//if (offset != 2)
LOG("539x: Write %02x @ %s (%02x) (%s)\n", data, wrregs[offset], offset, machine().describe_context());

4
src/devices/machine/ncr539x.h
View File

@ -25,8 +25,8 @@ public:
auto drq_callback() { return m_out_drq_cb.bind(); }
// our API
DECLARE_READ8_MEMBER(read);
DECLARE_WRITE8_MEMBER(write);
uint8_t read(offs_t offset);
void write(offs_t offset, uint8_t data);
void dma_read_data(int bytes, uint8_t *pData);
void dma_write_data(int bytes, uint8_t *pData);

8
src/mame/drivers/mac.cpp
View File

@ -546,11 +546,11 @@ READ8_MEMBER(mac_state::mac_5396_r)
{
if (offset < 0x100)
{
return m_539x_1->read(space, offset>>4);
return m_539x_1->read(offset>>4);
}
else // pseudo-DMA: read from the FIFO
{
return m_539x_1->read(space, 2);
return m_539x_1->read(2);
}
// never executed
@ -561,11 +561,11 @@ WRITE8_MEMBER(mac_state::mac_5396_w)
{
if (offset < 0x100)
{
m_539x_1->write(space, offset>>4, data);
m_539x_1->write(offset>>4, data);
}
else // pseudo-DMA: write to the FIFO
{
m_539x_1->write(space, 2, data);
m_539x_1->write(2, data);
}
}

8
src/mame/machine/macpci.cpp
View File

@ -186,11 +186,11 @@ READ8_MEMBER(macpci_state::mac_5396_r)
{
if (offset < 0x100)
{
return m_539x_1->read(space, offset>>4);
return m_539x_1->read(offset>>4);
}
else // pseudo-DMA: read from the FIFO
{
return m_539x_1->read(space, 2);
return m_539x_1->read(2);
}
// never executed
@ -201,11 +201,11 @@ WRITE8_MEMBER(macpci_state::mac_5396_w)
{
if (offset < 0x100)
{
m_539x_1->write(space, offset>>4, data);
m_539x_1->write(offset>>4, data);
}
else // pseudo-DMA: write to the FIFO
{
m_539x_1->write(space, 2, data);
m_539x_1->write(2, data);
}
}