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dp8344: SHL uses a bit count of 0-7, not 1-8 (nw)

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This commit is contained in:
AJR 2019-12-01 18:06:00 -05:00
parent 6f9c1e4be2
commit 4c14baf325
2 changed files with 3 additions and 2 deletions
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2
src/devices/cpu/bcp/bcpdasm.cpp
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@ -387,7 +387,7 @@ offs_t dp8344_disassembler::disassemble(std::ostream &stream, offs_t pc, const d
// C900-C9FF: SHL Rsd,b (2 T-states)
util::stream_format(stream, "%-8s", "shl");
format_register(stream, inst & 0x001f);
util::stream_format(stream, ",%d", 8 - ((inst & 0x00e0) >> 5));
util::stream_format(stream, ",%d", (inst & 0x00e0) == 0 ? 0 : 8 - ((inst & 0x00e0) >> 5));
break;
case 0xa00: case 0xa80:

3
src/devices/cpu/bcp/dp8344.cpp
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@ -1653,7 +1653,8 @@ void dp8344_device::store_result()
case 0x900:
set_carry(BIT(m_source_data, (m_latched_instr & 0x00e0) >> 5));
m_source_data <<= 8 - ((m_latched_instr & 0x00e0) >> 5);
if ((m_latched_instr & 0x00e0) != 0)
m_source_data <<= 8 - ((m_latched_instr & 0x00e0) >> 5);
set_nz(m_source_data);
write_register(m_latched_instr & 0x001f, m_source_data);
break;