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- Fixed Context usage and TLB exception vectors in the MIPS core [Harmony]

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This commit is contained in:
Ryan Holtz 2009-11-16 00:04:37 +00:00
parent e0d437dc1d
commit 4cef27ecc9
1 changed files with 2 additions and 1 deletions
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3
src/emu/cpu/mips/mips3drc.c
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@ -1157,9 +1157,10 @@ static void static_generate_exception(mips3_state *mips3, UINT8 exception, int r
if (exception == EXCEPTION_TLBLOAD || exception == EXCEPTION_TLBSTORE) if (exception == EXCEPTION_TLBLOAD || exception == EXCEPTION_TLBSTORE)
{ {
offset = 0x000;
/* set the upper bits of EntryHi and the lower bits of Context to the fault page */ /* set the upper bits of EntryHi and the lower bits of Context to the fault page */
UML_ROLINS(block, CPR032(COP0_EntryHi), IREG(0), IMM(0), IMM(0xffffe000)); // rolins [EntryHi],i0,0,0xffffe000 UML_ROLINS(block, CPR032(COP0_EntryHi), IREG(0), IMM(0), IMM(0xffffe000)); // rolins [EntryHi],i0,0,0xffffe000
UML_ROLINS(block, CPR032(COP0_Context), IREG(0), IMM(32-9), IMM(0x7fffff)); // rolins [Context],i0,32-9,0x7fffff UML_ROLINS(block, CPR032(COP0_Context), IREG(0), IMM(32-9), IMM(0x7ffff0)); // rolins [Context],i0,32-9,0x7fffff
} }
/* set the EPC and Cause registers */ /* set the EPC and Cause registers */