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change_pc? What change_pc?

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This commit is contained in:
Aaron Giles 2008-11-24 02:40:16 +00:00
parent 64164a3e97
commit 513011179d
108 changed files with 116 additions and 907 deletions
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10
src/emu/cpu/arm/arm.c
View File

@ -295,8 +295,6 @@ INLINE UINT32 GetRegister( int rIndex )
INLINE void SetRegister( int rIndex, UINT32 value )
{
arm.sArmRegister[sRegisterTable[MODE][rIndex]] = value;
if (rIndex == eR15)
change_pc(value & ADDRESS_MASK);
}
/***************************************************************************/
@ -311,7 +309,6 @@ static CPU_RESET( arm )
/* start up in SVC mode with interrupts disabled. */
R15 = eARM_MODE_SVC|I_MASK|F_MASK;
change_pc(R15 & ADDRESS_MASK);
}
static CPU_EXIT( arm )
@ -415,7 +412,6 @@ static CPU_EXECUTE( arm )
R15 = eARM_MODE_SVC; /* Set SVC mode so PC is saved to correct R14 bank */
SetRegister( 14, pc ); /* save PC */
R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x8|eARM_MODE_SVC|I_MASK|(pc&MODE_MASK);
change_pc(pc&ADDRESS_MASK);
arm_icount -= 2 * S_CYCLE + N_CYCLE;
}
else /* Undefined */
@ -447,7 +443,6 @@ static CPU_SET_CONTEXT( arm )
if (src)
{
memcpy( &arm, src, sizeof(arm) );
change_pc(R15 & ADDRESS_MASK);
}
}
@ -469,7 +464,6 @@ static void arm_check_irq_state(void)
R15 = eARM_MODE_FIQ; /* Set FIQ mode so PC is saved to correct R14 bank */
SetRegister( 14, pc ); /* save PC */
R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x1c|eARM_MODE_FIQ|I_MASK|F_MASK; /* Mask both IRQ & FIRQ, set PC=0x1c */
change_pc(R15 & ADDRESS_MASK);
arm.pendingFiq=0;
return;
}
@ -478,7 +472,6 @@ static void arm_check_irq_state(void)
R15 = eARM_MODE_IRQ; /* Set IRQ mode so PC is saved to correct R14 bank */
SetRegister( 14, pc ); /* save PC */
R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x18|eARM_MODE_IRQ|I_MASK|(pc&F_MASK); /* Mask only IRQ, set PC=0x18 */
change_pc(R15 & ADDRESS_MASK);
arm.pendingIrq=0;
return;
}
@ -545,7 +538,6 @@ static void HandleBranch( UINT32 insn )
{
R15 += off + 8;
}
change_pc(R15 & ADDRESS_MASK);
arm_icount -= 2 * S_CYCLE + N_CYCLE;
}
@ -621,7 +613,6 @@ static void HandleMemSingle( UINT32 insn )
if (rd == eR15)
{
R15 = (READ32(rnv) & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & MODE_MASK);
change_pc(R15 & ADDRESS_MASK);
/*
The docs are explicit in that the bottom bits should be masked off
@ -857,7 +848,6 @@ static void HandleALU( UINT32 insn )
{
/* Merge the old NZCV flags into the new PC value */
R15 = (rd & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & IRQ_MASK) | (R15&MODE_MASK);
change_pc(R15 & ADDRESS_MASK);
arm_icount -= S_CYCLE + N_CYCLE;
}
else

19
src/emu/cpu/arm7/arm7core.c
View File

@ -533,7 +533,6 @@ static void arm7_core_reset(const device_config *device)
SwitchMode(eARM7_MODE_SVC);
SET_CPSR(GET_CPSR | I_MASK | F_MASK | 0x10);
R15 = 0;
change_pc(R15);
}
// Execute used to be here.. moved to separate file (arm7exec.c) to be included by cpu cores separately
@ -564,7 +563,6 @@ static void arm7_check_irq_state(void)
SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */
SET_CPSR(GET_CPSR & ~T_MASK);
R15 = 0x10; /* IRQ Vector address */
change_pc(R15);
ARM7.pendingAbtD = 0;
return;
}
@ -577,7 +575,6 @@ static void arm7_check_irq_state(void)
SET_CPSR(GET_CPSR | I_MASK | F_MASK); /* Mask both IRQ & FIQ */
SET_CPSR(GET_CPSR & ~T_MASK);
R15 = 0x1c; /* IRQ Vector address */
change_pc(R15);
return;
}
@ -589,7 +586,6 @@ static void arm7_check_irq_state(void)
SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */
SET_CPSR(GET_CPSR & ~T_MASK);
R15 = 0x18; /* IRQ Vector address */
change_pc(R15);
return;
}
@ -601,7 +597,6 @@ static void arm7_check_irq_state(void)
SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */
SET_CPSR(GET_CPSR & ~T_MASK);
R15 = 0x0c; /* IRQ Vector address */
change_pc(R15);
ARM7.pendingAbtP = 0;
return;
}
@ -614,7 +609,6 @@ static void arm7_check_irq_state(void)
SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */
SET_CPSR(GET_CPSR & ~T_MASK);
R15 = 0x04; /* IRQ Vector address */
change_pc(R15);
ARM7.pendingUnd = 0;
return;
}
@ -635,7 +629,6 @@ static void arm7_check_irq_state(void)
SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */
SET_CPSR(GET_CPSR & ~T_MASK); /* Go to ARM mode */
R15 = 0x08; /* Jump to the SWI vector */
change_pc(R15);
ARM7.pendingSwi = 0;
return;
}
@ -792,8 +785,6 @@ static void HandleBranch(UINT32 insn)
{
R15 += off + 8;
}
change_pc(R15);
}
static void HandleMemSingle(UINT32 insn)
@ -866,7 +857,6 @@ static void HandleMemSingle(UINT32 insn)
{
R15 = READ32(rnv);
R15 -= 4;
change_pc(R15);
// LDR, PC takes 2S + 2N + 1I (5 total cycles)
ARM7_ICOUNT -= 2;
}
@ -1100,7 +1090,6 @@ static void HandleHalfWordDT(UINT32 insn)
}
}
}
change_pc(R15);
}
static void HandleSwap(UINT32 insn)
@ -1234,7 +1223,6 @@ static void HandleALU(UINT32 insn)
{
UINT32 op2, sc = 0, rd, rn, opcode;
UINT32 by, rdn;
UINT32 oldR15 = R15;
opcode = (insn & INSN_OPCODE) >> INSN_OPCODE_SHIFT;
@ -1396,9 +1384,6 @@ static void HandleALU(UINT32 insn)
#endif
}
}
if (oldR15 != R15)
change_pc(R15);
}
static void HandleMul(UINT32 insn)
@ -1512,7 +1497,6 @@ static void HandleMemBlock(UINT32 insn)
{
UINT32 rb = (insn & INSN_RN) >> INSN_RN_SHIFT;
UINT32 rbp = GET_REGISTER(rb);
UINT32 oldR15 = R15;
int result;
#if ARM7_DEBUG_CORE
@ -1687,7 +1671,4 @@ static void HandleMemBlock(UINT32 insn)
// STM takes (n+1)S+2N+1I cycles (n = # of register transfers)
ARM7_ICOUNT -= (result + 1) + 2 + 1;
}
if (oldR15 != R15)
change_pc(R15);
} /* HandleMemBlock */

6
src/emu/cpu/arm7/arm7exec.c
View File

@ -513,7 +513,6 @@
if (rd == 7)
{
R15 += 2;
change_pc(R15);
}
break;
case 0x3: /* Add HRd, HRs */
@ -526,7 +525,6 @@
if (rd == 7)
{
R15 += 2;
change_pc(R15);
}
break;
default:
@ -595,7 +593,6 @@
else
{
R15 &= ~1;
change_pc(R15);
}
break;
case 0x3: // MOV Hd, Hs
@ -616,7 +613,6 @@
if (rd == 7)
{
R15 &= ~1;
change_pc(R15);
}
break;
default:
@ -1355,8 +1351,6 @@
}
}
change_pc(R15);
ARM7_CHECKIRQ;
/* All instructions remove 3 cycles.. Others taking less / more will have adjusted this # prior to here */

27
src/emu/cpu/asap/asap.c
View File

@ -266,7 +266,6 @@ static void (*const conditiontable[16])(asap_state *) =
***************************************************************************/
#define ROPCODE(A,pc) memory_decrypted_read_dword((A)->program, pc)
#define UPDATEPC(A) change_pc((A)->pc)
INLINE UINT8 READBYTE(asap_state *asap, offs_t address)
@ -361,7 +360,6 @@ INLINE void generate_exception(asap_state *asap, int exception)
asap->pc = 0x40 * exception;
asap->nextpc = ~0;
UPDATEPC(asap);
asap->icount--;
}
@ -462,8 +460,6 @@ static CPU_RESET( asap )
asap->nextpc = ~0;
asap->irq_state = 0;
asap->irq_callback = NULL;
UPDATEPC(asap);
}
@ -512,7 +508,6 @@ static CPU_EXECUTE( asap )
/* check for IRQs */
asap->icount = cycles;
check_irqs(asap);
UPDATEPC(asap);
/* core execution loop */
if ((device->machine->debug_flags & DEBUG_FLAG_ENABLED) == 0)
@ -615,7 +610,6 @@ static void bsp(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
/*UPDATEPC(asap);*/
execute_instruction(asap);
asap->icount--;
@ -631,7 +625,6 @@ static void bmz(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
/*UPDATEPC(asap);*/
execute_instruction(asap);
asap->icount--;
@ -647,7 +640,6 @@ static void bgt(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
/*UPDATEPC(asap);*/
execute_instruction(asap);
asap->icount--;
@ -663,7 +655,6 @@ static void ble(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
/*UPDATEPC(asap);*/
execute_instruction(asap);
asap->icount--;
@ -679,7 +670,6 @@ static void bge(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
/*UPDATEPC(asap);*/
execute_instruction(asap);
asap->icount--;
@ -695,7 +685,6 @@ static void blt(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
/*UPDATEPC(asap);*/
execute_instruction(asap);
asap->icount--;
@ -711,7 +700,6 @@ static void bhi(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
/*UPDATEPC(asap);*/
execute_instruction(asap);
asap->icount--;
@ -727,7 +715,6 @@ static void bls(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
/*UPDATEPC(asap);*/
execute_instruction(asap);
asap->icount--;
@ -743,7 +730,6 @@ static void bcc(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
/*UPDATEPC(asap);*/
execute_instruction(asap);
asap->icount--;
@ -759,7 +745,6 @@ static void bcs(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
/*UPDATEPC(asap);*/
execute_instruction(asap);
asap->icount--;
@ -775,7 +760,6 @@ static void bpl(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
/*UPDATEPC(asap);*/
execute_instruction(asap);
asap->icount--;
@ -791,7 +775,6 @@ static void bmi(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
/*UPDATEPC(asap);*/
execute_instruction(asap);
asap->icount--;
@ -807,7 +790,6 @@ static void bne(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
/*UPDATEPC(asap);*/
execute_instruction(asap);
asap->icount--;
@ -823,7 +805,6 @@ static void beq(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
/*UPDATEPC(asap);*/
execute_instruction(asap);
asap->icount--;
@ -839,7 +820,6 @@ static void bvc(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
/*UPDATEPC(asap);*/
execute_instruction(asap);
asap->icount--;
@ -855,7 +835,6 @@ static void bvs(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
/*UPDATEPC(asap);*/
execute_instruction(asap);
asap->icount--;
@ -872,7 +851,6 @@ static void bsr(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
/*UPDATEPC(asap);*/
execute_instruction(asap);
asap->icount--;
@ -885,7 +863,6 @@ static void bsr_0(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
/*UPDATEPC(asap);*/
execute_instruction(asap);
asap->icount--;
@ -1621,7 +1598,6 @@ static void jsr(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
UPDATEPC(asap);
execute_instruction(asap);
asap->icount--;
@ -1634,7 +1610,6 @@ static void jsr_0(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
UPDATEPC(asap);
execute_instruction(asap);
asap->icount--;
@ -1649,7 +1624,6 @@ static void jsr_c(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
UPDATEPC(asap);
execute_instruction(asap);
asap->icount--;
@ -1664,7 +1638,6 @@ static void jsr_c0(asap_state *asap)
fetch_instruction(asap);
asap->pc = asap->nextpc;
asap->nextpc = ~0;
UPDATEPC(asap);
execute_instruction(asap);
asap->icount--;

2
src/emu/cpu/ccpu/ccpu.c
View File

@ -112,7 +112,6 @@ static CPU_SET_CONTEXT( ccpu )
/* copy the context */
if (src)
ccpu = *(ccpuRegs *)src;
change_pc(ccpu.PC);
}
@ -296,7 +295,6 @@ static CPU_EXECUTE( ccpu )
/* T4K */
case 0x50:
ccpu.PC = (ccpu.P << 12) + ccpu.J;
change_pc(ccpu.PC);
NEXT_ACC_B(); CYCLES(4);
break;

1
src/emu/cpu/drcfe.c
View File

@ -301,7 +301,6 @@ static opcode_desc *describe_one(drcfe_state *drcfe, offs_t curpc, const opcode_
}
/* get a pointer to the physical address */
change_pc(desc->physpc);
desc->opptr.v = memory_decrypted_read_ptr(drcfe->program, desc->physpc ^ drcfe->codexor);
assert(desc->opptr.v != NULL);
if (desc->opptr.v == NULL)

2
src/emu/cpu/dsp32/dsp32.c
View File

@ -336,7 +336,6 @@ static CPU_SET_CONTEXT( dsp32c )
/* copy the context */
if (src)
dsp32 = *(dsp32_regs *)src;
change_pc(dsp32.PC);
/* check for IRQs */
check_irqs();
@ -365,7 +364,6 @@ static CPU_RESET( dsp32c )
{
/* reset goes to 0 */
dsp32.PC = 0;
change_pc(dsp32.PC);
/* clear some registers */
dsp32.pcw &= 0x03ff;

31
src/emu/cpu/dsp32/dsp32ops.c
View File

@ -692,8 +692,6 @@ static void nop(void)
return;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
@ -702,7 +700,6 @@ static void goto_t(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
@ -713,7 +710,6 @@ static void goto_pl(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -725,7 +721,6 @@ static void goto_mi(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -737,7 +732,6 @@ static void goto_ne(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -749,7 +743,6 @@ static void goto_eq(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -761,7 +754,6 @@ static void goto_vc(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -773,7 +765,6 @@ static void goto_vs(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -785,7 +776,6 @@ static void goto_cc(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -797,7 +787,6 @@ static void goto_cs(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -809,7 +798,6 @@ static void goto_ge(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -821,7 +809,6 @@ static void goto_lt(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -833,7 +820,6 @@ static void goto_gt(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -845,7 +831,6 @@ static void goto_le(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -857,7 +842,6 @@ static void goto_hi(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -869,7 +853,6 @@ static void goto_ls(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -881,7 +864,6 @@ static void goto_auc(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -893,7 +875,6 @@ static void goto_aus(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -905,7 +886,6 @@ static void goto_age(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -917,7 +897,6 @@ static void goto_alt(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -929,7 +908,6 @@ static void goto_ane(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -941,7 +919,6 @@ static void goto_aeq(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -953,7 +930,6 @@ static void goto_avc(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -965,7 +941,6 @@ static void goto_avs(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -977,7 +952,6 @@ static void goto_agt(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -989,7 +963,6 @@ static void goto_ale(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -1100,7 +1073,6 @@ static void dec_goto(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
}
@ -1113,7 +1085,6 @@ static void call(void)
dsp32.r[mr] = dsp32.PC + 4;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (INT16)op);
change_pc(dsp32.PC);
}
@ -1122,7 +1093,6 @@ static void goto24(void)
UINT32 op = OP;
execute_one();
dsp32.PC = TRUNCATE24(REG24((op >> 16) & 0x1f) + (op & 0xffff) + ((op >> 5) & 0xff0000));
change_pc(dsp32.PC);
}
@ -1134,7 +1104,6 @@ static void call24(void)
dsp32.r[mr] = dsp32.PC + 4;
execute_one();
dsp32.PC = (op & 0xffff) + ((op >> 5) & 0xff0000);
change_pc(dsp32.PC);
}

17
src/emu/cpu/dsp56k/dsp56ops.c
View File

@ -594,7 +594,6 @@ static void execute_one(void)
if (size != 0x1337)
{
PC += size;
change_pc(PC);
dsp56k_process_loop();
dsp56k_process_rep(size);
@ -1081,7 +1080,6 @@ static void execute_one(void)
/* Must have been a good opcode */
PC += size;
change_pc(PC);
dsp56k_process_loop();
dsp56k_process_rep(size);
@ -2384,7 +2382,6 @@ static size_t dsp56k_op_bcc(const UINT16 op, const UINT16 op2, UINT8* cycles)
core.ppc = PC;
PC += offset;
change_pc(PC);
cycles += 4;
return 0;
@ -2413,7 +2410,6 @@ static size_t dsp56k_op_bcc_1(const UINT16 op, UINT8* cycles)
core.ppc = PC;
PC += offset;
change_pc(PC) ;
cycles += 4;
return 0;
@ -2457,7 +2453,6 @@ static size_t dsp56k_op_bra_1(const UINT16 op, UINT8* cycles)
/* Jump */
core.ppc = PC;
PC += branchOffset;
change_pc(PC);
/* S L E U N Z V C */
/* - - - - - - - - */
@ -2483,7 +2478,6 @@ static size_t dsp56k_op_brkcc(const UINT16 op, UINT8* cycles)
/* TODO: I think this PC = LA thing is off-by-1, but it's working this way because its consistently so */
core.ppc = PC;
PC = LA;
change_pc(PC);
SR = SSL; /* TODO: A-83. I believe only the Loop Flag and Forever Flag come back here. */
SP--;
@ -2524,7 +2518,6 @@ static size_t dsp56k_op_bscc(const UINT16 op, const UINT16 op2, UINT8* cycles)
/* Change */
core.ppc = PC;
PC = PC + (INT16)op2;
change_pc(PC);
}
/* S L E U N Z V C */
@ -2555,7 +2548,6 @@ static size_t dsp56k_op_bsr(const UINT16 op, const UINT16 op2, UINT8* cycles)
/* Change */
core.ppc = PC;
PC = PC + (INT16)op2;
change_pc(PC);
/* S L E U N Z V C */
/* - - - - - - - - */
@ -2813,7 +2805,6 @@ static size_t dsp56k_op_jmp(const UINT16 op, const UINT16 op2, UINT8* cycles)
{
core.ppc = PC;
PC = op2;
change_pc(PC);
/* S L E U N Z V C */
/* - - - - - - - - */
@ -2830,7 +2821,6 @@ static size_t dsp56k_op_jmp_1(const UINT16 op, UINT8* cycles)
core.ppc = PC;
PC = *((UINT16*)R.addr);
change_pc(PC);
/* S L E U N Z V C */
/* - - - - - - - - */
@ -2858,7 +2848,6 @@ static size_t dsp56k_op_jscc(const UINT16 op, const UINT16 op2, UINT8* cycles)
core.ppc = PC;
PC = branchOffset;
change_pc(PC);
cycles += 4; /* TODO: +jx oscillator clock cycles */
return 0;
@ -2897,7 +2886,6 @@ static size_t dsp56k_op_jsr(const UINT16 op, const UINT16 op2, UINT8* cycles)
core.ppc = PC;
PC = branchOffset;
change_pc(PC);
/* S L E U N Z V C */
/* - - - - - - - - */
@ -3569,7 +3557,6 @@ static size_t dsp56k_op_rti(const UINT16 op, UINT8* cycles)
{
core.ppc = PC;
PC = SSH;
change_pc(PC);
SR = SSL;
SP = SP - 1;
@ -3587,7 +3574,6 @@ static size_t dsp56k_op_rts(const UINT16 op, UINT8* cycles)
/* Pop */
core.ppc = PC;
PC = SSH;
change_pc(PC);
/* SR = SSL; The status register is not affected. */
@ -4255,7 +4241,6 @@ static void dsp56k_process_loop(void)
core.ppc = PC;
PC = SSH;
change_pc(PC);
}
}
else if (LF_bit())
@ -4277,7 +4262,6 @@ static void dsp56k_process_loop(void)
{
LC--;
PC = SSH;
change_pc(PC);
}
}
}
@ -4300,7 +4284,6 @@ static void dsp56k_process_rep(size_t repSize)
{
LC--;
PC -= repSize; /* A little strange - rewind by the size of the rep'd op */
change_pc(PC);
}
}
}

1
src/emu/cpu/dsp56k/dsp56pcu.c
View File

@ -289,7 +289,6 @@ static void pcu_service_interrupts(void)
core.ppc = PC;
PC = irq_vector;
change_pc(PC);
// TODO: 5-9 5-11 Gotta' Clear HC (HCP gets it too) when taking this exception!
HC_bit_set(0);

11
src/emu/cpu/e132xs/e132xs.c
View File

@ -709,7 +709,6 @@ INLINE void set_global_register(UINT8 code, UINT32 val)
if( code == PC_REGISTER )
{
SET_PC(val);
change_pc(PC);
}
else if( code == SR_REGISTER )
{
@ -1266,7 +1265,6 @@ INLINE void execute_br(struct regs_decode *decode)
{
PPC = PC;
PC += EXTRA_S;
change_pc(PC);
SET_M(0);
hyperstone_ICount -= hyperstone.clock_cycles_2;
@ -1304,7 +1302,6 @@ static void execute_trap(UINT32 addr)
PPC = PC;
PC = addr;
change_pc(PC);
hyperstone_ICount -= hyperstone.clock_cycles_2;
}
@ -1334,7 +1331,6 @@ static void execute_int(UINT32 addr)
PPC = PC;
PC = addr;
change_pc(PC);
hyperstone_ICount -= hyperstone.clock_cycles_2;
}
@ -1363,7 +1359,6 @@ static void execute_exception(UINT32 addr)
PPC = PC;
PC = addr;
change_pc(PC);
DEBUG_PRINTF(("EXCEPTION! PPC = %08X PC = %08X\n",PPC-2,PC-2));
hyperstone_ICount -= hyperstone.clock_cycles_2;
@ -1403,7 +1398,6 @@ static void execute_software(struct regs_decode *decode)
PPC = PC;
PC = addr;
change_pc(PC);
}
@ -1697,7 +1691,6 @@ static CPU_RESET( hyperstone )
set_global_register(TPR_REGISTER, 0xc000000);
PC = get_trap_addr(TRAPNO_RESET);
change_pc(PC);
SET_FP(0);
SET_FL(2);
@ -1785,7 +1778,6 @@ INLINE void hyperstone_movd(struct regs_decode *decode)
PPC = PC;
PC = SET_PC(SREG);
change_pc(PC);
SR = (SREGF & 0xffe00000) | ((SREG & 0x01) << 18 ) | (SREGF & 0x3ffff);
if (hyperstone.intblock < 1)
hyperstone.intblock = 1;
@ -4502,7 +4494,6 @@ INLINE void hyperstone_call(struct regs_decode *decode)
PPC = PC;
PC = EXTRA_S; // const value
change_pc(PC);
hyperstone.intblock = 2;
@ -4759,7 +4750,7 @@ static CPU_SET_INFO( hyperstone )
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + E132XS_PC: PC = info->i; change_pc(PC); break;
case CPUINFO_INT_REGISTER + E132XS_PC: PC = info->i; break;
case CPUINFO_INT_REGISTER + E132XS_SR: SR = info->i; break;
case CPUINFO_INT_REGISTER + E132XS_FER: FER = info->i; break;
case CPUINFO_INT_REGISTER + E132XS_G3: set_global_register(3, info->i); break;

2
src/emu/cpu/g65816/g65816.h
View File

@ -97,7 +97,7 @@ CPU_GET_INFO( g65816 );
#define g65816_read_8(addr) memory_read_byte_8be(g65816i_cpu.program, addr)
#define g65816_write_8(addr,data) memory_write_byte_8be(g65816i_cpu.program, addr,data)
#define g65816_read_8_immediate(A) memory_read_byte_8be(g65816i_cpu.program, A)
#define g65816_jumping(A) change_pc(A)
#define g65816_jumping(A)
#define g65816_branching(A)

14
src/emu/cpu/h6280/h6280ops.h
View File

@ -28,7 +28,6 @@
#define S h6280.sp.b.l
#define TRANSLATED(addr) ((h6280.mmr[(addr)>>13] << 13) | ((addr)&0x1fff))
//#define CHANGE_PC do { offs_t temp = TRANSLATED(PCW); change_pc(temp); } while (0)
#define CHANGE_PC
#define H6280_CYCLES(cyc) \
{ \
@ -80,7 +79,6 @@
P = (P & ~_fD) | _fI; /* knock out D and set I flag */ \
PCL = RDMEM(vector); \
PCH = RDMEM((vector+1)); \
CHANGE_PC; \
}
#define CHECK_AND_TAKE_IRQ_LINES \
@ -203,7 +201,6 @@ INLINE void WRMEM(offs_t addr, UINT8 data) {
PCW++; \
EAW = PCW + (signed char)tmp; \
PCD = EAD; \
CHANGE_PC; \
} \
else \
{ \
@ -568,7 +565,6 @@ INLINE void WRMEM(offs_t addr, UINT8 data) {
P = (P & ~_fD) | _fI; \
PCL = RDMEM(H6280_IRQ2_VEC); \
PCH = RDMEM(H6280_IRQ2_VEC+1); \
CHANGE_PC
/* 6280 ********************************************************
* BSR Branch to subroutine
@ -766,7 +762,6 @@ INLINE void WRMEM(offs_t addr, UINT8 data) {
#define JMP \
CLEAR_T; \
PCD = EAD; \
CHANGE_PC
/* 6280 ********************************************************
* JSR Jump to subroutine
@ -779,7 +774,6 @@ INLINE void WRMEM(offs_t addr, UINT8 data) {
PUSH(PCH); \
PUSH(PCL); \
PCD = EAD; \
CHANGE_PC
/* 6280 ********************************************************
* LDA Load accumulator
@ -958,7 +952,6 @@ INLINE void WRMEM(offs_t addr, UINT8 data) {
((P & _fZ) ^ _fZ); \
PULL(PCL); \
PULL(PCH); \
CHANGE_PC; \
CHECK_IRQ_LINES
#else
@ -967,7 +960,6 @@ INLINE void WRMEM(offs_t addr, UINT8 data) {
P |= _fB; \
PULL(PCL); \
PULL(PCH); \
CHANGE_PC; \
CHECK_IRQ_LINES
#endif
@ -979,8 +971,7 @@ INLINE void WRMEM(offs_t addr, UINT8 data) {
CLEAR_T; \
PULL(PCL); \
PULL(PCH); \
PCW++; \
CHANGE_PC
PCW++;
/* 6280 ********************************************************
* SAX Swap accumulator and index X
@ -1204,8 +1195,7 @@ INLINE void WRMEM(offs_t addr, UINT8 data) {
if (tmp&0x10) h6280.mmr[4] = A; \
if (tmp&0x20) h6280.mmr[5] = A; \
if (tmp&0x40) h6280.mmr[6] = A; \
if (tmp&0x80) h6280.mmr[7] = A; \
CHANGE_PC
if (tmp&0x80) h6280.mmr[7] = A
/* 6280 ********************************************************
* TAX Transfer accumulator to index X

6
src/emu/cpu/h83002/h8_16.c
View File

@ -247,7 +247,6 @@ static CPU_RESET(h8)
h8->h8err = 0;
h8->pc = h8_mem_read32(h8, 0) & 0xffffff;
change_pc(h8->pc);
// disable timers
h8->h8TSTR = 0;
@ -270,7 +269,6 @@ static void h8_GenException(h83xx_state *h8, UINT8 vectornr)
if (h8->h8uiflag == 0)
h8_set_ccr(h8, h8_get_ccr(h8) | 0x40);
h8->pc = h8_mem_read32(h8, vectornr * 4) & 0xffffff;
change_pc(h8->pc);
// I couldn't find timing info for exceptions, so this is a guess (based on JSR/BSR)
H8_IFETCH_TIMING(2);
@ -373,8 +371,8 @@ static CPU_SET_INFO( h8 )
h83xx_state *h8 = device->token;
switch(state) {
case CPUINFO_INT_PC: h8->pc = info->i; change_pc(h8->pc); break;
case CPUINFO_INT_REGISTER + H8_PC: h8->pc = info->i; change_pc(h8->pc); break;
case CPUINFO_INT_PC: h8->pc = info->i; break;
case CPUINFO_INT_REGISTER + H8_PC: h8->pc = info->i; break;
case CPUINFO_INT_REGISTER + H8_CCR: h8_set_ccr(h8, info->i); break;
case CPUINFO_INT_REGISTER + H8_E0: h8->regs[0] = info->i; break;

6
src/emu/cpu/h83002/h8_8.c
View File

@ -247,7 +247,6 @@ static CPU_RESET(h8bit)
h8->h8err = 0;
h8->pc = h8_mem_read16(h8, 0);
change_pc(h8->pc);
// disable timers
h8->h8TSTR = 0;
@ -267,7 +266,6 @@ static void h8_GenException(h83xx_state *h8, UINT8 vectornr)
if (h8->h8uiflag == 0)
h8_set_ccr(h8, h8_get_ccr(h8) | 0x40);
h8->pc = h8_mem_read16(h8, vectornr * 2) & 0xffff;
change_pc(h8->pc);
// I couldn't find timing info for exceptions, so this is a guess (based on JSR/BSR)
H8_IFETCH_TIMING(2);
@ -364,8 +362,8 @@ static CPU_SET_INFO( h8 )
h83xx_state *h8 = device->token;
switch(state) {
case CPUINFO_INT_PC: h8->pc = info->i; change_pc(h8->pc); break;
case CPUINFO_INT_REGISTER + H8_PC: h8->pc = info->i; change_pc(h8->pc); break;
case CPUINFO_INT_PC: h8->pc = info->i; break;
case CPUINFO_INT_REGISTER + H8_PC: h8->pc = info->i; break;
case CPUINFO_INT_REGISTER + H8_CCR: h8_set_ccr(h8, info->i); break;
case CPUINFO_INT_REGISTER + H8_E0: h8->regs[0] = info->i; break;

11
src/emu/cpu/h83002/h8ops.h
View File

@ -151,7 +151,6 @@ static CPU_EXECUTE(h8)
// bcc @xx:8
sdata8 = (opcode & 0xff);
if( h8_branch(h8, (opcode >> 8) & 0xf) == 1) h8->pc += sdata8;
change_pc(h8->pc);
break;
case 0x5:
h8_group5(h8, opcode);
@ -1222,7 +1221,6 @@ static void h8_group5(h83xx_state *h8, UINT16 opcode)
h8_setreg32(h8, H8_SP, h8_getreg32(h8, H8_SP)+4);
// extended mode
h8->pc = udata32;
change_pc(h8->pc);
H8_IFETCH_TIMING(2);
H8_STACK_TIMING(2);
H8_IOP_TIMING(2);
@ -1240,7 +1238,6 @@ static void h8_group5(h83xx_state *h8, UINT16 opcode)
h8_setreg32(h8, H8_SP, h8_getreg32(h8, H8_SP)-4);
h8_mem_write32(h8, h8_getreg32(h8, H8_SP), h8->pc);
h8->pc = h8->pc + sdata8;
change_pc(h8->pc);
H8_IFETCH_TIMING(2); H8_STACK_TIMING(2);
break;
case 0x6:
@ -1258,7 +1255,6 @@ static void h8_group5(h83xx_state *h8, UINT16 opcode)
h8_setreg16(h8, H8_SP, h8_getreg16(h8, H8_SP)+2);
h8->pc = udata16;
change_pc(h8->pc);
}
else
{
@ -1268,7 +1264,6 @@ static void h8_group5(h83xx_state *h8, UINT16 opcode)
// extended mode
h8->pc = udata32;
change_pc(h8->pc);
}
// must do this last, because set_ccr() does a check_irq()
h8_set_ccr(h8, (UINT8)udata16);
@ -1299,7 +1294,6 @@ static void h8_group5(h83xx_state *h8, UINT16 opcode)
sdata16 = h8_mem_read16(h8, h8->pc);
h8->pc += 2;
if( h8_branch(h8, (opcode >> 4) & 0xf) == 1) h8->pc += sdata16;
change_pc(h8->pc);
H8_IOP_TIMING(2)
}
break;
@ -1308,7 +1302,6 @@ static void h8_group5(h83xx_state *h8, UINT16 opcode)
address24 = h8_getreg32(h8, (opcode>>4)&7);
address24 &= H8_ADDR_MASK;
h8->pc = address24;
change_pc(h8->pc);
H8_IFETCH_TIMING(2);
break;
// jmp @aa:24
@ -1316,7 +1309,6 @@ static void h8_group5(h83xx_state *h8, UINT16 opcode)
address24 = h8_mem_read32(h8, h8->pc-2);
address24 &= H8_ADDR_MASK;
h8->pc = address24;
change_pc(h8->pc);
H8_IFETCH_TIMING(2);
H8_IOP_TIMING(2);
break;
@ -1334,7 +1326,6 @@ static void h8_group5(h83xx_state *h8, UINT16 opcode)
h8_setreg32(h8, H8_SP, h8_getreg32(h8, H8_SP)-4);
h8_mem_write32(h8, h8_getreg32(h8, H8_SP), h8->pc+2);
h8->pc += sdata16 + 2;
change_pc(h8->pc);
H8_IFETCH_TIMING(2); H8_STACK_TIMING(2); H8_IOP_TIMING(2);
}
break;
@ -1346,7 +1337,6 @@ static void h8_group5(h83xx_state *h8, UINT16 opcode)
h8_setreg32(h8, H8_SP, h8_getreg32(h8, H8_SP)-4);
h8_mem_write32(h8, h8_getreg32(h8, H8_SP), h8->pc);
h8->pc = address24;
change_pc(h8->pc);
H8_STACK_TIMING(2);
H8_IOP_TIMING(2);
break;
@ -1358,7 +1348,6 @@ static void h8_group5(h83xx_state *h8, UINT16 opcode)
h8_setreg32(h8, H8_SP, h8_getreg32(h8, H8_SP)-4);
h8_mem_write32(h8, h8_getreg32(h8, H8_SP), h8->pc+2);
h8->pc = address24;
change_pc(h8->pc);
H8_IFETCH_TIMING(2);
H8_STACK_TIMING(2);
H8_IOP_TIMING(2);

65
src/emu/cpu/hd6309/6309ops.c
View File

@ -37,7 +37,6 @@ OP_HANDLER( illegal )
PUSHBYTE(CC);
PCD = RM16(m68_state, 0xfff0);
CHANGE_PC;
}
static void IIError(m68_state_t *m68_state)
@ -217,7 +216,6 @@ OP_HANDLER( jmp_di )
{
DIRECT;
PCD = EAD;
CHANGE_PC;
}
/* $0F CLR direct -0100 */
@ -273,7 +271,6 @@ OP_HANDLER( lbra )
{
IMMWORD(EAP);
PC += EA;
CHANGE_PC;
if ( EA == 0xfffd ) /* EHC 980508 speed up busy loop */
if ( m68_state->icount > 0)
@ -286,7 +283,6 @@ OP_HANDLER( lbsr )
IMMWORD(EAP);
PUSHWORD(pPC);
PC += EA;
CHANGE_PC;
}
/* $18 ILLEGAL */
@ -393,7 +389,7 @@ OP_HANDLER( exg )
case 2: Y = t2; break;
case 3: U = t2; break;
case 4: S = t2; break;
case 5: PC = t2; CHANGE_PC; break;
case 5: PC = t2; break;
case 6: W = t2; break;
case 7: V = t2; break;
case 8: A = (promote ? t2 >> 8 : t2); break;
@ -411,7 +407,7 @@ OP_HANDLER( exg )
case 2: Y = t1; break;
case 3: U = t1; break;
case 4: S = t1; break;
case 5: PC = t1; CHANGE_PC; break;
case 5: PC = t1; break;
case 6: W = t1; break;
case 7: V = t1; break;
case 8: A = (promote ? t1 >> 8 : t1); break;
@ -463,7 +459,7 @@ OP_HANDLER( tfr )
case 2: Y = t; break;
case 3: U = t; break;
case 4: S = t; break;
case 5: PC = t; CHANGE_PC; break;
case 5: PC = t; break;
case 6: W = t; break;
case 7: V = t; break;
case 8: A = (promote ? t >> 8 : t); break;
@ -483,7 +479,6 @@ OP_HANDLER( bra )
UINT8 t;
IMMBYTE(t);
PC += SIGNED(t);
CHANGE_PC;
/* JB 970823 - speed up busy loops */
if( t == 0xfe )
if( m68_state->icount > 0 ) m68_state->icount = 0;
@ -730,11 +725,6 @@ OP_HANDLER( addr_r )
CLR_NZVC;
*dst16Reg = r16;
SET_FLAGS16(*src16Reg,*dst16Reg,r16);
if ( (tb&15) == 5 )
{
CHANGE_PC;
}
}
else
{
@ -763,11 +753,6 @@ OP_HANDLER( adcr )
CLR_NZVC;
*dst16Reg = r16;
SET_FLAGS16(*src16Reg,*dst16Reg,r16);
if ( (tb&15) == 5 )
{
CHANGE_PC;
}
}
else
{
@ -797,11 +782,6 @@ OP_HANDLER( subr )
CLR_NZVC;
*dst16Reg = r16;
SET_FLAGS16((UINT32)*dst16Reg,(UINT32)*src16Reg,r16);
if ( (tb&15) == 5 )
{
CHANGE_PC;
}
}
else
{
@ -830,11 +810,6 @@ OP_HANDLER( sbcr )
CLR_NZVC;
*dst16Reg = r16;
SET_FLAGS16((UINT32)*dst16Reg,(UINT32)*src16Reg,r16);
if ( (tb&15) == 5 )
{
CHANGE_PC;
}
}
else
{
@ -863,11 +838,6 @@ OP_HANDLER( andr )
CLR_NZV;
*dst16Reg = r16;
SET_NZ16(r16);
if ( (tb&15) == 5 )
{
CHANGE_PC;
}
}
else
{
@ -896,11 +866,6 @@ OP_HANDLER( orr )
CLR_NZV;
*dst16Reg = r16;
SET_NZ16(r16);
if ( (tb&15) == 5 )
{
CHANGE_PC;
}
}
else
{
@ -929,11 +894,6 @@ OP_HANDLER( eorr )
CLR_NZV;
*dst16Reg = r16;
SET_NZ16(r16);
if ( (tb&15) == 5 )
{
CHANGE_PC;
}
}
else
{
@ -998,7 +958,6 @@ OP_HANDLER( tfmpp )
}
PCD = PCD - 3;
CHANGE_PC;
W--;
}
else
@ -1033,7 +992,6 @@ OP_HANDLER( tfmmm )
}
PCD = PCD - 3;
CHANGE_PC;
W--;
}
else
@ -1068,7 +1026,6 @@ OP_HANDLER( tfmpc )
}
PCD = PCD - 3;
CHANGE_PC;
W--;
}
else
@ -1103,7 +1060,6 @@ OP_HANDLER( tfmcp )
}
PCD = PCD - 3;
CHANGE_PC;
W--;
}
else
@ -1182,7 +1138,7 @@ OP_HANDLER( puls )
if( t&0x10 ) { PULLWORD(XD); m68_state->icount -= 2; }
if( t&0x20 ) { PULLWORD(YD); m68_state->icount -= 2; }
if( t&0x40 ) { PULLWORD(UD); m68_state->icount -= 2; }
if( t&0x80 ) { PULLWORD(PCD); CHANGE_PC; m68_state->icount -= 2; }
if( t&0x80 ) { PULLWORD(PCD); m68_state->icount -= 2; }
/* HJB 990225: moved check after all PULLs */
if( t&0x01 ) { check_irq_lines(m68_state); }
@ -1227,7 +1183,7 @@ OP_HANDLER( pulu )
if( t&0x10 ) { PULUWORD(XD); m68_state->icount -= 2; }
if( t&0x20 ) { PULUWORD(YD); m68_state->icount -= 2; }
if( t&0x40 ) { PULUWORD(SD); m68_state->icount -= 2; }
if( t&0x80 ) { PULUWORD(PCD); CHANGE_PC; m68_state->icount -= 2; }
if( t&0x80 ) { PULUWORD(PCD); m68_state->icount -= 2; }
/* HJB 990225: moved check after all PULLs */
if( t&0x01 ) { check_irq_lines(m68_state); }
@ -1239,7 +1195,6 @@ OP_HANDLER( pulu )
OP_HANDLER( rts )
{
PULLWORD(PCD);
CHANGE_PC;
}
/* $3A ABX inherent ----- */
@ -1271,7 +1226,6 @@ OP_HANDLER( rti )
PULLWORD(UD);
}
PULLWORD(PCD);
CHANGE_PC;
check_irq_lines(m68_state); /* HJB 990116 */
}
@ -1337,7 +1291,6 @@ OP_HANDLER( swi )
PUSHBYTE(CC);
CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */
PCD=RM16(m68_state, 0xfffa);
CHANGE_PC;
}
/* $1130 BAND */
@ -1508,7 +1461,6 @@ OP_HANDLER( swi2 )
PUSHBYTE(A);
PUSHBYTE(CC);
PCD = RM16(m68_state, 0xfff4);
CHANGE_PC;
}
/* $113F SWI3 absolute indirect ----- */
@ -1529,7 +1481,6 @@ OP_HANDLER( swi3 )
PUSHBYTE(A);
PUSHBYTE(CC);
PCD = RM16(m68_state, 0xfff2);
CHANGE_PC;
}
/* $40 NEGA inherent ?**** */
@ -2180,7 +2131,6 @@ OP_HANDLER( jmp_ix )
{
fetch_effective_address(m68_state);
PCD = EAD;
CHANGE_PC;
}
/* $6F CLR indexed -0100 */
@ -2334,7 +2284,6 @@ OP_HANDLER( jmp_ex )
{
EXTENDED;
PCD = EAD;
CHANGE_PC;
}
/* $7F CLR extended -0100 */
@ -2555,7 +2504,6 @@ OP_HANDLER( bsr )
IMMBYTE(t);
PUSHWORD(pPC);
PC += SIGNED(t);
CHANGE_PC;
}
/* $8E LDX (LDY) immediate -**0- */
@ -2905,7 +2853,6 @@ OP_HANDLER( jsr_di )
DIRECT;
PUSHWORD(pPC);
PCD = EAD;
CHANGE_PC;
}
/* $9E LDX (LDY) direct -**0- */
@ -3297,7 +3244,6 @@ OP_HANDLER( jsr_ix )
fetch_effective_address(m68_state);
PUSHWORD(pPC);
PCD = EAD;
CHANGE_PC;
}
/* $aE LDX (LDY) indexed -**0- */
@ -3686,7 +3632,6 @@ OP_HANDLER( jsr_ex )
EXTENDED;
PUSHWORD(pPC);
PCD = EAD;
CHANGE_PC;
}
/* $bE LDX (LDY) extended -**0- */

10
src/emu/cpu/hd6309/hd6309.c
View File

@ -214,8 +214,6 @@ INLINE void fetch_effective_address( m68_state_t *m68_state );
#define EAD m68_state->ea.d
#define EAP m68_state->ea
#define CHANGE_PC change_pc(PCD)
#define M6809_CWAI 8 /* set when CWAI is waiting for an interrupt */
#define M6809_SYNC 16 /* set when SYNC is waiting for an interrupt */
#define M6809_LDS 32 /* set when LDS occured at least once */
@ -349,7 +347,6 @@ INLINE void fetch_effective_address( m68_state_t *m68_state );
if( f ) \
{ \
PC += SIGNED(t); \
CHANGE_PC; \
} \
}
@ -361,7 +358,6 @@ INLINE void fetch_effective_address( m68_state_t *m68_state );
if( !(MD & MD_EM) ) \
m68_state->icount -= 1; \
PC += t.w.l; \
CHANGE_PC; \
} \
}
@ -459,7 +455,6 @@ static void check_irq_lines( m68_state_t *m68_state )
}
CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */
PCD=RM16(m68_state, 0xfff6);
CHANGE_PC;
(void)(*m68_state->irq_callback)(m68_state->device, HD6309_FIRQ_LINE);
}
else
@ -493,7 +488,6 @@ static void check_irq_lines( m68_state_t *m68_state )
}
CC |= CC_II; /* inhibit IRQ */
PCD=RM16(m68_state, 0xfff8);
CHANGE_PC;
(void)(*m68_state->irq_callback)(m68_state->device, HD6309_IRQ_LINE);
}
}
@ -577,7 +571,6 @@ static CPU_RESET( hd6309 )
CC |= CC_IF; /* FIRQ disabled */
PCD = RM16(m68_state, 0xfffe);
CHANGE_PC;
UpdateState(m68_state);
}
@ -630,7 +623,6 @@ static void set_irq_line(m68_state_t *m68_state, int irqline, int state)
}
CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */
PCD = RM16(m68_state, 0xfffc);
CHANGE_PC;
}
else if (irqline < 2)
{
@ -1246,7 +1238,7 @@ static CPU_SET_INFO( hd6309 )
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(m68_state, INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + HD6309_PC: PC = info->i; CHANGE_PC; break;
case CPUINFO_INT_REGISTER + HD6309_PC: PC = info->i; break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + HD6309_S: S = info->i; break;
case CPUINFO_INT_REGISTER + HD6309_CC: CC = info->i; check_irq_lines(m68_state); break;

4
src/emu/cpu/i386/i386.h
View File

@ -381,8 +381,6 @@ INLINE void CHANGE_PC(UINT32 pc)
{
translate_address(&address);
}
change_pc(address & I.a20_mask);
}
INLINE void NEAR_BRANCH(INT32 offs)
@ -398,8 +396,6 @@ INLINE void NEAR_BRANCH(INT32 offs)
{
translate_address(&address);
}
change_pc(address & I.a20_mask);
}
INLINE UINT8 FETCH(void)

7
src/emu/cpu/i8085/i8085.c
View File

@ -1084,7 +1084,6 @@ INLINE void execute_one(int opcode)
break;
case 0xe9: i8085_ICount -= (I.cputype) ? 6 : 5; /* PCHL */
I.PC.d = I.HL.w.l;
change_pc(I.PC.d);
break;
case 0xea: i8085_ICount -= 10; /* JPE nnnn */
M_JMP( I.AF.b.l & VF );
@ -1280,7 +1279,6 @@ static void Interrupt(void)
case 0xc30000: /* JMP nnnn */
i8085_ICount -= 10;
I.PC.d = I.IRQ1 & 0xffff;
change_pc(I.PC.d);
break;
default:
switch( I.ISRV )
@ -1294,7 +1292,6 @@ static void Interrupt(void)
I.PC.d = I.IRQ1;
else
I.PC.d = 0x3c;
change_pc(I.PC.d);
break;
default:
LOG(("i8085 take int $%02x\n", I.IRQ1));
@ -1405,7 +1402,6 @@ static CPU_RESET( i8085 )
I.device = device;
I.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
I.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
change_pc(I.PC.d);
I.cputype = cputype_bak;
}
@ -1435,7 +1431,6 @@ static CPU_SET_CONTEXT( i8085 )
if( src )
{
I = *(i8085_Regs*)src;
change_pc(I.PC.d);
}
}
@ -1663,7 +1658,7 @@ static CPU_SET_INFO( i8085 )
case CPUINFO_INT_INPUT_STATE + I8085_RST75_LINE:i8085_set_irq_line(I8085_RST75_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: i8085_set_irq_line(INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_PC: I.PC.w.l = info->i; change_pc(I.PC.d); break;
case CPUINFO_INT_PC: I.PC.w.l = info->i; break;
case CPUINFO_INT_REGISTER + I8085_PC: I.PC.w.l = info->i; break;
case CPUINFO_INT_SP: I.SP.w.l = info->i; break;
case CPUINFO_INT_REGISTER + I8085_SP: I.SP.w.l = info->i; break;

4
src/emu/cpu/i8085/i8085cpu.h
View File

@ -142,7 +142,6 @@ int q = I.AF.b.h+R; \
{ \
i8085_ICount -= 6; \
M_POP(PC); \
change_pc(I.PC.d); \
} \
}
@ -150,7 +149,6 @@ int q = I.AF.b.h+R; \
#define M_JMP(cc) { \
if (cc) { \
I.PC.w.l = ARG16(); \
change_pc(I.PC.d); \
} else { \
I.PC.w.l += 2; \
i8085_ICount += (I.cputype) ? 3 : 0; \
@ -166,7 +164,6 @@ int q = I.AF.b.h+R; \
i8085_ICount -= (I.cputype) ? 7 : 6 ; \
M_PUSH(PC); \
I.PC.d = a; \
change_pc(I.PC.d); \
} else { \
I.PC.w.l += 2; \
i8085_ICount += (I.cputype) ? 2 : 0; \
@ -176,7 +173,6 @@ int q = I.AF.b.h+R; \
#define M_RST(nn) { \
M_PUSH(PC); \
I.PC.d = 8 * nn; \
change_pc(I.PC.d); \
}
#define M_DSUB() { \

3
src/emu/cpu/i86/i86.c
View File

@ -178,8 +178,6 @@ static CPU_RESET( i8086 )
I.base[CS] = SegBase(CS);
I.pc = 0xffff0 & AMASK;
ExpandFlags(I.flags);
change_pc(I.pc);
}
static CPU_EXIT( i8086 )
@ -204,7 +202,6 @@ static CPU_SET_CONTEXT( i8086 )
I.base[DS] = SegBase(DS);
I.base[ES] = SegBase(ES);
I.base[SS] = SegBase(SS);
change_pc(I.pc);
}
}

2
src/emu/cpu/i86/i86.h
View File

@ -103,7 +103,7 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,SIH,SIL,DIH,DIL } BREGS;
#define FETCHOP (memory_decrypted_read_byte(I.program, FETCH_XOR(I.pc++)))
#define PEEKOP(addr) (memory_decrypted_read_byte(I.program, FETCH_XOR(addr)))
#define FETCHWORD(var) { var = memory_raw_read_byte(I.program, FETCH_XOR(I.pc)); var += (memory_raw_read_byte(I.program, FETCH_XOR(I.pc + 1)) << 8); I.pc += 2; }
#define CHANGE_PC(addr) change_pc(addr)
#define CHANGE_PC(addr)
#define PUSH(val) { I.regs.w[SP] -= 2; WriteWord(((I.base[SS] + I.regs.w[SP]) & AMASK), val); }
#define POP(var) { var = ReadWord(((I.base[SS] + I.regs.w[SP]) & AMASK)); I.regs.w[SP] += 2; }

15
src/emu/cpu/i960/i960.c
View File

@ -98,7 +98,6 @@ INLINE void send_iac(i960_state_t *i960, UINT32 adr)
i960->SAT = iac[1];
i960->PRCB = iac[2];
i960->IP = iac[3];
change_pc(i960->IP);
break;
default:
fatalerror("I960: %x: IAC %08x %08x %08x %08x", i960->PIP, iac[0], iac[1], iac[2], iac[3]);
@ -377,7 +376,6 @@ INLINE void bxx(i960_state_t *i960, UINT32 opcode, int mask)
{
if(i960->AC & mask) {
i960->IP += get_disp(i960, opcode);
change_pc(i960->IP);
}
}
@ -385,7 +383,6 @@ INLINE void bxx_s(i960_state_t *i960, UINT32 opcode, int mask)
{
if(i960->AC & mask) {
i960->IP += get_disp_s(i960, opcode);
change_pc(i960->IP);
}
}
@ -547,8 +544,6 @@ static void do_call(i960_state_t *i960, UINT32 adr, int type, UINT32 stack)
i960->r[I960_FP] = (i960->r[I960_SP] + 63) & ~63;
i960->r[I960_SP] = i960->r[I960_FP] + 64;
change_pc(i960->IP);
}
static void do_ret_0(i960_state_t *i960)
@ -580,7 +575,6 @@ static void do_ret_0(i960_state_t *i960)
// mame_printf_debug("RET (type %d): FP %x, %x => %x, rcache_pos %d\n", type, i960->r[I960_FP], i960->IP, i960->r[I960_RIP], i960->rcache_pos);
i960->IP = i960->r[I960_RIP];
change_pc(i960->IP);
}
static void do_ret(i960_state_t *i960)
@ -618,7 +612,6 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode)
case 0x08: // b
i960->icount--;
i960->IP += get_disp(i960, opcode);
change_pc(i960->IP);
break;
case 0x09: // call
@ -633,14 +626,12 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode)
i960->icount -= 5;
i960->r[0x1e] = i960->IP;
i960->IP += get_disp(i960, opcode);
change_pc(i960->IP);
break;
case 0x10: // bno
i960->icount--;
if(!(i960->AC & 7)) {
i960->IP += get_disp(i960, opcode);
change_pc(i960->IP);
}
break;
@ -729,7 +720,6 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode)
if(!(t2 & (1<<t1))) {
i960->AC = (i960->AC & ~7) | 2;
i960->IP += get_disp_s(i960, opcode);
change_pc(i960->IP);
} else
i960->AC &= ~7;
break;
@ -789,7 +779,6 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode)
if(t2 & (1<<t1)) {
i960->AC = (i960->AC & ~7) | 2;
i960->IP += get_disp_s(i960, opcode);
change_pc(i960->IP);
} else
i960->AC &= ~7;
break;
@ -1799,7 +1788,6 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode)
case 0x84: // bx
i960->icount -= 3;
i960->IP = get_ea(i960, opcode);
change_pc(i960->IP);
break;
case 0x85: // balx
@ -1807,7 +1795,6 @@ INLINE void execute_op(i960_state_t *i960, UINT32 opcode)
t1 = get_ea(i960, opcode);
i960->r[(opcode>>19)&0x1f] = i960->IP;
i960->IP = t1;
change_pc(i960->IP);
break;
case 0x86: // callx
@ -2058,7 +2045,7 @@ static CPU_SET_INFO( i960 )
switch(state) {
// Interfacing
case CPUINFO_INT_REGISTER + I960_IP: i960->IP = info->i; change_pc(i960->IP); break;
case CPUINFO_INT_REGISTER + I960_IP: i960->IP = info->i; break;
case CPUINFO_INT_INPUT_STATE + I960_IRQ0: set_irq_line(i960, I960_IRQ0, info->i); break;
case CPUINFO_INT_INPUT_STATE + I960_IRQ1: set_irq_line(i960, I960_IRQ1, info->i); break;
case CPUINFO_INT_INPUT_STATE + I960_IRQ2: set_irq_line(i960, I960_IRQ2, info->i); break;

9
src/emu/cpu/konami/konami.c
View File

@ -131,7 +131,6 @@ static PAIR ea; /* effective address */
} \
CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */ \
PCD = RM16(0xfff6); \
change_pc(PC); /* TS 971002 */ \
(void)(*konami.irq_callback)(konami.device, KONAMI_FIRQ_LINE); \
} \
else \
@ -159,7 +158,6 @@ static PAIR ea; /* effective address */
} \
CC |= CC_II; /* inhibit IRQ */ \
PCD = RM16(0xfff8); \
change_pc(PC); /* TS 971002 */ \
(void)(*konami.irq_callback)(konami.device, KONAMI_IRQ_LINE); \
}
@ -291,7 +289,6 @@ CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N
if( f ) \
{ \
PC += SIGNED(t); \
change_pc(PC); /* TS 971002 */ \
} \
}
@ -302,7 +299,6 @@ CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N
{ \
konami_ICount -= 1; \
PC += t.w.l; \
change_pc(PC); /* TS 971002 */ \
} \
}
@ -381,7 +377,6 @@ static CPU_SET_CONTEXT( konami )
{
if( src )
konami = *(konami_Regs*)src;
change_pc(PC); /* TS 971002 */
CHECK_IRQ_LINES;
}
@ -422,7 +417,6 @@ static CPU_RESET( konami )
CC |= CC_IF; /* FIRQ disabled */
PCD = RM16(0xfffe);
change_pc(PC); /* TS 971002 */
}
static CPU_EXIT( konami )
@ -467,7 +461,6 @@ static void set_irq_line(int irqline, int state)
}
CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */
PCD = RM16(0xfffc);
change_pc(PC); /* TS 971002 */
}
else if (irqline < 2)
{
@ -533,7 +526,7 @@ static CPU_SET_INFO( konami )
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + KONAMI_PC: PC = info->i; change_pc(PC); break;
case CPUINFO_INT_REGISTER + KONAMI_PC: PC = info->i; break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + KONAMI_S: S = info->i; break;
case CPUINFO_INT_REGISTER + KONAMI_CC: CC = info->i; CHECK_IRQ_LINES; break;

19
src/emu/cpu/konami/konamops.c
View File

@ -147,7 +147,6 @@ INLINE void jmp_di( void )
{
DIRECT;
PCD=EAD;
change_pc(PCD);
}
/* $0F CLR direct -0100 */
@ -192,7 +191,6 @@ INLINE void lbra( void )
{
IMMWORD(ea);
PC += EA;
change_pc(PCD);
/* EHC 980508 speed up busy loop */
if( EA == 0xfffd && konami_ICount > 0 )
@ -205,7 +203,6 @@ INLINE void lbsr( void )
IMMWORD(ea);
PUSHWORD(pPC);
PC += EA;
change_pc(PCD);
}
/* $18 ILLEGAL */
@ -304,7 +301,6 @@ INLINE void bra( void )
UINT8 t;
IMMBYTE(t);
PC += SIGNED(t);
change_pc(PCD);
/* JB 970823 - speed up busy loops */
if( t == 0xfe && konami_ICount > 0 )
konami_ICount = 0;
@ -547,7 +543,7 @@ INLINE void puls( void )
if( t&0x10 ) { PULLWORD(XD); konami_ICount -= 2; }
if( t&0x20 ) { PULLWORD(YD); konami_ICount -= 2; }
if( t&0x40 ) { PULLWORD(UD); konami_ICount -= 2; }
if( t&0x80 ) { PULLWORD(PCD); change_pc(PCD); konami_ICount -= 2; }
if( t&0x80 ) { PULLWORD(PCD); konami_ICount -= 2; }
/* check after all PULLs */
if( t&0x01 ) { CHECK_IRQ_LINES; }
@ -580,7 +576,7 @@ INLINE void pulu( void )
if( t&0x10 ) { PULUWORD(XD); konami_ICount -= 2; }
if( t&0x20 ) { PULUWORD(YD); konami_ICount -= 2; }
if( t&0x40 ) { PULUWORD(SD); konami_ICount -= 2; }
if( t&0x80 ) { PULUWORD(PCD); change_pc(PCD); konami_ICount -= 2; }
if( t&0x80 ) { PULUWORD(PCD); konami_ICount -= 2; }
/* check after all PULLs */
if( t&0x01 ) { CHECK_IRQ_LINES; }
@ -592,7 +588,6 @@ INLINE void pulu( void )
INLINE void rts( void )
{
PULLWORD(PCD);
change_pc(PCD);
}
/* $3A ABX inherent ----- */
@ -616,7 +611,6 @@ INLINE void rti( void )
PULLWORD(UD);
}
PULLWORD(PCD);
change_pc(PCD);
CHECK_IRQ_LINES;
}
@ -671,7 +665,6 @@ INLINE void swi( void )
PUSHBYTE(CC);
CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */
PCD=RM16(0xfffa);
change_pc(PCD);
}
/* $103F SWI2 absolute indirect ----- */
@ -687,7 +680,6 @@ INLINE void swi2( void )
PUSHBYTE(A);
PUSHBYTE(CC);
PCD=RM16(0xfff4);
change_pc(PCD);
}
/* $113F SWI3 absolute indirect ----- */
@ -703,7 +695,6 @@ INLINE void swi3( void )
PUSHBYTE(A);
PUSHBYTE(CC);
PCD=RM16(0xfff2);
change_pc(PCD);
}
/* $40 NEGA inherent ?**** */
@ -1045,7 +1036,6 @@ INLINE void tst_ix( void )
INLINE void jmp_ix( void )
{
PCD=EAD;
change_pc(PCD);
}
/* $6F CLR indexed -0100 */
@ -1158,7 +1148,6 @@ INLINE void jmp_ex( void )
{
EXTENDED;
PCD=EAD;
change_pc(PCD);
}
/* $7F CLR extended -0100 */
@ -1363,7 +1352,6 @@ INLINE void bsr( void )
IMMBYTE(t);
PUSHWORD(pPC);
PC += SIGNED(t);
change_pc(PCD);
}
/* $8E LDX (LDY) immediate -**0- */
@ -1594,7 +1582,6 @@ INLINE void jsr_di( void )
DIRECT;
PUSHWORD(pPC);
PCD=EAD;
change_pc(PCD);
}
/* $9E LDX (LDY) direct -**0- */
@ -1813,7 +1800,6 @@ INLINE void jsr_ix( void )
{
PUSHWORD(pPC);
PCD=EAD;
change_pc(PCD);
}
/* $aE LDX (LDY) indexed -**0- */
@ -2039,7 +2025,6 @@ INLINE void jsr_ex( void )
EXTENDED;
PUSHWORD(pPC);
PCD=EAD;
change_pc(PCD);
}
/* $bE LDX (LDY) extended -**0- */

8
src/emu/cpu/lh5801/5801tbl.c
View File

@ -192,14 +192,12 @@ INLINE void lh5801_rtn(void)
{
P=memory_read_byte(lh5801.program,++S)<<8;
P|=memory_read_byte(lh5801.program,++S);
change_pc(P);
}
INLINE void lh5801_rti(void)
{
P=memory_read_byte(lh5801.program,++S)<<8;
P|=memory_read_byte(lh5801.program,++S);
change_pc(P);
lh5801.t=memory_read_byte(lh5801.program,++S);
}
@ -217,7 +215,6 @@ INLINE void lh5801_push_word(UINT16 data)
INLINE void lh5801_jmp(UINT16 adr)
{
P=adr;
change_pc(P);
}
INLINE void lh5801_branch_plus(int doit)
@ -226,7 +223,6 @@ INLINE void lh5801_branch_plus(int doit)
if (doit) {
lh5801_icount-=3;
P+=t;
change_pc(P);
}
}
@ -236,7 +232,6 @@ INLINE void lh5801_branch_minus(int doit)
if (doit) {
lh5801_icount-=3;
P-=t;
change_pc(P);
}
}
@ -247,7 +242,6 @@ INLINE void lh5801_lop(void)
if (UL--) {
lh5801_icount-=3;
P-=t;
change_pc(P);
}
}
@ -256,7 +250,6 @@ INLINE void lh5801_sjp(void)
UINT16 n=lh5801_readop_word();
lh5801_push_word(P);
P=n;
change_pc(n);
}
INLINE void lh5801_vector(int doit, int nr)
@ -265,7 +258,6 @@ INLINE void lh5801_vector(int doit, int nr)
lh5801_push_word(P);
P=memory_read_byte(lh5801.program,0xff00+nr)<<8;
P|=memory_read_byte(lh5801.program,0xff00+nr+1);
change_pc(P);
lh5801_icount-=21-8;
}
lh5801.t&=~Z; // after the jump!?

5
src/emu/cpu/lh5801/lh5801.c
View File

@ -104,8 +104,6 @@ static CPU_RESET( lh5801 )
{
P = (memory_read_byte(lh5801.program, 0xfffe)<<8) | memory_read_byte(lh5801.program, 0xffff);
change_pc(P);
lh5801.idle=0;
}
@ -120,7 +118,6 @@ static CPU_SET_CONTEXT( lh5801 )
if( src )
{
lh5801 = *(LH5801_Regs*)src;
change_pc(P);
}
}
@ -128,8 +125,6 @@ static CPU_EXECUTE( lh5801 )
{
lh5801_icount = cycles;
change_pc(P);
if (lh5801.idle) {
lh5801_icount=0;
} else {

5
src/emu/cpu/lr35902/lr35902.c
View File

@ -347,7 +347,6 @@ static CPU_SET_CONTEXT( lr35902 )
{
if( src )
Regs = *(lr35902_regs *)src;
change_pc(Regs.w.PC);
}
/****************************************************************************/
@ -403,9 +402,9 @@ static CPU_SET_INFO( lr35902 )
case CPUINFO_INT_INPUT_STATE + 4: lr35902_set_irq_line(state-CPUINFO_INT_INPUT_STATE, info->i); break;
case CPUINFO_INT_SP: Regs.w.SP = info->i; break;
case CPUINFO_INT_PC: Regs.w.PC = info->i; change_pc(Regs.w.PC); break;
case CPUINFO_INT_PC: Regs.w.PC = info->i; break;
case CPUINFO_INT_REGISTER + LR35902_PC: Regs.w.PC = info->i; change_pc(Regs.w.PC); break;
case CPUINFO_INT_REGISTER + LR35902_PC: Regs.w.PC = info->i; break;
case CPUINFO_INT_REGISTER + LR35902_SP: Regs.w.SP = info->i; break;
case CPUINFO_INT_REGISTER + LR35902_AF: Regs.w.AF = info->i; break;
case CPUINFO_INT_REGISTER + LR35902_BC: Regs.w.BC = info->i; break;

2
src/emu/cpu/m37710/m37710.h
View File

@ -106,7 +106,7 @@ void m37710_state_load(void *file);
#define m37710_read_8_immediate(A) memory_read_byte_16le(m37710i_cpu->program, A)
#define m37710_read_16(addr) memory_read_word_16le(m37710i_cpu->program, addr)
#define m37710_write_16(addr,data) memory_write_word_16le(m37710i_cpu->program, addr,data)
#define m37710_jumping(A) change_pc(A)
#define m37710_jumping(A)
#define m37710_branching(A)

9
src/emu/cpu/m6502/m4510.c
View File

@ -228,8 +228,6 @@ static CPU_RESET( m4510 )
m4510->high=0x8200;
m4510->mem[7]=0x20000;
CHANGE_PC;
m4510->port = 0xff;
m4510->ddr = 0x00;
}
@ -250,7 +248,6 @@ static CPU_SET_CONTEXT( m4510 )
{
token = src;
m4510 = token;
CHANGE_PC;
}
}
@ -270,7 +267,6 @@ INLINE void m4510_take_irq(m4510_Regs *m4510)
LOG(("M4510#%d takes IRQ ($%04x)\n", cpunum_get_active(), PCD));
/* call back the cpuintrf to let it clear the line */
if (m4510->irq_callback) (*m4510->irq_callback)(m4510->device, 0);
CHANGE_PC;
}
m4510->pending_irq = 0;
}
@ -281,8 +277,6 @@ static CPU_EXECUTE( m4510 )
m4510->icount = cycles;
CHANGE_PC;
do
{
UINT8 op;
@ -339,7 +333,6 @@ static void m4510_set_irq_line(m4510_Regs *m4510, int irqline, int state)
PCL = RDMEM(EAD);
PCH = RDMEM(EAD+1);
LOG(("M4510#%d takes NMI ($%04x)\n", cpunum_get_active(), PCD));
CHANGE_PC;
}
}
else
@ -422,7 +415,7 @@ static CPU_SET_INFO( m4510 )
case CPUINFO_INT_INPUT_STATE + M4510_IRQ_LINE: m4510_set_irq_line(m4510, M4510_IRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: m4510_set_irq_line(m4510, INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_PC: PCW = info->i; change_pc(PCD); break;
case CPUINFO_INT_PC: PCW = info->i; break;
case CPUINFO_INT_REGISTER + M4510_PC: m4510->pc.w.l = info->i; break;
case CPUINFO_INT_SP: SPL = info->i; break;
case CPUINFO_INT_REGISTER + M4510_S: m4510->sp.b.l = info->i; break;

19
src/emu/cpu/m6502/m6502.c
View File

@ -188,8 +188,6 @@ static CPU_RESET( m6502 )
m6502->after_cli = 0; /* pending IRQ and last insn cleared I */
m6502->irq_state = 0;
m6502->nmi_state = 0;
change_pc(PCD);
}
static CPU_EXIT( m6502 )
@ -209,7 +207,6 @@ static CPU_SET_CONTEXT( m6502 )
{
token = src;
m6502 = token;
change_pc(PCD);
}
}
@ -228,7 +225,6 @@ INLINE void m6502_take_irq(m6502_Regs *m6502)
LOG(("M6502#%d takes IRQ ($%04x)\n", cpunum_get_active(), PCD));
/* call back the cpuintrf to let it clear the line */
if (m6502->irq_callback) (*m6502->irq_callback)(m6502->device, 0);
change_pc(PCD);
}
m6502->pending_irq = 0;
}
@ -239,8 +235,6 @@ static CPU_EXECUTE( m6502 )
m6502->icount = cycles;
change_pc(PCD);
do
{
UINT8 op;
@ -306,7 +300,6 @@ static void m6502_set_irq_line(m6502_Regs *m6502, int irqline, int state)
PCL = RDMEM(EAD);
PCH = RDMEM(EAD+1);
LOG(("M6502#%d takes NMI ($%04x)\n", cpunum_get_active(), PCD));
change_pc(PCD);
}
}
else
@ -458,7 +451,6 @@ INLINE void m65c02_take_irq(m6502_Regs *m6502)
LOG(("M65c02#%d takes IRQ ($%04x)\n", cpunum_get_active(), PCD));
/* call back the cpuintrf to let it clear the line */
if (m6502->irq_callback) (*m6502->irq_callback)(m6502->device, 0);
change_pc(PCD);
}
m6502->pending_irq = 0;
}
@ -469,8 +461,6 @@ static CPU_EXECUTE( m65c02 )
m6502->icount = cycles;
change_pc(PCD);
do
{
UINT8 op;
@ -528,7 +518,6 @@ static void m65c02_set_irq_line(m6502_Regs *m6502, int irqline, int state)
PCL = RDMEM(EAD);
PCH = RDMEM(EAD+1);
LOG(("M6502#%d takes NMI ($%04x)\n", cpunum_get_active(), PCD));
change_pc(PCD);
}
}
else
@ -574,8 +563,6 @@ static CPU_RESET( deco16 )
m6502->p = F_T|F_I|F_Z|F_B|(P&F_D); /* set T, I and Z flags */
m6502->pending_irq = 0; /* nonzero if an IRQ is pending */
m6502->after_cli = 0; /* pending IRQ and last insn cleared I */
change_pc(PCD);
}
INLINE void deco16_take_irq(m6502_Regs *m6502)
@ -593,7 +580,6 @@ INLINE void deco16_take_irq(m6502_Regs *m6502)
LOG(("M6502#%d takes IRQ ($%04x)\n", cpunum_get_active(), PCD));
/* call back the cpuintrf to let it clear the line */
if (m6502->irq_callback) (*m6502->irq_callback)(m6502->device, 0);
change_pc(PCD);
}
m6502->pending_irq = 0;
}
@ -616,7 +602,6 @@ static void deco16_set_irq_line(m6502_Regs *m6502, int irqline, int state)
PCL = RDMEM(EAD+1);
PCH = RDMEM(EAD);
LOG(("M6502#%d takes NMI ($%04x)\n", cpunum_get_active(), PCD));
change_pc(PCD);
}
}
else
@ -646,8 +631,6 @@ static CPU_EXECUTE( deco16 )
m6502->icount = cycles;
change_pc(PCD);
do
{
UINT8 op;
@ -706,7 +689,7 @@ static CPU_SET_INFO( m6502 )
case CPUINFO_INT_INPUT_STATE + M6502_SET_OVERFLOW: m6502_set_irq_line(m6502, M6502_SET_OVERFLOW, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: m6502_set_irq_line(m6502, INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_PC: PCW = info->i; change_pc(PCD); break;
case CPUINFO_INT_PC: PCW = info->i; break;
case CPUINFO_INT_REGISTER + M6502_PC: m6502->pc.w.l = info->i; break;
case CPUINFO_INT_SP: S = info->i; break;
case CPUINFO_INT_REGISTER + M6502_S: m6502->sp.b.l = info->i; break;

11
src/emu/cpu/m6502/m6509.c
View File

@ -115,8 +115,6 @@ static WRITE8_HANDLER( m6509_write_00000 )
m6509->pc_bank.b.h2=data&0xf;
m6509->pc.w.h=m6509->pc_bank.w.h;
change_pc(PCD);
}
static WRITE8_HANDLER( m6509_write_00001 )
@ -167,8 +165,6 @@ static CPU_RESET( m6509 )
m6509->pending_irq = 0; /* nonzero if an IRQ is pending */
m6509->after_cli = 0; /* pending IRQ and last insn cleared I */
m6509->irq_callback = NULL;
change_pc(PCD);
}
static CPU_EXIT( m6509 )
@ -188,7 +184,6 @@ static CPU_SET_CONTEXT( m6509 )
{
token = src;
m6502 = token;
change_pc(PCD);
}
}
@ -211,7 +206,6 @@ INLINE void m6509_take_irq( m6509_Regs *m6502)
LOG(("M6509#%d takes IRQ ($%04x)\n", cpunum_get_active(), PCD));
/* call back the cpuintrf to let it clear the line */
if (m6502->irq_callback) (*m6502->irq_callback)(m6502->device, 0);
change_pc(PCD);
}
m6502->pending_irq = 0;
}
@ -223,8 +217,6 @@ static CPU_EXECUTE( m6509 )
m6502->icount = cycles;
change_pc(PCD);
do
{
UINT8 op;
@ -284,7 +276,6 @@ static void m6509_set_irq_line(m6509_Regs *m6509, int irqline, int state)
PCL = RDMEM(EAD);
PCH = RDMEM(EAD+1);
LOG(("M6509#%d takes NMI ($%04x)\n", cpunum_get_active(), PCD));
change_pc(PCD);
}
}
else
@ -324,7 +315,7 @@ static CPU_SET_INFO( m6509 )
case CPUINFO_INT_INPUT_STATE + M6509_SET_OVERFLOW:m6509_set_irq_line(m6509, M6509_SET_OVERFLOW, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: m6509_set_irq_line(m6509, INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_PC: PCW = info->i; change_pc(PCD); break;
case CPUINFO_INT_PC: PCW = info->i; break;
case CPUINFO_INT_REGISTER + M6509_PC: m6509->pc.w.l = info->i; break;
case CPUINFO_INT_SP: S = info->i; break;
case CPUINFO_INT_REGISTER + M6509_S: m6509->sp.b.l = info->i; break;

8
src/emu/cpu/m6502/m65ce02.c
View File

@ -122,8 +122,6 @@ static CPU_RESET( m65ce02 )
m65ce02->pending_irq = 0; /* nonzero if an IRQ is pending */
m65ce02->after_cli = 0; /* pending IRQ and last insn cleared I */
m65ce02->irq_callback = NULL;
change_pc(PCD);
}
static CPU_EXIT( m65ce02 )
@ -154,7 +152,6 @@ INLINE void m65ce02_take_irq(m65ce02_Regs *m65ce02)
LOG(("M65ce02#%d takes IRQ ($%04x)\n", cpunum_get_active(), PCD));
/* call back the cpuintrf to let it clear the line */
if (m65ce02->irq_callback) (*m65ce02->irq_callback)(m65ce02->device, 0);
change_pc(PCD);
}
m65ce02->pending_irq = 0;
}
@ -165,8 +162,6 @@ static CPU_EXECUTE( m65ce02 )
m65ce02->icount = cycles;
change_pc(PCD);
do
{
UINT8 op;
@ -223,7 +218,6 @@ static void m65ce02_set_irq_line(m65ce02_Regs *m65ce02, int irqline, int state)
PCL = RDMEM(EAD);
PCH = RDMEM(EAD+1);
LOG(("M65ce02#%d takes NMI ($%04x)\n", cpunum_get_active(), PCD));
change_pc(PCD);
}
}
else
@ -251,7 +245,7 @@ static CPU_SET_INFO( m65ce02 )
case CPUINFO_INT_INPUT_STATE + M65CE02_IRQ_STATE: m65ce02_set_irq_line( m65ce02, M65CE02_IRQ_LINE, info->i ); break;
case CPUINFO_INT_INPUT_STATE + M65CE02_NMI_STATE: m65ce02_set_irq_line( m65ce02, INPUT_LINE_NMI, info->i ); break;
case CPUINFO_INT_PC: PCW = info->i; change_pc(PCD); break;
case CPUINFO_INT_PC: PCW = info->i; break;
case CPUINFO_INT_REGISTER + M65CE02_PC: m65ce02->pc.w.l = info->i; break;
case CPUINFO_INT_SP: m65ce02->sp.b.l = info->i; break;
case CPUINFO_INT_REGISTER + M65CE02_S: m65ce02->sp.w.l = info->i; break;

2
src/emu/cpu/m6502/minc4510.h
View File

@ -52,8 +52,6 @@
#define M4510_MEM(addr) (m4510->mem[(addr)>>13]+(addr))
#define CHANGE_PC change_pc(M4510_MEM(PCD))
#define PEEK_OP() memory_decrypted_read_byte(m4510->space, M4510_MEM(PCW))
#define RDMEM(addr) memory_read_byte_8le(m4510->space, M4510_MEM(addr)); m4510->icount -= 1

2
src/emu/cpu/m6502/mincce02.h
View File

@ -53,8 +53,6 @@
#define IRQ_STATE m65ce02->irq_state
#define AFTER_CLI m65ce02->after_cli
#define CHANGE_PC change_pc(PCD)
/***************************************************************
* RDOP read an opcode
***************************************************************/

18
src/emu/cpu/m6502/ops02.h
View File

@ -67,8 +67,6 @@
#define RDMEM_ID(a) m6502->rdmem_id(m6502->space,a)
#define WRMEM_ID(a,d) m6502->wrmem_id(m6502->space,a,d)
#define CHANGE_PC change_pc(PCD)
/***************************************************************
* RDOP read an opcode
***************************************************************/
@ -104,7 +102,6 @@
RDMEM( (PCH << 8 ) | EAL) ; \
} \
PCD = EAD; \
CHANGE_PC; \
} \
}
@ -409,8 +406,7 @@
PUSH(P | F_B); \
P = (P | F_I); \
PCL = RDMEM(M6502_IRQ_VEC); \
PCH = RDMEM(M6502_IRQ_VEC+1); \
CHANGE_PC
PCH = RDMEM(M6502_IRQ_VEC+1)
/* 6502 ********************************************************
* BVC Branch if overflow clear
@ -538,8 +534,7 @@
#define JMP \
if( EAD == PPC && !m6502->pending_irq && !m6502->after_cli ) \
if( m6502->icount > 0 ) m6502->icount = 0; \
PCD = EAD; \
CHANGE_PC
PCD = EAD
/* 6502 ********************************************************
* JSR Jump to subroutine
@ -552,8 +547,7 @@
PUSH(PCH); \
PUSH(PCL); \
EAH = RDOPARG(); \
PCD = EAD; \
CHANGE_PC
PCD = EAD
/* 6502 ********************************************************
* LDA Load accumulator
@ -670,8 +664,7 @@
{ \
LOG(("M6502#%d RTI sets after_cli\n",cpunum_get_active())); \
m6502->after_cli = 1; \
} \
CHANGE_PC
}
/* 6502 ********************************************************
* RTS Return from subroutine
@ -682,8 +675,7 @@
RDMEM(SPD); \
PULL(PCL); \
PULL(PCH); \
RDMEM(PCW); PCW++; \
CHANGE_PC
RDMEM(PCW); PCW++
/* 6502 ********************************************************
* SBC Subtract with carry

7
src/emu/cpu/m6502/ops09.h
View File

@ -30,9 +30,6 @@
#define IBWH m6502->ind_bank.w.h
#define IB m6502->ind_bank.d
#undef CHANGE_PC
#define CHANGE_PC change_pc(PCD|PB)
/***************************************************************
* RDOP read an opcode
***************************************************************/
@ -177,7 +174,6 @@
EAW = PCW + (signed char)tmp; \
m6502->icount -= (PCH == EAH) ? 1 : 2; \
PCD = EAD|PB; \
CHANGE_PC; \
} \
else \
{ \
@ -197,8 +193,7 @@
PUSH(PCL); \
EAH = RDOPARG(); \
EAWH = PBWH; \
PCD = EAD; \
CHANGE_PC
PCD = EAD
/* 6510 ********************************************************
* KIL Illegal opcode

1
src/emu/cpu/m6502/ops4510.h
View File

@ -54,7 +54,6 @@
m4510->mem[5]=(m4510->high&0x2000) ? (m4510->high&0xfff)<<8:0; \
m4510->mem[6]=(m4510->high&0x4000) ? (m4510->high&0xfff)<<8:0; \
m4510->mem[7]=(m4510->high&0x8000) ? (m4510->high&0xfff)<<8:0; \
CHANGE_PC; \
m4510->icount -= 3; \
{ \
UINT8 op = RDOP(); \

7
src/emu/cpu/m6502/opsc02.h
View File

@ -149,7 +149,6 @@
RDMEM( PCW - 1 ); \
} \
PCD = EAD; \
CHANGE_PC; \
}
/* 65C02 ********************************************************
@ -252,8 +251,7 @@
PUSH(P | F_B); \
P = (P | F_I) & ~F_D; \
PCL = RDMEM(M6502_IRQ_VEC); \
PCH = RDMEM(M6502_IRQ_VEC+1); \
CHANGE_PC
PCH = RDMEM(M6502_IRQ_VEC+1);
/* 65C02 *******************************************************
@ -357,5 +355,4 @@
PUSH(PCL); \
EAH = RDOPARG(); \
EAW = PCW + (INT16)(EAW-1); \
PCD = EAD; \
CHANGE_PC
PCD = EAD;

29
src/emu/cpu/m6502/opsce02.h
View File

@ -322,7 +322,6 @@
tmp = RDOPARG(); \
EAW = PCW + (signed char)tmp; \
PCD = EAD; \
CHANGE_PC; \
} \
else \
{ \
@ -339,7 +338,6 @@
EAH = RDOPARG(); \
EAW = PCW + (short)(EAW-1); \
PCD = EAD; \
CHANGE_PC; \
} \
else \
{ \
@ -357,8 +355,7 @@
PUSH(P | F_B); \
P = (P | F_I); \
PCL = RDMEM(M6502_IRQ_VEC); \
PCH = RDMEM(M6502_IRQ_VEC+1); \
CHANGE_PC
PCH = RDMEM(M6502_IRQ_VEC+1);
/* 65ce02 ********************************************************
* BSR Branch to subroutine
@ -369,8 +366,7 @@
PUSH(PCL); \
EAH = RDOPARG(); \
EAW = PCW + (INT16)(EAW-1); \
PCD = EAD; \
CHANGE_PC
PCD = EAD;
/* 65ce02 ******************************************************
* CLC Clear carry flag
@ -537,8 +533,7 @@
* set PC to the effective address
***************************************************************/
#define JMP \
PCD = EAD; \
CHANGE_PC
PCD = EAD;
/* 65ce02 ******************************************************
* JSR Jump to subroutine
@ -550,8 +545,7 @@
PUSH(PCH); \
PUSH(PCL); \
EAH = RDOPARG(); \
PCD = EAD; \
CHANGE_PC
PCD = EAD;
/* 65ce02 ******************************************************
* JSR Jump to subroutine
@ -564,8 +558,7 @@
PUSH(PCL); \
EAH = RDOPARG(); \
PCL = RDMEM(EAD); \
PCH = RDMEM(EAD+1); \
CHANGE_PC
PCH = RDMEM(EAD+1);
/* 65ce02 ******************************************************
* JSR Jump to subroutine
@ -578,8 +571,7 @@
PUSH(PCL); \
EAH = RDOPARG(); \
PCL = RDMEM(EAD); \
PCH = RDMEM(EAD+1); \
CHANGE_PC
PCH = RDMEM(EAD+1);
/* 65ce02 ******************************************************
* LDA Load accumulator
@ -766,8 +758,7 @@
{ \
LOG(("M65ce02#%d RTI sets after_cli\n", cpunum_get_active())); \
AFTER_CLI = 1; \
} \
CHANGE_PC
}
/* 65ce02 ******************************************************
* RTS Return from subroutine
@ -776,8 +767,7 @@
#define RTS \
PULL(PCL); \
PULL(PCH); \
RDMEM(PCW); PCW++; \
CHANGE_PC
RDMEM(PCW); PCW++;
/* 65ce02 ******************************************************
* RTS imm
@ -799,8 +789,7 @@
if( IRQ_STATE != CLEAR_LINE && !(P & F_I) ) { \
LOG(("M65ce02#%d RTI sets after_cli\n", cpunum_get_active())); \
AFTER_CLI = 1; \
} \
CHANGE_PC
}
/* 65ce02 *******************************************************

3
src/emu/cpu/m6502/tdeco16.c
View File

@ -16,8 +16,7 @@
PUSH(P | F_B); \
P = (P | F_I); \
PCL = RDMEM(DECO16_IRQ_VEC+1); \
PCH = RDMEM(DECO16_IRQ_VEC); \
CHANGE_PC
PCH = RDMEM(DECO16_IRQ_VEC);
/*****************************************************************************

12
src/emu/cpu/m6800/6800ops.c
View File

@ -234,7 +234,6 @@ OP_HANDLER( bra )
UINT8 t;
IMMBYTE(t);
PC+=SIGNED(t);
CHANGE_PC(m68_state);
/* speed up busy loops */
if (t==0xfe) EAT_CYCLES;
}
@ -402,7 +401,6 @@ OP_HANDLER( pulx )
OP_HANDLER( rts )
{
PULLWORD(pPC);
CHANGE_PC(m68_state);
}
/* $3a ABX inherent ----- */
@ -419,7 +417,6 @@ OP_HANDLER( rti )
PULLBYTE(A);
PULLWORD(pX);
PULLWORD(pPC);
CHANGE_PC(m68_state);
CHECK_IRQ_LINES(m68_state); /* HJB 990417 */
}
@ -466,7 +463,6 @@ OP_HANDLER( swi )
PUSHBYTE(CC);
SEI;
PCD = RM16(m68_state, 0xfffa);
CHANGE_PC(m68_state);
}
/* $40 NEGA inherent ?**** */
@ -797,7 +793,7 @@ OP_HANDLER( tst_ix )
/* $6e JMP indexed ----- */
OP_HANDLER( jmp_ix )
{
INDEXED; PC=EA; CHANGE_PC(m68_state);
INDEXED; PC=EA;
}
/* $6f CLR indexed -0100 */
@ -946,7 +942,7 @@ OP_HANDLER( tst_ex )
/* $7e JMP extended ----- */
OP_HANDLER( jmp_ex )
{
EXTENDED; PC=EA; CHANGE_PC(m68_state); /* TS 971002 */
EXTENDED; PC=EA;
}
/* $7f CLR extended -0100 */
@ -1091,7 +1087,6 @@ OP_HANDLER( bsr )
IMMBYTE(t);
PUSHWORD(pPC);
PC += SIGNED(t);
CHANGE_PC(m68_state); /* TS 971002 */
}
/* $8e LDS immediate -**0- */
@ -1258,7 +1253,6 @@ OP_HANDLER( jsr_di )
DIRECT;
PUSHWORD(pPC);
PC = EA;
CHANGE_PC(m68_state);
}
/* $9e LDS direct -**0- */
@ -1433,7 +1427,6 @@ OP_HANDLER( jsr_ix )
INDEXED;
PUSHWORD(pPC);
PC = EA;
CHANGE_PC(m68_state);
}
/* $ae LDS indexed -**0- */
@ -1610,7 +1603,6 @@ OP_HANDLER( jsr_ex )
EXTENDED;
PUSHWORD(pPC);
PC = EA;
CHANGE_PC(m68_state);
}
/* $be LDS extended -**0- */

8
src/emu/cpu/m6800/m6800.c
View File

@ -414,8 +414,7 @@ static const UINT8 flags8d[256]= /* decrement */
#define IDXWORD(w) {INDEXED;w.d=RM16(m68_state, EAD);}
/* Macros for branch instructions */
#define CHANGE_PC(m68_state) change_pc(PCD)
#define BRANCH(f) {IMMBYTE(t);if(f){PC+=SIGNED(t);CHANGE_PC(m68_state);}}
#define BRANCH(f) {IMMBYTE(t);if(f){PC+=SIGNED(t);}}
#define NXORV ((CC&0x08)^((CC&0x02)<<2))
#define M6800_WAI 8 /* set when WAI is waiting for an interrupt */
@ -552,7 +551,6 @@ static void enter_interrupt(m68_state_t *m68_state, const char *message,UINT16 i
}
SEI;
PCD = RM16(m68_state, irq_vector );
CHANGE_PC(m68_state);
}
@ -906,7 +904,6 @@ static CPU_RESET( m6800 )
SEI; /* IRQ disabled */
PCD = RM16(m68_state, 0xfffe );
CHANGE_PC(m68_state);
m68_state->wai_state = 0;
m68_state->nmi_state = 0;
@ -957,7 +954,6 @@ static CPU_SET_CONTEXT( m6800 )
{
m68_state_t *m68_state = src;
CHANGE_PC(m68_state);
CHECK_IRQ_LINES(m68_state); /* HJB 990417 */
}
@ -2707,7 +2703,7 @@ static CPU_SET_INFO( m6800 )
case CPUINFO_INT_INPUT_STATE + M6800_TIN_LINE: set_irq_line(m68_state, M6800_TIN_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(m68_state, INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_PC: PC = info->i; CHANGE_PC(m68_state); break;
case CPUINFO_INT_PC: PC = info->i; break;
case CPUINFO_INT_REGISTER + M6800_PC: m68_state->pc.w.l = info->i; break;
case CPUINFO_INT_SP: S = info->i; break;
case CPUINFO_INT_REGISTER + M6800_S: m68_state->s.w.l = info->i; break;

3
src/emu/cpu/m68000/m68kcpu.h
View File

@ -1137,14 +1137,12 @@ INLINE void m68ki_fake_pull_32(m68ki_cpu_core *m68k)
INLINE void m68ki_jump(m68ki_cpu_core *m68k, UINT32 new_pc)
{
REG_PC = new_pc;
change_pc(REG_PC);
}
INLINE void m68ki_jump_vector(m68ki_cpu_core *m68k, UINT32 vector)
{
REG_PC = (vector<<2) + m68k->vbr;
REG_PC = m68ki_read_data_32(m68k, REG_PC);
change_pc(REG_PC);
}
@ -1166,7 +1164,6 @@ INLINE void m68ki_branch_16(m68ki_cpu_core *m68k, UINT32 offset)
INLINE void m68ki_branch_32(m68ki_cpu_core *m68k, UINT32 offset)
{
REG_PC += offset;
change_pc(REG_PC);
}

13
src/emu/cpu/m6805/6805ops.c
View File

@ -810,7 +810,6 @@ OP_HANDLER( rti )
PULLBYTE(A);
PULLBYTE(X);
PULLWORD(pPC);
change_pc(PC);
#if IRQ_LEVEL_DETECT
if( m6805.irq_state != CLEAR_LINE && (CC & IFLAG) == 0 )
m6805.pending_interrupts |= M6805_INT_IRQ;
@ -821,7 +820,6 @@ OP_HANDLER( rti )
OP_HANDLER( rts )
{
PULLWORD(pPC);
change_pc(PC);
}
/* $82 ILLEGAL */
@ -835,7 +833,6 @@ OP_HANDLER( swi )
PUSHBYTE(m6805.cc);
SEI;
if(SUBTYPE==SUBTYPE_HD63705) RM16( 0x1ffa, &pPC ); else RM16( 0xfffc, &pPC );
change_pc(PC);
}
/* $84 ILLEGAL */
@ -1174,7 +1171,6 @@ OP_HANDLER( jmp_di )
{
DIRECT;
PC = EA;
change_pc(PC);
}
/* $bd JSR direct ---- */
@ -1183,7 +1179,6 @@ OP_HANDLER( jsr_di )
DIRECT;
PUSHWORD(m6805.pc);
PC = EA;
change_pc(PC);
}
/* $be LDX direct -**- */
@ -1331,7 +1326,6 @@ OP_HANDLER( jmp_ex )
{
EXTENDED;
PC = EA;
change_pc(PC);
}
/* $cd JSR extended ---- */
@ -1340,7 +1334,6 @@ OP_HANDLER( jsr_ex )
EXTENDED;
PUSHWORD(m6805.pc);
PC = EA;
change_pc(PC);
}
/* $ce LDX extended -**- */
@ -1488,7 +1481,6 @@ OP_HANDLER( jmp_ix2 )
{
INDEXED2;
PC = EA;
change_pc(PC);
}
/* $dd JSR indexed, 2 byte offset ---- */
@ -1497,7 +1489,6 @@ OP_HANDLER( jsr_ix2 )
INDEXED2;
PUSHWORD(m6805.pc);
PC = EA;
change_pc(PC);
}
/* $de LDX indexed, 2 byte offset -**- */
@ -1645,7 +1636,6 @@ OP_HANDLER( jmp_ix1 )
{
INDEXED1;
PC = EA;
change_pc(PC);
}
/* $ed JSR indexed, 1 byte offset ---- */
@ -1654,7 +1644,6 @@ OP_HANDLER( jsr_ix1 )
INDEXED1;
PUSHWORD(m6805.pc);
PC = EA;
change_pc(PC);
}
/* $ee LDX indexed, 1 byte offset -**- */
@ -1802,7 +1791,6 @@ OP_HANDLER( jmp_ix )
{
INDEXED;
PC = EA;
change_pc(PC);
}
/* $fd JSR indexed ---- */
@ -1811,7 +1799,6 @@ OP_HANDLER( jsr_ix )
INDEXED;
PUSHWORD(m6805.pc);
PC = EA;
change_pc(PC);
}
/* $fe LDX indexed -**- */

17
src/emu/cpu/m6805/m6805.c
View File

@ -201,7 +201,7 @@ static const UINT8 flags8d[256]= /* decrement */
#define IDX1BYTE(b) {INDEXED1;b=RM(EAD);}
#define IDX2BYTE(b) {INDEXED2;b=RM(EAD);}
/* Macros for branch instructions */
#define BRANCH(f) { UINT8 t; IMMBYTE(t); if(f) { PC+=SIGNED(t); change_pc(PC); if (t==0xfe) { /* speed up busy loops */ if(m6805_ICount > 0) m6805_ICount = 0; } } }
#define BRANCH(f) { UINT8 t; IMMBYTE(t); if(f) { PC+=SIGNED(t); if (t==0xfe) { /* speed up busy loops */ if(m6805_ICount > 0) m6805_ICount = 0; } } }
/* what they say it is ... */
static const unsigned char cycles1[] =
@ -298,13 +298,11 @@ static void m68705_Interrupt(void)
{
m6805.pending_interrupts &= ~(1<<M68705_IRQ_LINE);
RM16( 0xfffa, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<M68705_INT_TIMER))!=0)
{
m6805.pending_interrupts &= ~(1<<M68705_INT_TIMER);
RM16( 0xfff8, &pPC);
change_pc(PC);
}
}
m6805_ICount -= 11;
@ -332,7 +330,6 @@ static void Interrupt(void)
(*m6805.irq_callback)(m6805.device, 0);
RM16( 0x1ffc, &pPC);
change_pc(PC);
m6805.pending_interrupts &= ~(1<<HD63705_INT_NMI);
m6805_ICount -= 11;
@ -370,56 +367,47 @@ static void Interrupt(void)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ1);
RM16( 0x1ff8, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_IRQ2))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ2);
RM16( 0x1fec, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_ADCONV))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_ADCONV);
RM16( 0x1fea, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER1))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER1);
RM16( 0x1ff6, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER2))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER2);
RM16( 0x1ff4, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER3))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER3);
RM16( 0x1ff2, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_PCI))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_PCI);
RM16( 0x1ff0, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_SCI))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_SCI);
RM16( 0x1fee, &pPC);
change_pc(PC);
}
}
else
#endif
{
RM16( 0xffff - 5, &pPC );
change_pc(PC);
}
} // CC & IFLAG
@ -464,7 +452,6 @@ static CPU_RESET( m6805 )
/* IRQ disabled */
SEI;
RM16( 0xfffe , &pPC );
change_pc(PC);
}
static CPU_EXIT( m6805 )
@ -889,7 +876,7 @@ static CPU_SET_INFO( m6805 )
case CPUINFO_INT_REGISTER + M6805_A: A = info->i; break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + M6805_PC: PC = info->i; change_pc(PC); break;
case CPUINFO_INT_REGISTER + M6805_PC: PC = info->i; break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + M6805_S: S = SP_ADJUST(info->i); break;
case CPUINFO_INT_REGISTER + M6805_X: X = info->i; break;

25
src/emu/cpu/m6809/6809ops.c
View File

@ -150,7 +150,6 @@ OP_HANDLER( jmp_di )
{
DIRECT;
PCD = EAD;
CHANGE_PC;
}
/* $0F CLR direct -0100 */
@ -196,7 +195,6 @@ OP_HANDLER( lbra )
{
IMMWORD(EAP);
PC += EA;
CHANGE_PC;
if ( EA == 0xfffd ) /* EHC 980508 speed up busy loop */
if ( m68_state->icount > 0)
@ -209,7 +207,6 @@ OP_HANDLER( lbsr )
IMMWORD(EAP);
PUSHWORD(pPC);
PC += EA;
CHANGE_PC;
}
/* $18 ILLEGAL */
@ -307,7 +304,7 @@ OP_HANDLER( exg )
case 2: Y = t2; break;
case 3: U = t2; break;
case 4: S = t2; break;
case 5: PC = t2; CHANGE_PC; break;
case 5: PC = t2; break;
case 8: A = t2; break;
case 9: B = t2; break;
case 10: CC = t2; break;
@ -319,7 +316,7 @@ OP_HANDLER( exg )
case 2: Y = t1; break;
case 3: U = t1; break;
case 4: S = t1; break;
case 5: PC = t1; CHANGE_PC; break;
case 5: PC = t1; break;
case 8: A = t1; break;
case 9: B = t1; break;
case 10: CC = t1; break;
@ -361,7 +358,7 @@ OP_HANDLER( tfr )
case 2: Y = t; break;
case 3: U = t; break;
case 4: S = t; break;
case 5: PC = t; CHANGE_PC; break;
case 5: PC = t; break;
case 8: A = t; break;
case 9: B = t; break;
case 10: CC = t; break;
@ -375,7 +372,6 @@ OP_HANDLER( bra )
UINT8 t;
IMMBYTE(t);
PC += SIGNED(t);
CHANGE_PC;
/* JB 970823 - speed up busy loops */
if( t == 0xfe )
if( m68_state->icount > 0 ) m68_state->icount = 0;
@ -622,7 +618,7 @@ OP_HANDLER( puls )
if( t&0x10 ) { PULLWORD(XD); m68_state->icount -= 2; }
if( t&0x20 ) { PULLWORD(YD); m68_state->icount -= 2; }
if( t&0x40 ) { PULLWORD(UD); m68_state->icount -= 2; }
if( t&0x80 ) { PULLWORD(PCD); CHANGE_PC; m68_state->icount -= 2; }
if( t&0x80 ) { PULLWORD(PCD); m68_state->icount -= 2; }
/* HJB 990225: moved check after all PULLs */
if( t&0x01 ) { check_irq_lines(m68_state); }
@ -655,7 +651,7 @@ OP_HANDLER( pulu )
if( t&0x10 ) { PULUWORD(XD); m68_state->icount -= 2; }
if( t&0x20 ) { PULUWORD(YD); m68_state->icount -= 2; }
if( t&0x40 ) { PULUWORD(SD); m68_state->icount -= 2; }
if( t&0x80 ) { PULUWORD(PCD); CHANGE_PC; m68_state->icount -= 2; }
if( t&0x80 ) { PULUWORD(PCD); m68_state->icount -= 2; }
/* HJB 990225: moved check after all PULLs */
if( t&0x01 ) { check_irq_lines(m68_state); }
@ -667,7 +663,6 @@ OP_HANDLER( pulu )
OP_HANDLER( rts )
{
PULLWORD(PCD);
CHANGE_PC;
}
/* $3A ABX inherent ----- */
@ -693,7 +688,6 @@ OP_HANDLER( rti )
PULLWORD(UD);
}
PULLWORD(PCD);
CHANGE_PC;
check_irq_lines(m68_state); /* HJB 990116 */
}
@ -749,7 +743,6 @@ OP_HANDLER( swi )
PUSHBYTE(CC);
CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */
PCD=RM16(m68_state, 0xfffa);
CHANGE_PC;
}
/* $103F SWI2 absolute indirect ----- */
@ -765,7 +758,6 @@ OP_HANDLER( swi2 )
PUSHBYTE(A);
PUSHBYTE(CC);
PCD = RM16(m68_state, 0xfff4);
CHANGE_PC;
}
/* $113F SWI3 absolute indirect ----- */
@ -781,7 +773,6 @@ OP_HANDLER( swi3 )
PUSHBYTE(A);
PUSHBYTE(CC);
PCD = RM16(m68_state, 0xfff2);
CHANGE_PC;
}
/* $40 NEGA inherent ?**** */
@ -1134,7 +1125,6 @@ OP_HANDLER( jmp_ix )
{
fetch_effective_address(m68_state);
PCD = EAD;
CHANGE_PC;
}
/* $6F CLR indexed -0100 */
@ -1249,7 +1239,6 @@ OP_HANDLER( jmp_ex )
{
EXTENDED;
PCD = EAD;
CHANGE_PC;
}
/* $7F CLR extended -0100 */
@ -1455,7 +1444,6 @@ OP_HANDLER( bsr )
IMMBYTE(t);
PUSHWORD(pPC);
PC += SIGNED(t);
CHANGE_PC;
}
/* $8E LDX (LDY) immediate -**0- */
@ -1686,7 +1674,6 @@ OP_HANDLER( jsr_di )
DIRECT;
PUSHWORD(pPC);
PCD = EAD;
CHANGE_PC;
}
/* $9E LDX (LDY) direct -**0- */
@ -1923,7 +1910,6 @@ OP_HANDLER( jsr_ix )
fetch_effective_address(m68_state);
PUSHWORD(pPC);
PCD = EAD;
CHANGE_PC;
}
/* $aE LDX (LDY) indexed -**0- */
@ -2153,7 +2139,6 @@ OP_HANDLER( jsr_ex )
EXTENDED;
PUSHWORD(pPC);
PCD = EAD;
CHANGE_PC;
}
/* $bE LDX (LDY) extended -**0- */

10
src/emu/cpu/m6809/m6809.c
View File

@ -155,8 +155,6 @@ INLINE void fetch_effective_address( m68_state_t *m68_state );
#define EAD m68_state->ea.d
#define EAP m68_state->ea
#define CHANGE_PC change_pc(PCD)
#define M6809_CWAI 8 /* set when CWAI is waiting for an interrupt */
#define M6809_SYNC 16 /* set when SYNC is waiting for an interrupt */
#define M6809_LDS 32 /* set when LDS occured at least once */
@ -269,7 +267,6 @@ INLINE void fetch_effective_address( m68_state_t *m68_state );
if( f ) \
{ \
PC += SIGNED(t); \
CHANGE_PC; \
} \
}
@ -280,7 +277,6 @@ INLINE void fetch_effective_address( m68_state_t *m68_state );
{ \
m68_state->icount -= 1; \
PC += t.w.l; \
CHANGE_PC; \
} \
}
@ -326,7 +322,6 @@ static void check_irq_lines(m68_state_t *m68_state)
}
CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */
PCD=RM16(m68_state, 0xfff6);
CHANGE_PC;
(void)(*m68_state->irq_callback)(m68_state->device, M6809_FIRQ_LINE);
}
else
@ -354,7 +349,6 @@ static void check_irq_lines(m68_state_t *m68_state)
}
CC |= CC_II; /* inhibit IRQ */
PCD=RM16(m68_state, 0xfff8);
CHANGE_PC;
(void)(*m68_state->irq_callback)(m68_state->device, M6809_IRQ_LINE);
}
}
@ -431,7 +425,6 @@ static CPU_RESET( m6809 )
CC |= CC_IF; /* FIRQ disabled */
PCD = RM16(m68_state, 0xfffe);
CHANGE_PC;
UpdateState(m68_state);
}
@ -477,7 +470,6 @@ static void set_irq_line(m68_state_t *m68_state, int irqline, int state)
}
CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */
PCD = RM16(m68_state, 0xfffc);
CHANGE_PC;
}
else if (irqline < 2)
{
@ -1093,7 +1085,7 @@ static CPU_SET_INFO( m6809 )
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(m68_state, INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + M6809_PC: PC = info->i; CHANGE_PC; break;
case CPUINFO_INT_REGISTER + M6809_PC: PC = info->i; break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + M6809_S: S = info->i; break;
case CPUINFO_INT_REGISTER + M6809_CC: CC = info->i; check_irq_lines(m68_state); break;

12
src/emu/cpu/mb86233/mb86233.c
View File

@ -109,7 +109,6 @@ static CPU_SET_CONTEXT( mb86233 )
/* copy the context */
if (src)
mb86233 = *(MB86233_REGS *)src;
change_pc(GETPC());
}
@ -1440,7 +1439,6 @@ static CPU_EXECUTE( mb86233 )
{
case 0x00: /* BRIF <addr> */
GETPC() = data - 1;
change_pc( GETPC() );
break;
case 0x02: /* BRIF indirect */
@ -1454,14 +1452,12 @@ static CPU_EXECUTE( mb86233 )
break;
GETPC() = data;
change_pc( GETPC() );
break;
case 0x04: /* BSIF <addr> */
GETPCS()[GETPCSP()] = GETPC();
GETPCSP()++;
GETPC() = data - 1;
change_pc( GETPC() );
break;
case 0x06: /* BSIF indirect */
@ -1477,13 +1473,11 @@ static CPU_EXECUTE( mb86233 )
break;
GETPC() = data;
change_pc( GETPC() );
break;
case 0x0a: /* RTIF */
--GETPCSP();
GETPC() = GETPCS()[GETPCSP()];
change_pc( GETPC() );
break;
case 0x0c: /* LDIF */
@ -1527,14 +1521,12 @@ static CPU_EXECUTE( mb86233 )
break;
GETPC() = data;
change_pc( GETPC() );
break;
case 0x04: /* BSUL <addr> */
GETPCS()[GETPCSP()] = GETPC();
GETPCSP()++;
GETPC() = data - 1;
change_pc( GETPC() );
break;
case 0x06: /* BSUL indirect */
@ -1550,13 +1542,11 @@ static CPU_EXECUTE( mb86233 )
break;
GETPC() = data;
change_pc( GETPC() );
break;
case 0x0a: /* RTUL */
--GETPCSP();
GETPC() = GETPCS()[GETPCSP()];
change_pc( GETPC() );
break;
case 0x0c: /* LDUL */
@ -1621,7 +1611,7 @@ static CPU_SET_INFO( mb86233 )
switch (state)
{
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + MB86233_PC: GETPC() = info->i; change_pc(GETPC()); break;
case CPUINFO_INT_REGISTER + MB86233_PC: GETPC() = info->i; break;
case CPUINFO_INT_REGISTER + MB86233_A: GETA().u = info->i; break;
case CPUINFO_INT_REGISTER + MB86233_B: GETB().u = info->i; break;
case CPUINFO_INT_REGISTER + MB86233_P: GETP().u = info->i; break;

9
src/emu/cpu/mb88xx/mb88xx.c
View File

@ -114,7 +114,6 @@ static CPU_SET_CONTEXT( mb88 )
/* copy the context */
if (src)
mb88 = *(mb88Regs *)src;
change_pc(GETPC());
}
/***************************************************************************
@ -225,7 +224,6 @@ static void update_pio( void )
mb88.PC = 0x02;
mb88.PA = 0x00;
mb88.st = 1;
change_pc(GETPC());
mb88.pending_interrupt = 0;
@ -533,7 +531,6 @@ static CPU_EXECUTE( mb88 )
mb88.SI = ( mb88.SI - 1 ) & 3;
mb88.PC = mb88.SP[mb88.SI] & 0x3f;
mb88.PA = mb88.SP[mb88.SI] >> 6;
change_pc(GETPC());
mb88.st = 1;
break;
@ -583,7 +580,6 @@ static CPU_EXECUTE( mb88 )
mb88.st = (mb88.SP[mb88.SI] >> 13)&1;
mb88.zf = (mb88.SP[mb88.SI] >> 14)&1;
mb88.cf = (mb88.SP[mb88.SI] >> 15)&1;
change_pc(GETPC());
break;
case 0x3d: /* jpa imm ZCS:..x */
@ -664,8 +660,6 @@ static CPU_EXECUTE( mb88 )
mb88.SI = ( mb88.SI + 1 ) & 3;
mb88.PC = arg & 0x3f;
mb88.PA = ( ( opcode & 7 ) << 2 ) | ( arg >> 6 );
change_pc(GETPC());
}
mb88.st = 1;
break;
@ -679,7 +673,6 @@ static CPU_EXECUTE( mb88 )
{
mb88.PC = arg & 0x3f;
mb88.PA = ( ( opcode & 7 ) << 2 ) | ( arg >> 6 );
change_pc(GETPC());
}
mb88.st = 1;
break;
@ -740,7 +733,6 @@ static CPU_EXECUTE( mb88 )
if ( TEST_ST() )
{
mb88.PC = opcode & 0x3f;
change_pc(GETPC());
}
mb88.st = 1;
break;
@ -770,7 +762,6 @@ static CPU_SET_INFO( mb88 )
case CPUINFO_INT_PC:
mb88.PC = info->i & 0x3f;
mb88.PA = (info->i >> 6) & 0x1f;
change_pc(GETPC());
break;
case CPUINFO_INT_REGISTER + MB88_PC: mb88.PC = info->i; break;
case CPUINFO_INT_REGISTER + MB88_PA: mb88.PA = info->i; break;

1
src/emu/cpu/mc68hc11/hc11ops.c
View File

@ -30,7 +30,6 @@ INLINE void CYCLES(int cycles)
INLINE void SET_PC(int pc)
{
hc11.pc = pc;
change_pc(hc11.pc);
}
INLINE void PUSH8(UINT8 value)

3
src/emu/cpu/mc68hc11/mc68hc11.c
View File

@ -379,7 +379,6 @@ static CPU_SET_CONTEXT( hc11 )
if (src) {
hc11 = *(HC11_REGS*)src;
}
change_pc(hc11.pc);
}
static CPU_EXECUTE( hc11 )
@ -408,7 +407,7 @@ static CPU_SET_INFO( mc68hc11 )
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_PC: hc11.pc = info->i; break;
case CPUINFO_INT_REGISTER + HC11_PC: hc11.pc = info->i; change_pc(hc11.pc); break;
case CPUINFO_INT_REGISTER + HC11_PC: hc11.pc = info->i; break;
case CPUINFO_INT_REGISTER + HC11_SP: hc11.sp = info->i; break;
case CPUINFO_INT_REGISTER + HC11_A: hc11.d.d8.a = info->i; break;
case CPUINFO_INT_REGISTER + HC11_B: hc11.d.d8.b = info->i; break;

9
src/emu/cpu/mcs48/mcs48.c
View File

@ -245,7 +245,6 @@ INLINE void pull_pc_psw(mcs48_state *mcs48)
PSW = (mcs48->pc.b.h & 0xf0) | 0x08 | sp;
mcs48->pc.b.h &= 0x0f;
update_regptr(mcs48);
change_pc(PC);
}
@ -260,7 +259,6 @@ INLINE void pull_pc(mcs48_state *mcs48)
mcs48->pc.b.l = ram_r(8 + 2*sp);
mcs48->pc.b.h = ram_r(9 + 2*sp) & 0x0f;
PSW = (PSW & 0xf0) | 0x08 | sp;
change_pc(PC);
}
@ -307,7 +305,6 @@ INLINE void execute_jmp(mcs48_state *mcs48, UINT16 address)
{
UINT16 a11 = (mcs48->irq_in_progress) ? 0 : mcs48->a11;
PC = address | a11;
change_pc(PC);
}
@ -334,7 +331,6 @@ INLINE void execute_jcc(mcs48_state *mcs48, UINT8 result)
if (result != 0)
{
PC = ((PC - 1) & 0xf00) | offset;
change_pc(PC);
}
else
ADJUST_CYCLES;
@ -499,7 +495,7 @@ OPHANDLER( jmp_4 ) { execute_jmp(mcs48, argument_fetch(mcs48, PC) | 0x400); }
OPHANDLER( jmp_5 ) { execute_jmp(mcs48, argument_fetch(mcs48, PC) | 0x500); }
OPHANDLER( jmp_6 ) { execute_jmp(mcs48, argument_fetch(mcs48, PC) | 0x600); }
OPHANDLER( jmp_7 ) { execute_jmp(mcs48, argument_fetch(mcs48, PC) | 0x700); }
OPHANDLER( jmpp_xa ) { PC &= 0xf00; PC |= program_r(PC | A); change_pc(PC); }
OPHANDLER( jmpp_xa ) { PC &= 0xf00; PC |= program_r(PC | A); }
OPHANDLER( jnc ) { execute_jcc(mcs48, (PSW & C_FLAG) == 0); }
OPHANDLER( jni ) { execute_jcc(mcs48, mcs48->irq_state != 0); }
@ -847,7 +843,6 @@ static void check_irqs(mcs48_state *mcs48)
/* transfer to location 0x03 */
push_pc_psw(mcs48);
PC = 0x03;
change_pc(0x03);
mcs48->inst_cycles += 2;
/* indicate we took the external IRQ */
@ -863,7 +858,6 @@ static void check_irqs(mcs48_state *mcs48)
/* transfer to location 0x07 */
push_pc_psw(mcs48);
PC = 0x07;
change_pc(0x07);
mcs48->inst_cycles += 2;
/* timer overflow flip-flop is reset once taken */
@ -926,7 +920,6 @@ static CPU_EXECUTE( mcs48 )
unsigned opcode;
update_regptr(mcs48);
change_pc(PC);
mcs48->icount = cycles;

6
src/emu/cpu/mcs51/mcs51.c
View File

@ -308,9 +308,6 @@ struct _mcs51_state_t
MACROS
***************************************************************************/
#undef change_pc
#define change_pc(x)
/* Read Opcode/Opcode Arguments from Program Code */
#define ROP(pc) memory_decrypted_read_byte(mcs51_state->program, pc)
#define ROP_ARG(pc) memory_raw_read_byte(mcs51_state->program, pc)
@ -771,7 +768,6 @@ INLINE void pop_pc(mcs51_state_t *mcs51_state)
PC = (IRAM_IR(tmpSP--) & 0xff) << 8; //Store hi byte to PC (must use IRAM_IR to access stack pointing above 128 bytes)
PC = PC | IRAM_IR(tmpSP--); //Store lo byte to PC (must use IRAM_IR to access stack pointing above 128 bytes)
SP = tmpSP; //Decrement Stack Pointer
change_pc(PC);
}
//Set the PSW Parity Flag
@ -1720,7 +1716,6 @@ static void check_irqs(mcs51_state_t *mcs51_state)
//Save current pc to stack, set pc to new interrupt vector
push_pc(mcs51_state);
PC = int_vec;
change_pc(PC);
/* interrupts take 24 cycles */
mcs51_state->inst_cycles += 2;
@ -1909,7 +1904,6 @@ static CPU_EXECUTE( mcs51 )
mcs51_state_t *mcs51_state = device->token;
UINT8 op;
change_pc(PC);
update_ptrs(mcs51_state);
mcs51_state->icount = cycles;

19
src/emu/cpu/mcs51/mcs51ops.c
View File

@ -11,7 +11,6 @@ OPHANDLER( acall )
PUSH_PC(); //Save PC to the stack
//Thanks Gerrit for help with this! :)
PC = (PC & 0xf800) | ((r & 0xe0) << 3) | addr;
change_pc(PC);
}
//ADD A, #data /* 1: 0010 0100 */
@ -94,7 +93,6 @@ OPHANDLER( ajmp )
UINT8 addr = ROP_ARG(PC++); //Grab code address byte
//Thanks Gerrit for help with this! :)
PC = (PC & 0xf800) | ((r & 0xe0) << 3) | addr;
change_pc(PC);
}
//ANL data addr, A /* 1: 0101 0010 */
@ -171,7 +169,6 @@ OPHANDLER( cjne_a_byte )
if(ACC != data) //Jump if values are not equal
{
PC = PC + rel_addr;
change_pc(PC);
}
//Set carry flag to 1 if 1st compare value is < 2nd compare value
@ -188,7 +185,6 @@ OPHANDLER( cjne_a_mem )
if(ACC != data) //Jump if values are not equal
{
PC = PC + rel_addr;
change_pc(PC);
}
//Set carry flag to 1 if 1st compare value is < 2nd compare value
@ -205,7 +201,6 @@ OPHANDLER( cjne_ir_byte )
if(srcdata != data) //Jump if values are not equal
{
PC = PC + rel_addr;
change_pc(PC);
}
//Set carry flag to 1 if 1st compare value is < 2nd compare value
@ -222,7 +217,6 @@ OPHANDLER( cjne_r_byte )
if(srcdata != data) //Jump if values are not equal
{
PC = PC + rel_addr;
change_pc(PC);
}
//Set carry flag to 1 if 1st compare value is < 2nd compare value
@ -350,7 +344,6 @@ OPHANDLER( djnz_mem )
if(IRAM_R(addr) != 0) //Branch if contents of data address is not 0
{
PC = PC + rel_addr;
change_pc(PC);
}
}
@ -362,7 +355,6 @@ OPHANDLER( djnz_r )
if(R_REG(r) != 0) //Branch if contents of R0 - R7 is not 0
{
PC = PC + rel_addr;
change_pc(PC);
}
}
@ -409,7 +401,6 @@ OPHANDLER( jb )
if(BIT_R(addr)) //If bit set at specified bit address, jump
{
PC = PC + rel_addr;
change_pc(PC);
}
}
@ -421,7 +412,6 @@ OPHANDLER( jbc )
if(BIT_R(addr)) { //If bit set at specified bit address, jump
PC = PC + rel_addr;
BIT_W(addr,0); //Clear Bit also
change_pc(PC);
}
}
@ -432,7 +422,6 @@ OPHANDLER( jc )
if(GET_CY) //Jump if Carry Flag Set
{
PC = PC + rel_addr;
change_pc(PC);
}
}
@ -440,7 +429,6 @@ OPHANDLER( jc )
OPHANDLER( jmp_iadptr )
{
PC = ACC + DPTR;
change_pc(PC);
}
//JNB bit addr, code addr /* 1: 0011 0000 */
@ -451,7 +439,6 @@ OPHANDLER( jnb )
if(!BIT_R(addr)) //If bit NOT set at specified bit address, jump
{
PC = PC + rel_addr;
change_pc(PC);
}
}
@ -462,7 +449,6 @@ OPHANDLER( jnc )
if(!GET_CY) //Jump if Carry Flag not set
{
PC = PC + rel_addr;
change_pc(PC);
}
}
@ -473,7 +459,6 @@ OPHANDLER( jnz )
if(ACC != 0) //Branch if ACC is not 0
{
PC = PC+rel_addr;
change_pc(PC);
}
}
@ -484,7 +469,6 @@ OPHANDLER( jz )
if(ACC == 0) //Branch if ACC is 0
{
PC = PC+rel_addr;
change_pc(PC);
}
}
@ -496,7 +480,6 @@ OPHANDLER( lcall )
addr_lo = ROP_ARG(PC++);
PUSH_PC();
PC = (UINT16)((addr_hi<<8) | addr_lo);
change_pc(PC);
}
//LJMP code addr /* 1: 0000 0010 */
@ -506,7 +489,6 @@ OPHANDLER( ljmp )
addr_hi = ROP_ARG(PC++);
addr_lo = ROP_ARG(PC++);
PC = (UINT16)((addr_hi<<8) | addr_lo);
change_pc(PC);
}
//MOV A, #data /* 1: 0111 0100 */
@ -858,7 +840,6 @@ OPHANDLER( sjmp )
{
INT8 rel_addr = ROP_ARG(PC++); //Grab relative code address
PC = PC + rel_addr; //Update PC
change_pc(PC);
}
//SUBB A, #data /* 1: 1001 0100 */

1
src/emu/cpu/minx/minx.c
View File

@ -130,7 +130,6 @@ static CPU_RESET( minx )
regs.halted = regs.interrupt_pending = 0;
regs.PC = rd16( 0 );
change_pc( regs.PC );
}

1
src/emu/cpu/minx/minxfunc.h
View File

@ -331,7 +331,6 @@ INLINE void JMP( UINT16 arg )
{
regs.V = regs.U;
regs.PC = arg;
change_pc( GET_MINX_PC );
}

1
src/emu/cpu/mips/mips3.c
View File

@ -318,7 +318,6 @@ static int update_pcbase(void)
return 0;
}
mips3.pcbase = entry & ~0xfff;
change_pc(mips3.pcbase);
return 1;
}

7
src/emu/cpu/mips/psx.c
View File

@ -1358,7 +1358,6 @@ INLINE void mips_commit_delayed_load( psxcpu_state *psxcpu )
static void mips_set_pc( psxcpu_state *psxcpu, unsigned pc )
{
psxcpu->pc = pc;
change_pc( pc );
}
static void mips_fetch_next_op( psxcpu_state *psxcpu )
@ -1367,9 +1366,7 @@ static void mips_fetch_next_op( psxcpu_state *psxcpu )
{
UINT32 safepc = psxcpu->delayv & ~psxcpu->bad_word_address_mask;
change_pc( safepc );
psxcpu->op = memory_decrypted_read_dword( psxcpu->program, safepc );
change_pc( psxcpu->pc );
}
else
{
@ -1390,10 +1387,6 @@ INLINE int mips_advance_pc( psxcpu_state *psxcpu )
mips_load_bad_address( psxcpu, psxcpu->pc );
return 0;
}
else
{
change_pc( psxcpu->pc );
}
}
else if( psxcpu->delayr == PSXCPU_DELAYR_NOTPC )
{

6
src/emu/cpu/mips/r3000.c
View File

@ -248,9 +248,6 @@ INLINE void generate_exception(r3000_state *r3000, int exception)
r3000->pc += 0x80;
else
r3000->pc += 0x180;
/* swap to the new space */
change_pc(r3000->pc);
}
@ -354,7 +351,6 @@ static void r3000_reset(r3000_state *r3000, int bigendian)
r3000->nextpc = ~0;
r3000->cpr[0][COP0_PRId] = 0x0200;
r3000->cpr[0][COP0_Status] = 0x0000;
change_pc(r3000->pc);
}
static CPU_RESET( r3000be )
@ -702,7 +698,6 @@ static CPU_EXECUTE( r3000 )
r3000->icount = cycles;
r3000->icount -= r3000->interrupt_cycles;
r3000->interrupt_cycles = 0;
change_pc(r3000->pc);
/* check for IRQs */
check_irqs(r3000);
@ -726,7 +721,6 @@ static CPU_EXECUTE( r3000 )
{
r3000->pc = r3000->nextpc;
r3000->nextpc = ~0;
change_pc(r3000->pc);
}
else
r3000->pc += 4;

2
src/emu/cpu/nec/nec.h
View File

@ -88,7 +88,7 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,IXH,IXL,IYH,IYL } BREGS;
/************************************************************************/
#define CHANGE_PC do { EMPTY_PREFETCH(); change_pc((nec_state->sregs[PS]<<4) + nec_state->ip); } while (0)
#define CHANGE_PC do { EMPTY_PREFETCH(); } while (0)
#define SegBase(Seg) (nec_state->sregs[Seg] << 4)

2
src/emu/cpu/powerpc/ppc.c
View File

@ -1726,8 +1726,6 @@ static CPU_SET_CONTEXT( ppc )
/* copy the context */
if (src)
ppc = *(PPC_REGS *)src;
change_pc(ppc.pc);
}
/**************************************************************************

10
src/emu/cpu/powerpc/ppc403.c
View File

@ -145,7 +145,6 @@ static CPU_RESET( ppc403 )
ppc.pc = ppc.npc = 0xfffffffc;
ppc_set_msr(0);
change_pc(ppc.pc);
}
static CPU_EXECUTE( ppc403 )
@ -153,7 +152,6 @@ static CPU_EXECUTE( ppc403 )
UINT32 fit_trigger_cycle;
ppc_icount = cycles;
ppc_tb_base_icount = cycles;
change_pc(ppc.npc);
fit_trigger_cycle = 0x7fffffff;
@ -270,7 +268,6 @@ void ppc403_exception(int exception)
ppc_set_msr(msr);
ppc.npc = EVPR | 0x0500;
change_pc(ppc.npc);
ppc.interrupt_pending &= ~0x1;
}
@ -295,7 +292,6 @@ void ppc403_exception(int exception)
ppc.npc = 0xfff00000 | 0x0700;
else
ppc.npc = EVPR | 0x0700;
change_pc(ppc.npc);
break;
}
@ -317,7 +313,6 @@ void ppc403_exception(int exception)
ppc.npc = 0xfff00000 | 0x0c00;
else
ppc.npc = EVPR | 0x0c00;
change_pc(ppc.npc);
break;
}
@ -337,7 +332,6 @@ void ppc403_exception(int exception)
ppc_set_msr(msr);
ppc.npc = EVPR | 0x1000;
change_pc(ppc.npc);
ppc.tsr |= 0x08000000; // PIT interrupt
ppc.interrupt_pending &= ~0x2;
@ -361,7 +355,6 @@ void ppc403_exception(int exception)
ppc_set_msr(msr);
ppc.npc = EVPR | 0x1010;
change_pc(ppc.npc);
ppc.interrupt_pending &= ~0x4;
}
break;
@ -382,7 +375,6 @@ void ppc403_exception(int exception)
ppc_set_msr(msr);
ppc.npc = EVPR | 0x1020;
change_pc(ppc.npc);
break;
}
@ -402,7 +394,6 @@ void ppc403_exception(int exception)
EXISR |= 0x80000000;
ppc.npc = EVPR | 0x100;
change_pc(ppc.npc);
break;
}
@ -531,7 +522,6 @@ static void ppc_rfci(UINT32 op)
msr = ppc.srr3;
ppc_set_msr( msr );
change_pc(ppc.npc);
}
#endif

8
src/emu/cpu/powerpc/ppc602.c
View File

@ -66,7 +66,6 @@ void ppc602_exception(int exception)
ppc.npc = ppc.ibr | 0x0500;
ppc.interrupt_pending &= ~0x1;
change_pc(ppc.npc);
}
break;
@ -90,7 +89,6 @@ void ppc602_exception(int exception)
ppc.npc = ppc.ibr | 0x0900;
ppc.interrupt_pending &= ~0x2;
change_pc(ppc.npc);
}
break;
@ -111,7 +109,6 @@ void ppc602_exception(int exception)
ppc.npc = 0xfff00000 | 0x0700;
else
ppc.npc = ppc.ibr | 0x0700;
change_pc(ppc.npc);
}
break;
@ -132,7 +129,6 @@ void ppc602_exception(int exception)
ppc.npc = 0xfff00000 | 0x0c00;
else
ppc.npc = ppc.ibr | 0x0c00;
change_pc(ppc.npc);
}
break;
@ -156,7 +152,6 @@ void ppc602_exception(int exception)
ppc.npc = ppc.ibr | 0x1400;
ppc.interrupt_pending &= ~0x4;
change_pc(ppc.npc);
}
break;
@ -212,7 +207,6 @@ static CPU_RESET( ppc602 )
ppc.pc = ppc.npc = 0xfff00100;
ppc_set_msr(0x40);
change_pc(ppc.pc);
ppc.hid0 = 1;
@ -237,8 +231,6 @@ static CPU_EXECUTE( ppc602 )
ppc_dec_trigger_cycle = 0x7fffffff;
}
change_pc(ppc.npc);
// MinGW's optimizer kills setjmp()/longjmp()
SETJMP_GNUC_PROTECT();

10
src/emu/cpu/powerpc/ppc603.c
View File

@ -22,7 +22,6 @@ void ppc603_exception(int exception)
ppc.npc = 0x00000000 | 0x0500;
ppc.interrupt_pending &= ~0x1;
change_pc(ppc.npc);
}
break;
@ -46,7 +45,6 @@ void ppc603_exception(int exception)
ppc.npc = 0x00000000 | 0x0900;
ppc.interrupt_pending &= ~0x2;
change_pc(ppc.npc);
}
break;
@ -68,7 +66,6 @@ void ppc603_exception(int exception)
ppc.npc = 0xfff00000 | 0x0700;
else
ppc.npc = 0x00000000 | 0x0700;
change_pc(ppc.npc);
}
break;
@ -90,7 +87,6 @@ void ppc603_exception(int exception)
ppc.npc = 0xfff00000 | 0x0c00;
else
ppc.npc = 0x00000000 | 0x0c00;
change_pc(ppc.npc);
}
break;
@ -114,7 +110,6 @@ void ppc603_exception(int exception)
ppc.npc = 0x00000000 | 0x1400;
ppc.interrupt_pending &= ~0x4;
change_pc(ppc.npc);
}
break;
@ -138,7 +133,6 @@ void ppc603_exception(int exception)
ppc.npc = 0x00000000 | 0x0300;
ppc.interrupt_pending &= ~0x4;
change_pc(ppc.npc);
}
break;
@ -162,7 +156,6 @@ void ppc603_exception(int exception)
ppc.npc = 0x00000000 | 0x0400;
ppc.interrupt_pending &= ~0x4;
change_pc(ppc.npc);
}
break;
@ -219,7 +212,6 @@ static CPU_RESET( ppc603 )
ppc.pc = ppc.npc = 0xfff00100;
ppc_set_msr(0x40);
change_pc(ppc.pc);
ppc.hid0 = 1;
@ -245,8 +237,6 @@ static CPU_EXECUTE( ppc603 )
ppc_dec_trigger_cycle = 0x7fffffff;
}
change_pc(ppc.npc);
// MinGW's optimizer kills setjmp()/longjmp()
SETJMP_GNUC_PROTECT();

8
src/emu/cpu/powerpc/ppc_ops.c
View File

@ -213,8 +213,6 @@ static void ppc_bx(UINT32 op)
if( LKBIT ) {
LR = ppc.pc + 4;
}
change_pc(ppc.npc);
}
static void ppc_bcx(UINT32 op)
@ -227,8 +225,6 @@ static void ppc_bcx(UINT32 op)
} else {
ppc.npc = ppc.pc + (SIMM16 & ~0x3);
}
change_pc(ppc.npc);
}
if( LKBIT ) {
@ -242,7 +238,6 @@ static void ppc_bcctrx(UINT32 op)
if( condition ) {
ppc.npc = CTR & ~0x3;
change_pc(ppc.npc);
}
if( LKBIT ) {
@ -256,7 +251,6 @@ static void ppc_bclrx(UINT32 op)
if( condition ) {
ppc.npc = LR & ~0x3;
change_pc(ppc.npc);
}
if( LKBIT ) {
@ -1018,8 +1012,6 @@ static void ppc_rfi(UINT32 op)
ppc.npc = ppc_get_spr(SPR_SRR0);
msr = ppc_get_spr(SPR_SRR1);
ppc_set_msr( msr );
change_pc(ppc.npc);
}
static void ppc_rlwimix(UINT32 op)

11
src/emu/cpu/s2650/s2650.c
View File

@ -350,7 +350,6 @@ static const int S2650_relative[0x100] =
REL_EA( s2650c->page ); \
s2650c->page = s2650c->ea & PAGE; \
s2650c->iar = s2650c->ea & PMSK; \
change_pc(s2650c->ea); \
} else s2650c->iar = (s2650c->iar + 1) & PMSK; \
}
@ -363,7 +362,6 @@ static const int S2650_relative[0x100] =
REL_ZERO( 0 ); \
s2650c->page = s2650c->ea & PAGE; \
s2650c->iar = s2650c->ea & PMSK; \
change_pc(s2650c->ea); \
}
/***************************************************************
@ -377,7 +375,6 @@ static const int S2650_relative[0x100] =
BRA_EA(); \
s2650c->page = s2650c->ea & PAGE; \
s2650c->iar = s2650c->ea & PMSK; \
change_pc(s2650c->ea); \
} else s2650c->iar = (s2650c->iar + 2) & PMSK; \
}
@ -391,7 +388,6 @@ static const int S2650_relative[0x100] =
s2650c->ea = (s2650c->ea + s2650c->reg[3]) & AMSK; \
s2650c->page = s2650c->ea & PAGE; \
s2650c->iar = s2650c->ea & PMSK; \
change_pc(s2650c->ea); \
}
/***************************************************************
@ -407,7 +403,6 @@ static const int S2650_relative[0x100] =
s2650c->ras[s2650c->psu & SP] = s2650c->page + s2650c->iar; \
s2650c->page = s2650c->ea & PAGE; \
s2650c->iar = s2650c->ea & PMSK; \
change_pc(s2650c->ea); \
} else s2650c->iar = (s2650c->iar + 1) & PMSK; \
}
@ -422,7 +417,6 @@ static const int S2650_relative[0x100] =
s2650c->ras[s2650c->psu & SP] = s2650c->page + s2650c->iar; \
s2650c->page = s2650c->ea & PAGE; \
s2650c->iar = s2650c->ea & PMSK; \
change_pc(s2650c->ea); \
}
/***************************************************************
@ -438,7 +432,6 @@ static const int S2650_relative[0x100] =
s2650c->ras[s2650c->psu & SP] = s2650c->page + s2650c->iar; \
s2650c->page = s2650c->ea & PAGE; \
s2650c->iar = s2650c->ea & PMSK; \
change_pc(s2650c->ea); \
} else s2650c->iar = (s2650c->iar + 2) & PMSK; \
}
@ -454,7 +447,6 @@ static const int S2650_relative[0x100] =
s2650c->ras[s2650c->psu & SP] = s2650c->page + s2650c->iar; \
s2650c->page = s2650c->ea & PAGE; \
s2650c->iar = s2650c->ea & PMSK; \
change_pc(s2650c->ea); \
}
/***************************************************************
@ -470,7 +462,6 @@ static const int S2650_relative[0x100] =
s2650c->psu = (s2650c->psu & ~SP) | ((s2650c->psu - 1) & SP); \
s2650c->page = s2650c->ea & PAGE; \
s2650c->iar = s2650c->ea & PMSK; \
change_pc(s2650c->ea); \
} \
}
@ -488,7 +479,6 @@ static const int S2650_relative[0x100] =
s2650c->psu = (s2650c->psu & ~SP) | ((s2650c->psu - 1) & SP); \
s2650c->page = s2650c->ea & PAGE; \
s2650c->iar = s2650c->ea & PMSK; \
change_pc(s2650c->ea); \
s2650c->psu &= ~II; \
CHECK_IRQ_LINE; \
} \
@ -1499,7 +1489,6 @@ static CPU_SET_INFO( s2650 )
case CPUINFO_INT_PC:
s2650c->page = info->i & PAGE;
s2650c->iar = info->i & PMSK;
change_pc(s2650c->page + s2650c->iar);
break;
case CPUINFO_INT_REGISTER + S2650_PC: s2650c->page = info->i & PAGE; s2650c->iar = info->i & PMSK; break;

11
src/emu/cpu/saturn/satops.c
View File

@ -320,7 +320,6 @@ INLINE void saturn_jump_after_test(void)
} else {
saturn.pc=(saturn.pc+adr-2)&0xfffff;
}
change_pc(saturn.pc);
}
}
INLINE void saturn_st_clear_bit(void)
@ -429,7 +428,6 @@ INLINE void saturn_jump(int adr, int jump)
if (jump) {
saturn.pc=adr;
saturn_ICount-=10;
change_pc(saturn.pc);
}
}
@ -439,7 +437,6 @@ INLINE void saturn_call(int adr)
saturn_push(saturn.pc);
saturn.pc=adr;
// saturn_ICount-=10;
change_pc(saturn.pc);
}
INLINE void saturn_return(int yes)
@ -447,7 +444,6 @@ INLINE void saturn_return(int yes)
if (yes) {
saturn.pc=saturn_pop();
// saturn_ICount-=10;
change_pc(saturn.pc);
}
}
@ -455,7 +451,6 @@ INLINE void saturn_return_carry_set(void)
{
saturn.pc=saturn_pop();
// saturn_ICount-=10;
change_pc(saturn.pc);
saturn.carry=1;
}
@ -463,7 +458,6 @@ INLINE void saturn_return_carry_clear(void)
{
saturn.pc=saturn_pop();
// saturn_ICount-=10;
change_pc(saturn.pc);
saturn.carry=0;
}
@ -473,7 +467,6 @@ INLINE void saturn_return_interrupt(void)
saturn.in_irq=0; /* set to 1 when an IRQ is taken */
saturn.pc=saturn_pop();
// saturn_ICount-=10;
change_pc(saturn.pc);
}
INLINE void saturn_return_xm_set(void)
@ -481,7 +474,6 @@ INLINE void saturn_return_xm_set(void)
saturn.pc=saturn_pop();
saturn.hst|=XM;
// saturn_ICount-=10;
change_pc(saturn.pc);
}
INLINE void saturn_pop_c(void)
@ -498,7 +490,6 @@ INLINE void saturn_indirect_jump(int reg)
{
saturn_assert(reg>=0 && reg<9);
saturn.pc=READ_20(S64_READ_A(reg));
change_pc(saturn.pc);
}
INLINE void saturn_equals_zero(int reg, int begin, int count)
@ -649,7 +640,6 @@ INLINE void saturn_load_pc(int reg)
{
saturn_assert(reg>=0 && reg<9);
saturn.pc=S64_READ_A(reg);
change_pc(saturn.pc);
}
INLINE void saturn_store_pc(int reg)
@ -663,7 +653,6 @@ INLINE void saturn_exchange_pc(int reg)
int temp=saturn.pc;
saturn_assert(reg>=0 && reg<9);
saturn.pc=S64_READ_A(reg);
change_pc(saturn.pc);
S64_WRITE_A(reg, temp);
}

7
src/emu/cpu/saturn/saturn.c
View File

@ -138,7 +138,6 @@ static CPU_RESET( saturn )
saturn.sleeping = 0;
saturn.irq_enable = 0;
saturn.in_irq = 0;
change_pc(saturn.pc);
}
static CPU_GET_CONTEXT( saturn )
@ -152,7 +151,6 @@ static CPU_SET_CONTEXT( saturn )
if( src )
{
saturn = *(Saturn_Regs*)src;
change_pc(saturn.pc);
}
}
@ -169,15 +167,12 @@ INLINE void saturn_take_irq(void)
LOG(("Saturn#%d takes IRQ ($%04x)\n", cpunum_get_active(), saturn.pc));
if (saturn.irq_callback) (*saturn.irq_callback)(saturn.device, SATURN_IRQ_LINE);
change_pc(saturn.pc);
}
static CPU_EXECUTE( saturn )
{
saturn_ICount = cycles;
change_pc(saturn.pc);
do
{
saturn.oldpc = saturn.pc;
@ -261,7 +256,7 @@ static CPU_SET_INFO( saturn )
case CPUINFO_INT_INPUT_STATE + SATURN_WAKEUP_LINE: saturn_set_wakeup_line(info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + SATURN_PC: saturn.pc = info->i; change_pc(saturn.pc); break;
case CPUINFO_INT_REGISTER + SATURN_PC: saturn.pc = info->i; break;
case CPUINFO_INT_REGISTER + SATURN_D0: saturn.d[0] = info->i; break;
case CPUINFO_INT_REGISTER + SATURN_D1: saturn.d[1] = info->i; break;
case CPUINFO_INT_REGISTER + SATURN_A: IntReg64(saturn.reg[A], info->i); break;

6
src/emu/cpu/sc61860/sc61860.c
View File

@ -85,7 +85,6 @@ static CPU_RESET( sc61860 )
sc61860.timer.t512ms=0;
sc61860.timer.count=256;
sc61860.pc=0;
change_pc(sc61860.pc);
}
static CPU_INIT( sc61860 )
@ -107,7 +106,6 @@ static CPU_SET_CONTEXT( sc61860 )
if( src )
{
sc61860 = *(SC61860_Regs*)src;
change_pc(sc61860.pc);
}
}
@ -115,8 +113,6 @@ static CPU_EXECUTE( sc61860 )
{
sc61860_ICount = cycles;
change_pc(sc61860.pc);
do
{
sc61860.oldpc = sc61860.pc;
@ -155,7 +151,7 @@ static CPU_SET_INFO( sc61860 )
{
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + SC61860_PC: sc61860.pc = info->i; change_pc(sc61860.pc); break;
case CPUINFO_INT_REGISTER + SC61860_PC: sc61860.pc = info->i; break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + SC61860_R: sc61860.r = info->i & 0x7F; break;
case CPUINFO_INT_REGISTER + SC61860_DP: sc61860.dp = info->i; break;

8
src/emu/cpu/sc61860/scops.c
View File

@ -299,12 +299,10 @@ INLINE void sc61860_execute_table_call(void)
sc61860.zero=v==sc61860.ram[A];
if (sc61860.zero) {
sc61860.pc=adr;
change_pc(sc61860.pc);
return;
}
}
sc61860.pc=READ_OP_ARG_WORD();
change_pc(sc61860.pc);
}
@ -313,7 +311,6 @@ INLINE void sc61860_call(UINT16 adr)
PUSH(sc61860.pc>>8);
PUSH(sc61860.pc&0xff);
sc61860.pc=adr;
change_pc(sc61860.pc);
}
INLINE void sc61860_return(void)
@ -321,7 +318,6 @@ INLINE void sc61860_return(void)
UINT16 t=POP();
t|=POP()<<8;
sc61860.pc=t;
change_pc(sc61860.pc);
}
INLINE void sc61860_jump(int yes)
@ -329,7 +325,6 @@ INLINE void sc61860_jump(int yes)
UINT16 adr=READ_OP_ARG_WORD();
if (yes) {
sc61860.pc=adr;
change_pc(sc61860.pc);
}
}
@ -339,7 +334,6 @@ INLINE void sc61860_jump_rel_plus(int yes)
adr+=READ_OP_ARG();
if (yes) {
sc61860.pc=adr;
change_pc(sc61860.pc);
sc61860_ICount-=3;
}
}
@ -350,7 +344,6 @@ INLINE void sc61860_jump_rel_minus(int yes)
adr-=READ_OP_ARG();
if (yes) {
sc61860.pc=adr;
change_pc(sc61860.pc);
sc61860_ICount-=3;
}
}
@ -365,7 +358,6 @@ INLINE void sc61860_loop(void)
if (!sc61860.carry) {
sc61860.pc=adr;
adr=POP();
change_pc(sc61860.pc);
sc61860_ICount-=3;
}
}

23
src/emu/cpu/se3208/se3208.c
View File

@ -540,7 +540,6 @@ INST(POP)
if(Set&(1<<10))
{
se3208_state->PC=PopVal(se3208_state)-2; //PC automatically incresases by 2
change_pc(se3208_state->PC+2);
}
}
@ -1011,7 +1010,6 @@ INST(CALL)
Offset<<=1;
PushVal(se3208_state,se3208_state->PC+2);
se3208_state->PC=se3208_state->PC+Offset;
change_pc(se3208_state->PC+2);
CLRFLAG(FLAG_E);
}
@ -1029,7 +1027,6 @@ INST(JV)
if(TESTFLAG(FLAG_V))
{
se3208_state->PC=se3208_state->PC+Offset;
change_pc(se3208_state->PC+2);
}
CLRFLAG(FLAG_E);
@ -1049,7 +1046,6 @@ INST(JNV)
if(!TESTFLAG(FLAG_V))
{
se3208_state->PC=se3208_state->PC+Offset;
change_pc(se3208_state->PC+2);
}
CLRFLAG(FLAG_E);
@ -1068,7 +1064,6 @@ INST(JC)
if(TESTFLAG(FLAG_C))
{
se3208_state->PC=se3208_state->PC+Offset;
change_pc(se3208_state->PC+2);
}
CLRFLAG(FLAG_E);
@ -1087,7 +1082,6 @@ INST(JNC)
if(!TESTFLAG(FLAG_C))
{
se3208_state->PC=se3208_state->PC+Offset;
change_pc(se3208_state->PC+2);
}
CLRFLAG(FLAG_E);
@ -1106,7 +1100,6 @@ INST(JP)
if(!TESTFLAG(FLAG_S))
{
se3208_state->PC=se3208_state->PC+Offset;
change_pc(se3208_state->PC+2);
}
CLRFLAG(FLAG_E);
@ -1125,7 +1118,6 @@ INST(JM)
if(TESTFLAG(FLAG_S))
{
se3208_state->PC=se3208_state->PC+Offset;
change_pc(se3208_state->PC+2);
}
CLRFLAG(FLAG_E);
@ -1144,7 +1136,6 @@ INST(JNZ)
if(!TESTFLAG(FLAG_Z))
{
se3208_state->PC=se3208_state->PC+Offset;
change_pc(se3208_state->PC+2);
}
CLRFLAG(FLAG_E);
@ -1163,7 +1154,6 @@ INST(JZ)
if(TESTFLAG(FLAG_Z))
{
se3208_state->PC=se3208_state->PC+Offset;
change_pc(se3208_state->PC+2);
}
CLRFLAG(FLAG_E);
@ -1184,7 +1174,6 @@ INST(JGE)
if(!(S^V))
{
se3208_state->PC=se3208_state->PC+Offset;
change_pc(se3208_state->PC+2);
}
CLRFLAG(FLAG_E);
@ -1205,7 +1194,6 @@ INST(JLE)
if(TESTFLAG(FLAG_Z) || (S^V))
{
se3208_state->PC=se3208_state->PC+Offset;
change_pc(se3208_state->PC+2);
}
CLRFLAG(FLAG_E);
}
@ -1223,7 +1211,6 @@ INST(JHI)
if(!(TESTFLAG(FLAG_Z) || TESTFLAG(FLAG_C)))
{
se3208_state->PC=se3208_state->PC+Offset;
change_pc(se3208_state->PC+2);
}
CLRFLAG(FLAG_E);
@ -1242,7 +1229,6 @@ INST(JLS)
if(TESTFLAG(FLAG_Z) || TESTFLAG(FLAG_C))
{
se3208_state->PC=se3208_state->PC+Offset;
change_pc(se3208_state->PC+2);
}
CLRFLAG(FLAG_E);
@ -1263,7 +1249,6 @@ INST(JGT)
if(!(TESTFLAG(FLAG_Z) || (S^V)))
{
se3208_state->PC=se3208_state->PC+Offset;
change_pc(se3208_state->PC+2);
}
CLRFLAG(FLAG_E);
@ -1284,7 +1269,6 @@ INST(JLT)
if(S^V)
{
se3208_state->PC=se3208_state->PC+Offset;
change_pc(se3208_state->PC+2);
}
CLRFLAG(FLAG_E);
@ -1304,7 +1288,6 @@ INST(JMP)
Offset<<=1;
se3208_state->PC=se3208_state->PC+Offset;
change_pc(se3208_state->PC+2);
CLRFLAG(FLAG_E);
}
@ -1314,7 +1297,6 @@ INST(JR)
UINT32 Src=EXTRACT(Opcode,0,3);
se3208_state->PC=se3208_state->R[Src]-2;
change_pc(se3208_state->PC+2);
CLRFLAG(FLAG_E);
}
@ -1324,7 +1306,6 @@ INST(CALLR)
UINT32 Src=EXTRACT(Opcode,0,3);
PushVal(se3208_state,se3208_state->PC+2);
se3208_state->PC=se3208_state->R[Src]-2;
change_pc(se3208_state->PC+2);
CLRFLAG(FLAG_E);
}
@ -1429,7 +1410,6 @@ INST(SWI)
CLRFLAG(FLAG_ENI|FLAG_E|FLAG_M);
se3208_state->PC=SE3208_Read32(se3208_state, 4*Imm+0x40)-2;
change_pc(se3208_state->PC+2);
}
INST(HALT)
@ -1735,7 +1715,6 @@ static CPU_RESET( SE3208 )
se3208_state->SR=0;
se3208_state->IRQ=CLEAR_LINE;
se3208_state->NMI=CLEAR_LINE;
change_pc(se3208_state->PC+2);
}
static void SE3208_NMI(se3208_state_t *se3208_state)
@ -1746,7 +1725,6 @@ static void SE3208_NMI(se3208_state_t *se3208_state)
CLRFLAG(FLAG_NMI|FLAG_ENI|FLAG_E|FLAG_M);
se3208_state->PC=SE3208_Read32(se3208_state, 4);
change_pc(se3208_state->PC+2);
}
static void SE3208_Interrupt(se3208_state_t *se3208_state)
@ -1764,7 +1742,6 @@ static void SE3208_Interrupt(se3208_state_t *se3208_state)
se3208_state->PC=SE3208_Read32(se3208_state, 8);
else
se3208_state->PC=SE3208_Read32(se3208_state, 4*se3208_state->irq_callback(se3208_state->device, 0));
change_pc(se3208_state->PC+2);
}

6
src/emu/cpu/sh2/sh2.c
View File

@ -49,7 +49,6 @@
20021020 O. Galibert
- DMA implementation, lightly tested
- change_pc() crap fixed
- delay slot in debugger fixed
- add divide box mirrors
- Nicola-ify the indentation
@ -334,7 +333,6 @@ INLINE void BF(UINT32 d)
{
INT32 disp = ((INT32)d << 24) >> 24;
sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
change_pc(sh2->pc & AM);
sh2_icount -= 2;
}
}
@ -425,7 +423,6 @@ INLINE void BT(UINT32 d)
{
INT32 disp = ((INT32)d << 24) >> 24;
sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
change_pc(sh2->pc & AM);
sh2_icount -= 2;
}
}
@ -1742,7 +1739,6 @@ INLINE void TRAPA(UINT32 i)
WL( sh2->r[15], sh2->pc );
sh2->pc = RL( sh2->ea );
change_pc(sh2->pc & AM);
sh2_icount -= 7;
}
@ -2173,7 +2169,6 @@ static CPU_RESET( sh2 )
sh2->pc = RL(0);
sh2->r[15] = RL(4);
sh2->sr = I;
change_pc(sh2->pc & AM);
sh2->internal_irq_level = -1;
}
@ -2203,7 +2198,6 @@ static CPU_EXECUTE( sh2 )
if (sh2->delay)
{
opcode = memory_decrypted_read_word(sh2->program, WORD_XOR_BE((UINT32)(sh2->delay & AM)));
change_pc(sh2->pc & AM);
sh2->pc -= 2;
}
else

1
src/emu/cpu/sh2/sh2comn.c
View File

@ -697,7 +697,6 @@ void sh2_exception(const char *message, int irqline)
/* fetch PC */
sh2->pc = RL( sh2, sh2->vbr + vector * 4 );
change_pc(sh2->pc & AM);
#endif
}

1
src/emu/cpu/sh2/sh2drc.c
View File

@ -818,7 +818,6 @@ static CPU_RESET( sh2 )
sh2->pc = memory_read_dword_32be(sh2->program, 0);
sh2->r[15] = memory_read_dword_32be(sh2->program, 4);
sh2->sr = I;
change_pc(sh2->pc & AM);
sh2->internal_irq_level = -1;

5
src/emu/cpu/sh4/sh4.c
View File

@ -313,7 +313,6 @@ INLINE void BF(UINT32 d)
{
INT32 disp = ((INT32)d << 24) >> 24;
sh4.pc = sh4.ea = sh4.pc + disp * 2 + 2;
change_pc(sh4.pc & AM);
sh4.sh4_icount -= 2;
}
}
@ -404,7 +403,6 @@ INLINE void BT(UINT32 d)
{
INT32 disp = ((INT32)d << 24) >> 24;
sh4.pc = sh4.ea = sh4.pc + disp * 2 + 2;
change_pc(sh4.pc & AM);
sh4.sh4_icount -= 2;
}
}
@ -1743,7 +1741,6 @@ INLINE void TRAPA(UINT32 i)
sh4.m[EXPEVT] = 0x00000160;
sh4.pc = sh4.vbr + 0x00000100;
change_pc(sh4.pc & AM);
sh4.sh4_icount -= 7;
}
@ -3311,7 +3308,6 @@ static CPU_RESET( sh4 )
sh4.fpu_pr = (sh4.fpscr & PR) ? 1 : 0;
sh4.fpul = 0;
sh4.dbr = 0;
change_pc(sh4.pc & AM);
sh4.internal_irq_level = -1;
sh4.irln = 15;
@ -3332,7 +3328,6 @@ static CPU_EXECUTE( sh4 )
if (sh4.delay)
{
opcode = memory_decrypted_read_word(sh4.program, WORD2_XOR_LE((UINT32)(sh4.delay & AM)));
change_pc(sh4.pc & AM);
sh4.pc -= 2;
}
else

1
src/emu/cpu/sh4/sh4comn.c
View File

@ -206,7 +206,6 @@ void sh4_exception(const char *message, int exception) // handle exception
/* fetch PC */
sh4.pc = sh4.vbr + vector;
change_pc(sh4.pc & AM);
}
static UINT32 compute_ticks_refresh_timer(emu_timer *timer, int hertz, int base, int divisor)

2
src/emu/cpu/sharc/sharc.c
View File

@ -617,8 +617,6 @@ static CPU_SET_CONTEXT( sharc )
{
sharc = *(SHARC_REGS *)src;
}
change_pc(sharc.pc);
}
static void sharc_set_irq_line(int irqline, int state)

4
src/emu/cpu/spc700/spc700.h
View File

@ -141,8 +141,8 @@ extern CPU_GET_INFO( spc700 );
//#define spc700_read_8_immediate(A) memory_raw_read_byte(spc700i_cpu.program,A)
#define spc700_read_instruction(A) memory_read_byte_8le(spc700i_cpu.program,A)
#define spc700_read_8_immediate(A) memory_read_byte_8le(spc700i_cpu.program,A)
#define spc700_jumping(A) change_pc(A)
#define spc700_branching(A) change_pc(A)
#define spc700_jumping(A)
#define spc700_branching(A)

6
src/emu/cpu/ssp1601/ssp1601.c
View File

@ -78,7 +78,6 @@ struct _ssp1601_state_t
#define FETCH() memory_decrypted_read_word(ssp1601_state->program, rPC++ << 1)
#define PROGRAM_WORD(a) memory_read_word(ssp1601_state->program, (a) << 1)
#define GET_PPC_OFFS() PPC
#define CHANGEPC() change_pc(rPC << 1)
#define REG_READ(ssp1601_state,r) (((r) <= 4) ? ssp1601_state->gr[r].w.h : reg_read_handlers[r](ssp1601_state, r))
#define REG_WRITE(ssp1601_state,r,d) { \
@ -294,7 +293,6 @@ static void write_PC(ssp1601_state_t *ssp1601_state, int reg, UINT32 d)
{
rPC = d;
ssp1601_state->g_cycles--;
CHANGEPC();
}
// 7
@ -611,7 +609,7 @@ static CPU_EXECUTE( ssp1601 )
int cond = 0;
CHECK_00f();
COND_CHECK
if (cond) { int new_PC = FETCH(); write_STACK(ssp1601_state, SSP_STACK, rPC); rPC = new_PC; CHANGEPC(); }
if (cond) { int new_PC = FETCH(); write_STACK(ssp1601_state, SSP_STACK, rPC); rPC = new_PC; }
else rPC++;
ssp1601_state->g_cycles--; // always 2 cycles
break;
@ -630,7 +628,7 @@ static CPU_EXECUTE( ssp1601 )
int cond = 0;
CHECK_00f();
COND_CHECK
if (cond) { rPC = FETCH(); CHANGEPC(); }
if (cond) { rPC = FETCH(); }
else rPC++;
ssp1601_state->g_cycles--;
break;

5
src/emu/cpu/t11/t11.c
View File

@ -224,7 +224,6 @@ static void t11_check_irqs(void)
PUSH(PC);
PCD = new_pc;
PSW = new_psw;
change_pc(PC);
t11_check_irqs();
/* count cycles and clear the WAIT flag */
@ -273,7 +272,6 @@ static CPU_SET_CONTEXT( t11 )
{
if (src)
t11 = *(t11_Regs *)src;
change_pc(PC);
t11_check_irqs();
}
@ -337,7 +335,6 @@ static CPU_RESET( t11 )
/* initial PC comes from the setup word */
PC = t11.initial_pc;
change_pc(PC);
/* PSW starts off at highest priority */
PSW = 0xe0;
@ -433,7 +430,7 @@ static CPU_SET_INFO( t11 )
case CPUINFO_INT_INPUT_STATE + T11_IRQ3: set_irq_line(T11_IRQ3, info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + T11_PC: PC = info->i; change_pc(PC); break;
case CPUINFO_INT_REGISTER + T11_PC: PC = info->i; break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + T11_SP: SP = info->i; break;
case CPUINFO_INT_REGISTER + T11_PSW: PSW = info->i; break;

19
src/emu/cpu/t11/t11ops.c
View File

@ -192,9 +192,9 @@
#define INCB_R(d) int dreg, dest, result; GET_DB_##d; CLR_NZV; result = dest + 1; SETB_NZ; if (dest == 0x7f) SET_V; PUT_DB_DREG(result)
#define INCB_M(d) int dreg, dest, result, ea; GET_DB_##d; CLR_NZV; result = dest + 1; SETB_NZ; if (dest == 0x7f) SET_V; PUT_DB_EA(result)
/* JMP: PC = ea */
#define JMP(d) int dreg, ea; GET_DREG; MAKE_EAW_##d(dreg); PC = ea; change_pc(PC)
#define JMP(d) int dreg, ea; GET_DREG; MAKE_EAW_##d(dreg); PC = ea
/* JSR: PUSH src, src = PC, PC = ea */
#define JSR(d) int sreg, dreg, ea; GET_SREG; GET_DREG; MAKE_EAW_##d(dreg); PUSH(REGW(sreg)); REGW(sreg) = PC; PC = ea; change_pc(PC)
#define JSR(d) int sreg, dreg, ea; GET_SREG; GET_DREG; MAKE_EAW_##d(dreg); PUSH(REGW(sreg)); REGW(sreg) = PC; PC = ea
/* MFPS: dst = flags */
#define MFPS_R(d) int dreg, result; result = PSW; CLR_NZV; SETB_NZ; PUT_DW_##d((signed char)result)
#define MFPS_M(d) int dreg, result, ea; result = PSW; CLR_NZV; SETB_NZ; PUT_DB_##d(result)
@ -257,11 +257,11 @@ static void op_0000(void)
{
case 0x00: /* HALT */ halt(); break;
case 0x01: /* WAIT */ t11_ICount = 0; t11.wait_state = 1; break;
case 0x02: /* RTI */ t11_ICount -= 24; PC = POP(); PSW = POP(); change_pc(PC); t11_check_irqs(); break;
case 0x03: /* BPT */ t11_ICount -= 48; PUSH(PSW); PUSH(PC); PC = RWORD(0x0c); PSW = RWORD(0x0e); change_pc(PC); t11_check_irqs(); break;
case 0x04: /* IOT */ t11_ICount -= 48; PUSH(PSW); PUSH(PC); PC = RWORD(0x10); PSW = RWORD(0x12); change_pc(PC); t11_check_irqs(); break;
case 0x02: /* RTI */ t11_ICount -= 24; PC = POP(); PSW = POP(); t11_check_irqs(); break;
case 0x03: /* BPT */ t11_ICount -= 48; PUSH(PSW); PUSH(PC); PC = RWORD(0x0c); PSW = RWORD(0x0e); t11_check_irqs(); break;
case 0x04: /* IOT */ t11_ICount -= 48; PUSH(PSW); PUSH(PC); PC = RWORD(0x10); PSW = RWORD(0x12); t11_check_irqs(); break;
case 0x05: /* RESET */ t11_ICount -= 110; break;
case 0x06: /* RTT */ t11_ICount -= 33; PC = POP(); PSW = POP(); change_pc(PC); t11_check_irqs(); break;
case 0x06: /* RTT */ t11_ICount -= 33; PC = POP(); PSW = POP(); t11_check_irqs(); break;
default: illegal(); break;
}
}
@ -273,7 +273,6 @@ static void halt(void)
PUSH(PC);
PC = RWORD(0x04);
PSW = RWORD(0x06);
change_pc(PC);
t11_check_irqs();
}
@ -284,7 +283,6 @@ static void illegal(void)
PUSH(PC);
PC = RWORD(0x08);
PSW = RWORD(0x0a);
change_pc(PC);
t11_check_irqs();
}
@ -295,8 +293,6 @@ static void mark(void)
SP = SP + 2 * (t11.op & 0x3f);
PC = REGW(5);
REGW(5) = POP();
change_pc(PC);
}
static void jmp_rgd(void) { t11_ICount -= 15; { JMP(RGD); } }
@ -314,7 +310,6 @@ static void rts(void)
GET_DREG;
PC = REGD(dreg);
REGW(dreg) = POP();
change_pc(PC);
}
static void ccc(void) { t11_ICount -= 18; { PSW &= ~(t11.op & 15); } }
@ -889,7 +884,6 @@ static void emt(void)
PUSH(PC);
PC = RWORD(0x18);
PSW = RWORD(0x1a);
change_pc(PC);
t11_check_irqs();
}
@ -900,7 +894,6 @@ static void trap(void)
PUSH(PC);
PC = RWORD(0x1c);
PSW = RWORD(0x1e);
change_pc(PC);
t11_check_irqs();
}

15
src/emu/cpu/tlcs90/tlcs90.c
View File

@ -1077,7 +1077,7 @@ INLINE void w16( const e_r r, UINT16 value )
case SP: T90.sp.w.l = value; return;
case AF: T90.af.w.l = value; return;
case AF2: T90.af2.w.l = value; return;
case PC: change_pc( T90.pc.d = value ); return;
case PC: T90.pc.d = value; return;
default:
fatalerror("%04x: unimplemented w16 register index = %d\n",cpu_get_pc(Machine->activecpu),r);
@ -1286,7 +1286,6 @@ static void take_interrupt(e_irq irq)
F &= ~IF;
T90.pc.w.l = 0x10 + irq * 8;
change_pc( T90.pc.d );
T90.extra_cycles += 20*2;
}
@ -1463,7 +1462,6 @@ static CPU_EXECUTE( t90 )
if ( Test( Read1_8() ) )
{
T90.pc.w.l = Read2_16();
change_pc( T90.pc.d );
Cyc();
}
else Cyc_f();
@ -1472,7 +1470,6 @@ static CPU_EXECUTE( t90 )
if ( Test( Read1_8() ) )
{
T90.pc.w.l += /*2 +*/ (INT8)Read2_8();
change_pc( T90.pc.d );
Cyc();
}
else Cyc_f();
@ -1481,7 +1478,6 @@ static CPU_EXECUTE( t90 )
if ( Test( Read1_8() ) )
{
T90.pc.w.l += /*2 +*/ Read2_16();
change_pc( T90.pc.d );
Cyc();
}
else Cyc_f();
@ -1493,7 +1489,6 @@ static CPU_EXECUTE( t90 )
{
Push( PC );
T90.pc.w.l = Read2_16();
change_pc( T90.pc.d );
Cyc();
}
else Cyc_f();
@ -1501,7 +1496,6 @@ static CPU_EXECUTE( t90 )
case CALLR:
Push( PC );
T90.pc.w.l += /*2 +*/ Read1_16();
change_pc( T90.pc.d );
Cyc();
break;
@ -1912,7 +1906,6 @@ static CPU_EXECUTE( t90 )
if ( --T90.bc.b.h )
{
T90.pc.w.l += /*2 +*/ (INT8)Read1_8();
change_pc( T90.pc.d );
Cyc();
}
else Cyc_f();
@ -1921,7 +1914,6 @@ static CPU_EXECUTE( t90 )
if ( --T90.bc.w.l )
{
T90.pc.w.l += /*2 +*/ (INT8)Read2_8();
change_pc( T90.pc.d );
Cyc();
}
else Cyc_f();
@ -1973,7 +1965,7 @@ static CPU_RESET( t90 )
{
T90.irq_state = 0;
T90.irq_mask = 0;
change_pc( T90.pc.d = 0x0000 );
T90.pc.d = 0x0000;
F &= ~IF;
/*
P0/D0-D7 P1/A0-A7 P2/A8-A15 P6 P7 = INPUT
@ -2003,7 +1995,6 @@ static CPU_SET_CONTEXT( t90 )
{
if( src )
T90 = *(t90_Regs*)src;
change_pc(T90.pc.d);
}
@ -2708,7 +2699,7 @@ static CPU_SET_INFO( t90 )
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_IRQ1: set_irq_line( INT1, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_IRQ2: set_irq_line( INT2, info->i); break;
case CPUINFO_INT_PC: change_pc( T90.pc.d = info->i ); break;
case CPUINFO_INT_PC: T90.pc.d = info->i; break;
case CPUINFO_INT_REGISTER + T90_PC: T90.pc.w.l = info->i; break;
case CPUINFO_INT_SP: T90.sp.w.l = info->i; break;
case CPUINFO_INT_REGISTER + T90_SP: T90.sp.w.l = info->i; break;

2
src/emu/cpu/tms32025/tms32025.c
View File

@ -132,7 +132,7 @@ Table 3-2. TMS32025/26 Memory Blocks
static UINT16 *tms32025_pgmmap[0x200];
static UINT16 *tms32025_datamap[0x200];
#define SET_PC(x) do { R.PC = (x); change_pc(R.PC<<1); } while (0)
#define SET_PC(x) do { R.PC = (x); } while (0)
#define P_IN(A) (memory_read_word_16be(R.io, (A)<<1))
#define P_OUT(A,V) (memory_write_word_16be(R.io, ((A)<<1),(V)))

1
src/emu/cpu/tms32051/tms32051.c
View File

@ -161,7 +161,6 @@ static int tms_icount;
INLINE void CHANGE_PC(UINT16 new_pc)
{
tms.pc = new_pc;
change_pc(tms.pc << 1);
}
INLINE UINT16 PM_READ16(UINT16 address)

9
src/emu/cpu/tms34010/34010ops.c
View File

@ -91,7 +91,6 @@ static void unimpl(tms34010_state *tms, UINT16 op)
PUSH(tms, GET_ST(tms));
RESET_ST(tms);
tms->pc = RLONG(tms, 0xfffffc20);
change_pc(TOBYTE(tms->pc));
COUNT_UNKNOWN_CYCLES(tms,16);
/* extra check to prevent bad things */
@ -1425,7 +1424,6 @@ static void move1_aa (tms34010_state *tms, UINT16 op) { MOVE_AA(1); }
PUSH(tms, tms->pc); \
tms->pc = R##REG(tms,DSTREG(op)); \
CORRECT_ODD_PC(tms,"CALL"); \
change_pc(TOBYTE(tms->pc)); \
COUNT_CYCLES(tms,3); \
}
static void call_a (tms34010_state *tms, UINT16 op) { CALL(A); }
@ -1443,7 +1441,6 @@ static void calla(tms34010_state *tms, UINT16 op)
PUSH(tms, tms->pc+0x20);
tms->pc = PARAM_LONG_NO_INC(tms);
CORRECT_ODD_PC(tms,"CALLA");
change_pc(TOBYTE(tms->pc));
COUNT_CYCLES(tms,4);
}
@ -1550,7 +1547,6 @@ static void emu(tms34010_state *tms, UINT16 op)
*rd = tms->pc; \
tms->pc = temppc; \
CORRECT_ODD_PC(tms,"EXGPC"); \
change_pc(TOBYTE(tms->pc)); \
COUNT_CYCLES(tms,2); \
}
static void exgpc_a (tms34010_state *tms, UINT16 op) { EXGPC(A); }
@ -1590,7 +1586,6 @@ static void getst_b (tms34010_state *tms, UINT16 op) { GETST(B); }
{ \
tms->pc = PARAM_LONG_NO_INC(tms); \
CORRECT_ODD_PC(tms,"J_XX_8"); \
change_pc(TOBYTE(tms->pc)); \
COUNT_CYCLES(tms,3); \
} \
else \
@ -1836,7 +1831,6 @@ static void j_NN_x(tms34010_state *tms, UINT16 op)
{ \
tms->pc = R##REG(tms,DSTREG(op)); \
CORRECT_ODD_PC(tms,"JUMP"); \
change_pc(TOBYTE(tms->pc)); \
COUNT_CYCLES(tms,2); \
}
static void jump_a (tms34010_state *tms, UINT16 op) { JUMP(A); }
@ -1867,7 +1861,6 @@ static void reti(tms34010_state *tms, UINT16 op)
INT32 st = POP(tms);
tms->pc = POP(tms);
CORRECT_ODD_PC(tms,"RETI");
change_pc(TOBYTE(tms->pc));
SET_ST(tms, st);
COUNT_CYCLES(tms,11);
}
@ -1877,7 +1870,6 @@ static void rets(tms34010_state *tms, UINT16 op)
UINT32 offs;
tms->pc = POP(tms);
CORRECT_ODD_PC(tms,"RETS");
change_pc(TOBYTE(tms->pc));
offs = PARAM_N(op);
if (offs)
{
@ -1905,7 +1897,6 @@ static void trap(tms34010_state *tms, UINT16 op)
RESET_ST(tms);
tms->pc = RLONG(tms, 0xffffffe0-(t<<5));
CORRECT_ODD_PC(tms,"TRAP");
change_pc(TOBYTE(tms->pc));
COUNT_CYCLES(tms,16);
}

7
src/emu/cpu/tms34010/tms34010.c
View File

@ -546,7 +546,6 @@ static void check_interrupt(tms34010_state *tms)
/* leap to the vector */
RESET_ST(tms);
tms->pc = RLONG(tms, 0xfffffee0);
change_pc(TOBYTE(tms->pc));
COUNT_CYCLES(tms,16);
return;
}
@ -600,7 +599,6 @@ static void check_interrupt(tms34010_state *tms)
PUSH(tms, GET_ST(tms));
RESET_ST(tms);
tms->pc = RLONG(tms, vector);
change_pc(TOBYTE(tms->pc));
COUNT_CYCLES(tms,16);
/* call the callback for externals */
@ -671,7 +669,6 @@ static CPU_RESET( tms34010 )
/* fetch the initial PC and reset the state */
tms->pc = RLONG(tms, 0xffffffe0) & 0xfffffff0;
change_pc(TOBYTE(tms->pc));
RESET_ST(tms);
/* HALT the CPU if requested, and remember to re-read the starting PC */
@ -808,7 +805,6 @@ static CPU_EXECUTE( tms34010 )
/* execute starting now */
tms->icount = cycles;
change_pc(TOBYTE(tms->pc));
/* check interrupts first */
tms->executing = TRUE;
@ -1573,7 +1569,6 @@ READ16_HANDLER( tms34020_io_register_r )
static STATE_POSTLOAD( tms34010_state_postload )
{
tms34010_state *tms = param;
change_pc(TOBYTE(tms->pc));
set_raster_op(tms);
set_pixel_function(tms);
}
@ -1714,7 +1709,7 @@ static CPU_SET_INFO( tms34010 )
case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(tms, 0, info->i); break;
case CPUINFO_INT_INPUT_STATE + 1: set_irq_line(tms, 1, info->i); break;
case CPUINFO_INT_PC: tms->pc = info->i; change_pc(TOBYTE(tms->pc)); break;
case CPUINFO_INT_PC: tms->pc = info->i; break;
case CPUINFO_INT_REGISTER + TMS34010_PC: tms->pc = info->i; break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + TMS34010_SP: SP(tms) = info->i; break;

7
src/emu/cpu/tms7000/tms7000.c
View File

@ -122,9 +122,6 @@ static tms7000_Regs tms7000;
#define SETZ pSR |= SR_Z
#define SETN pSR |= SR_N
#define CHANGE_PC change_pc(pPC)
static READ8_HANDLER( tms7000_internal_r );
static WRITE8_HANDLER( tms7000_internal_w );
static READ8_HANDLER( tms70x0_pf_r );
@ -249,7 +246,6 @@ static CPU_RESET( tms7000 )
WRA( tms7000.pc.b.h ); /* Write previous PC to A:B */
WRB( tms7000.pc.b.l );
pPC = RM16(0xfffe); /* Load reset vector */
CHANGE_PC;
tms7000_div_by_16_trigger = -16;
}
@ -270,7 +266,7 @@ static CPU_SET_INFO( tms7000 )
case CPUINFO_INT_INPUT_STATE + TMS7000_IRQ3_LINE: tms7000_set_irq_line(TMS7000_IRQ3_LINE, info->i); break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + TMS7000_PC: pPC = info->i; CHANGE_PC; break;
case CPUINFO_INT_REGISTER + TMS7000_PC: pPC = info->i; break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + TMS7000_SP: pSP = info->i; break;
case CPUINFO_INT_REGISTER + TMS7000_ST: pSR = info->i; tms7000_check_IRQ_lines(); break;
@ -449,7 +445,6 @@ static void tms7000_do_interrupt( UINT16 address, UINT8 line )
PUSHWORD( PC ); /* Push Program Counter */
pSR = 0; /* Clear Status register */
pPC = RM16(address); /* Load PC with interrupt vector */
CHANGE_PC;
if( tms7000.idle_state == 0 )
tms7000_icount -= 19; /* 19 cycles used */

59
src/emu/cpu/tms7000/tms70op.c
View File

@ -466,7 +466,6 @@ static void br_dir( void )
IMMWORD( p );
pPC = p.d;
CHANGE_PC;
tms7000_icount -= 10;
}
@ -486,7 +485,6 @@ static void br_inx( void )
IMMWORD( p );
pPC = p.w.l + RDB;
CHANGE_PC;
tms7000_icount -= 12;
}
@ -513,7 +511,6 @@ static void btjo_b2a( void )
pPC++;
tms7000_icount -= 7;
}
CHANGE_PC;
}
static void btjo_r2a( void )
@ -540,7 +537,6 @@ static void btjo_r2a( void )
pPC++;
tms7000_icount -= 7;
}
CHANGE_PC;
}
static void btjo_r2b( void )
@ -567,7 +563,6 @@ static void btjo_r2b( void )
pPC++;
tms7000_icount -= 10;
}
CHANGE_PC;
}
static void btjo_r2r( void )
@ -595,7 +590,6 @@ static void btjo_r2r( void )
pPC++;
tms7000_icount -= 12;
}
CHANGE_PC;
}
static void btjo_i2a( void )
@ -622,7 +616,6 @@ static void btjo_i2a( void )
pPC++;
tms7000_icount -= 9;
}
CHANGE_PC;
}
static void btjo_i2b( void )
@ -649,7 +642,6 @@ static void btjo_i2b( void )
pPC++;
tms7000_icount -= 9;
}
CHANGE_PC;
}
static void btjo_i2r( void )
@ -677,7 +669,6 @@ static void btjo_i2r( void )
pPC++;
tms7000_icount -= 11;
}
CHANGE_PC;
}
static void btjop_ap( void )
@ -705,7 +696,6 @@ static void btjop_ap( void )
pPC++;
tms7000_icount -= 11;
}
CHANGE_PC;
}
static void btjop_bp( void )
@ -733,7 +723,6 @@ static void btjop_bp( void )
pPC++;
tms7000_icount -= 10;
}
CHANGE_PC;
}
static void btjop_ip( void )
@ -762,7 +751,6 @@ static void btjop_ip( void )
pPC++;
tms7000_icount -= 12;
}
CHANGE_PC;
}
static void btjz_b2a( void )
@ -788,7 +776,6 @@ static void btjz_b2a( void )
pPC++;
tms7000_icount -= 7;
}
CHANGE_PC;
}
static void btjz_r2a( void )
@ -815,7 +802,6 @@ static void btjz_r2a( void )
pPC++;
tms7000_icount -= 7;
}
CHANGE_PC;
}
static void btjz_r2b( void )
@ -842,7 +828,6 @@ static void btjz_r2b( void )
pPC++;
tms7000_icount -= 10;
}
CHANGE_PC;
}
static void btjz_r2r( void )
@ -870,7 +855,6 @@ static void btjz_r2r( void )
pPC++;
tms7000_icount -= 12;
}
CHANGE_PC;
}
static void btjz_i2a( void )
@ -897,7 +881,6 @@ static void btjz_i2a( void )
pPC++;
tms7000_icount -= 9;
}
CHANGE_PC;
}
static void btjz_i2b( void )
@ -924,7 +907,6 @@ static void btjz_i2b( void )
pPC++;
tms7000_icount -= 9;
}
CHANGE_PC;
}
static void btjz_i2r( void )
@ -952,7 +934,6 @@ static void btjz_i2r( void )
pPC++;
tms7000_icount -= 11;
}
CHANGE_PC;
}
static void btjzp_ap( void )
@ -980,7 +961,6 @@ static void btjzp_ap( void )
pPC++;
tms7000_icount -= 11;
}
CHANGE_PC;
}
static void btjzp_bp( void )
@ -1008,7 +988,6 @@ static void btjzp_bp( void )
pPC++;
tms7000_icount -= 10;
}
CHANGE_PC;
}
static void btjzp_ip( void )
@ -1037,7 +1016,6 @@ static void btjzp_ip( void )
pPC++;
tms7000_icount -= 12;
}
CHANGE_PC;
}
static void call_dir( void )
@ -1047,7 +1025,6 @@ static void call_dir( void )
IMMWORD( tPC );
PUSHWORD( PC );
pPC = tPC.d;
CHANGE_PC;
tms7000_icount -= 14;
}
@ -1070,7 +1047,6 @@ static void call_inx( void )
IMMWORD( tPC );
PUSHWORD( PC );
pPC = tPC.w.l + RDB;
CHANGE_PC;
tms7000_icount -= 16;
}
@ -1601,7 +1577,6 @@ static void djnz_a( void )
pPC++;
tms7000_icount -= 2;
}
CHANGE_PC;
}
static void djnz_b( void )
@ -1629,7 +1604,6 @@ static void djnz_b( void )
pPC++;
tms7000_icount -= 2;
}
CHANGE_PC;
}
static void djnz_r( void )
@ -1660,7 +1634,6 @@ static void djnz_r( void )
pPC++;
tms7000_icount -= 3;
}
CHANGE_PC;
}
static void dsb_b2a( void )
@ -1934,7 +1907,6 @@ static void jc( void )
SIMMBYTE( s );
pPC += s;
CHANGE_PC;
tms7000_icount -= 7;
}
else
@ -1952,7 +1924,6 @@ static void jeq( void )
SIMMBYTE( s );
pPC += s;
CHANGE_PC;
tms7000_icount -= 7;
}
else
@ -1975,7 +1946,6 @@ static void jl( void )
SIMMBYTE( s );
pPC += s;
CHANGE_PC;
tms7000_icount -= 7;
}
}
@ -1986,7 +1956,6 @@ static void jmp( void )
SIMMBYTE( s );
pPC += s;
CHANGE_PC;
tms7000_icount -= 7;
}
@ -1998,7 +1967,6 @@ static void j_jn( void )
SIMMBYTE( s );
pPC += s;
CHANGE_PC;
tms7000_icount -= 7;
}
else
@ -2022,7 +1990,6 @@ static void jne( void )
SIMMBYTE( s );
pPC += s;
CHANGE_PC;
tms7000_icount -= 7;
}
}
@ -2040,7 +2007,6 @@ static void jp( void )
SIMMBYTE( s );
pPC += s;
CHANGE_PC;
tms7000_icount -= 7;
}
}
@ -2053,7 +2019,6 @@ static void jpz( void )
SIMMBYTE( s );
pPC += s;
CHANGE_PC;
tms7000_icount -= 7;
}
else
@ -3427,7 +3392,6 @@ static void trap_0( void )
{
PUSHWORD( PC );
pPC = RM16(0xfffe);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3435,7 +3399,6 @@ static void trap_1( void )
{
PUSHWORD( PC );
pPC = RM16(0xfffc);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3443,7 +3406,6 @@ static void trap_2( void )
{
PUSHWORD( PC );
pPC = RM16(0xfffa);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3451,7 +3413,6 @@ static void trap_3( void )
{
PUSHWORD( PC );
pPC = RM16(0xfff8);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3459,7 +3420,6 @@ static void trap_4( void )
{
PUSHWORD( PC );
pPC = RM16(0xfff6);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3467,7 +3427,6 @@ static void trap_5( void )
{
PUSHWORD( PC );
pPC = RM16(0xfff4);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3475,7 +3434,6 @@ static void trap_6( void )
{
PUSHWORD( PC );
pPC = RM16(0xfff2);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3483,7 +3441,6 @@ static void trap_7( void )
{
PUSHWORD( PC );
pPC = RM16(0xfff0);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3491,7 +3448,6 @@ static void trap_8( void )
{
PUSHWORD( PC );
pPC = RM16(0xffee);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3499,7 +3455,6 @@ static void trap_9( void )
{
PUSHWORD( PC );
pPC = RM16(0xffec);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3507,7 +3462,6 @@ static void trap_10( void )
{
PUSHWORD( PC );
pPC = RM16(0xffea);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3515,7 +3469,6 @@ static void trap_11( void )
{
PUSHWORD( PC );
pPC = RM16(0xffe8);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3523,7 +3476,6 @@ static void trap_12( void )
{
PUSHWORD( PC );
pPC = RM16(0xffe6);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3531,7 +3483,6 @@ static void trap_13( void )
{
PUSHWORD( PC );
pPC = RM16(0xffe4);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3539,7 +3490,6 @@ static void trap_14( void )
{
PUSHWORD( PC );
pPC = RM16(0xffe2);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3547,7 +3497,6 @@ static void trap_15( void )
{
PUSHWORD( PC );
pPC = RM16(0xffe0);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3555,7 +3504,6 @@ static void trap_16( void )
{
PUSHWORD( PC );
pPC = RM16(0xffde);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3563,7 +3511,6 @@ static void trap_17( void )
{
PUSHWORD( PC );
pPC = RM16(0xffdc);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3571,7 +3518,6 @@ static void trap_18( void )
{
PUSHWORD( PC );
pPC = RM16(0xffda);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3579,7 +3525,6 @@ static void trap_19( void )
{
PUSHWORD( PC );
pPC = RM16(0xffd8);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3587,7 +3532,6 @@ static void trap_20( void )
{
PUSHWORD( PC );
pPC = RM16(0xffd6);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3595,7 +3539,6 @@ static void trap_21( void )
{
PUSHWORD( PC );
pPC = RM16(0xffd4);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3603,7 +3546,6 @@ static void trap_22( void )
{
PUSHWORD( PC );
pPC = RM16(0xffd2);
CHANGE_PC;
tms7000_icount -= 14;
}
@ -3611,7 +3553,6 @@ static void trap_23( void )
{
PUSHWORD( PC );
pPC = RM16(0xffd0);
CHANGE_PC;
tms7000_icount -= 14;
}

16
src/emu/cpu/upd7810/7810ops.c
View File

@ -169,7 +169,6 @@ static void SLL_C(void)
static void JEA(void)
{
PC = EA;
change_pc( PCD );
}
/* 48 29: 0100 1000 0010 1001 */
@ -181,7 +180,6 @@ static void CALB(void)
WM( SPD, PCL );
PC = BC;
change_pc( PCD );
}
/* 48 2a: 0100 1000 0010 1010 */
@ -8113,7 +8111,6 @@ static void INRW_wa(void)
static void JB(void)
{
PC = BC;
change_pc( PCD );
}
/* 22: 0010 0010 */
@ -8337,7 +8334,6 @@ static void CALL_w(void)
WM( SPD, PCL );
PC = w.w.l;
change_pc( PCD );
}
/* 41: 0100 0001 */
@ -8453,7 +8449,6 @@ static void JRE(void)
PC -= 256 - offs;
else
PC += offs;
change_pc( PCD );
}
/* 50: 0101 0000 */
@ -8500,7 +8495,6 @@ static void JMP_w(void)
RDOPARG( w.b.h );
PCD = w.d;
change_pc( PCD );
}
/* 55: 0101 0101 oooo oooo xxxx xxxx */
@ -8866,7 +8860,6 @@ static void RETI(void)
SP++;
PSW = RM( SPD );
SP++;
change_pc( PCD );
}
/* 63: 0110 0011 oooo oooo */
@ -8998,7 +8991,6 @@ static void SOFTI(void)
WM( SPD, PCL );
PC = 0x0060;
change_pc( PCD );
}
/* 74: prefix */
@ -9045,7 +9037,6 @@ static void CALF(void)
WM( SPD, PCL );
PCD = w.d;
change_pc( PCD );
}
/* 80: 100t tttt */
@ -9070,8 +9061,6 @@ static void CALT(void)
PCL=RM(w.w.l);
PCH=RM(w.w.l+1);
change_pc( PCD );
}
}
@ -9268,7 +9257,6 @@ static void RET(void)
SP++;
PCH = RM( SPD );
SP++;
change_pc( PCD );
}
/* b9: 1011 1001 */
@ -9279,7 +9267,6 @@ static void RETS(void)
PCH = RM( SPD );
SP++;
PSW|=SK; /* skip one instruction */
change_pc( PCD );
}
/* ba: 1011 1010 */
@ -9335,7 +9322,6 @@ static void JR(void)
{
INT8 offs = (INT8)(OP << 2) >> 2;
PC += offs;
change_pc(PCD);
}
/*********************/
@ -9358,8 +9344,6 @@ static void CALT_7801(void)
PCL=RM(w.w.l);
PCH=RM(w.w.l+1);
change_pc( PCD );
}
/* DCR(W) and INR(W) instructions do not modify the CY register on at least 78c05 and 78c06 */

5
src/emu/cpu/upd7810/upd7810.c
View File

@ -843,7 +843,6 @@ static void upd7810_take_irq(void)
IFF = 0;
PSW &= ~(SK|L0|L1);
PC = vector;
change_pc( PCD );
}
}
@ -1769,7 +1768,6 @@ static CPU_EXECUTE( upd7810 )
}
PSW &= ~SK;
upd7810.handle_timers( cc );
change_pc( PCD );
}
else
{
@ -1816,7 +1814,6 @@ static void set_irq_line(int irqline, int state)
IFF = 0;
PSW &= ~(SK|L0|L1);
PC = 0x0004;
change_pc( PCD );
}
}
else
@ -1850,7 +1847,7 @@ static CPU_SET_INFO( upd7810 )
case CPUINFO_INT_INPUT_STATE + UPD7810_INTF2: set_irq_line(UPD7810_INTF2, info->i); break;
case CPUINFO_INT_INPUT_STATE + UPD7810_INTFE1: set_irq_line(UPD7810_INTFE1, info->i); break;
case CPUINFO_INT_PC: PC = info->i; change_pc(PCD); break;
case CPUINFO_INT_PC: PC = info->i; break;
case CPUINFO_INT_REGISTER + UPD7810_PC: PC = info->i; break;
case CPUINFO_INT_SP:
case CPUINFO_INT_REGISTER + UPD7810_SP: SP = info->i; break;

38
src/emu/cpu/v30mz/v30mz.c
View File

@ -124,8 +124,6 @@ static CPU_RESET( nec )
I.sregs[CS] = 0xffff;
CHANGE_PC;
for (i = 0;i < 256; i++)
{
for (j = i, c = 0; j > 0; j >>= 1)
@ -177,7 +175,6 @@ static void nec_interrupt(unsigned int_num,BOOLEAN md_flag)
PUSH(I.ip);
I.ip = (WORD)dest_off;
I.sregs[CS] = (WORD)dest_seg;
CHANGE_PC;
}
static void nec_trap(void)
@ -561,7 +558,7 @@ OP( 0x97, i_xchg_axdi ) { XchgAWReg(IY); CLK(3); }
OP( 0x98, i_cbw ) { I.regs.b[AH] = (I.regs.b[AL] & 0x80) ? 0xff : 0; CLK(1); }
OP( 0x99, i_cwd ) { I.regs.w[DW] = (I.regs.b[AH] & 0x80) ? 0xffff : 0; CLK(1); }
OP( 0x9a, i_call_far ) { UINT32 tmp, tmp2; FETCHWORD(tmp); FETCHWORD(tmp2); PUSH(I.sregs[CS]); PUSH(I.ip); I.ip = (WORD)tmp; I.sregs[CS] = (WORD)tmp2; CHANGE_PC; CLK(10); }
OP( 0x9a, i_call_far ) { UINT32 tmp, tmp2; FETCHWORD(tmp); FETCHWORD(tmp2); PUSH(I.sregs[CS]); PUSH(I.ip); I.ip = (WORD)tmp; I.sregs[CS] = (WORD)tmp2; CLK(10); }
OP( 0x9b, i_wait ) { logerror("%06x: Hardware POLL\n",cpu_get_pc(Machine->activecpu)); }
OP( 0x9c, i_pushf ) { PUSH( CompressFlags() ); CLK(2); }
OP( 0x9d, i_popf ) { UINT32 tmp; POP(tmp); ExpandFlags(tmp); CLK(3); if (I.TF) nec_trap(); }
@ -638,8 +635,8 @@ OP( 0xc1, i_rotshft_wd8 ) {
}
}
OP( 0xc2, i_ret_d16 ) { UINT32 count = FETCH; count += FETCH << 8; POP(I.ip); I.regs.w[SP]+=count; CHANGE_PC; CLK(6); }
OP( 0xc3, i_ret ) { POP(I.ip); CHANGE_PC; CLK(6); }
OP( 0xc2, i_ret_d16 ) { UINT32 count = FETCH; count += FETCH << 8; POP(I.ip); I.regs.w[SP]+=count; CLK(6); }
OP( 0xc3, i_ret ) { POP(I.ip); CLK(6); }
OP( 0xc4, i_les_dw ) { GetModRM; WORD tmp = GetRMWord(ModRM); RegWord(ModRM)=tmp; I.sregs[ES] = GetnextRMWord; CLK(6); }
OP( 0xc5, i_lds_dw ) { GetModRM; WORD tmp = GetRMWord(ModRM); RegWord(ModRM)=tmp; I.sregs[DS] = GetnextRMWord; CLK(6); }
OP( 0xc6, i_mov_bd8 ) { GetModRM; PutImmRMByte(ModRM); CLK(1); }
@ -666,12 +663,12 @@ OP( 0xc9, i_leave ) {
POP(I.regs.w[BP]);
CLK(2);
}
OP( 0xca, i_retf_d16 ) { UINT32 count = FETCH; count += FETCH << 8; POP(I.ip); POP(I.sregs[CS]); I.regs.w[SP]+=count; CHANGE_PC; CLK(9); }
OP( 0xcb, i_retf ) { POP(I.ip); POP(I.sregs[CS]); CHANGE_PC; CLK(8); }
OP( 0xca, i_retf_d16 ) { UINT32 count = FETCH; count += FETCH << 8; POP(I.ip); POP(I.sregs[CS]); I.regs.w[SP]+=count; CLK(9); }
OP( 0xcb, i_retf ) { POP(I.ip); POP(I.sregs[CS]); CLK(8); }
OP( 0xcc, i_int3 ) { nec_interrupt(3,0); CLK(9); }
OP( 0xcd, i_int ) { nec_interrupt(FETCH,0); CLK(10); }
OP( 0xce, i_into ) { if (OF) { nec_interrupt(4,0); CLK(13); } else CLK(6); }
OP( 0xcf, i_iret ) { POP(I.ip); POP(I.sregs[CS]); i_popf(); CHANGE_PC; CLK(10); }
OP( 0xcf, i_iret ) { POP(I.ip); POP(I.sregs[CS]); i_popf(); CLK(10); }
OP( 0xd0, i_rotshft_b ) {
UINT32 src, dst; GetModRM; src = (UINT32)GetRMByte(ModRM); dst=src;
@ -741,18 +738,18 @@ OP( 0xd6, i_setalc ) { I.regs.b[AL] = (CF)?0xff:0x00; CLK(3); logerror("%06x: Un
OP( 0xd7, i_trans ) { UINT32 dest = (I.regs.w[BW]+I.regs.b[AL])&0xffff; I.regs.b[AL] = GetMemB(DS, dest); CLK(5); }
OP( 0xd8, i_fpo ) { GetModRM; CLK(1); logerror("%06x: Unimplemented floating point control %04x\n",cpu_get_pc(Machine->activecpu),ModRM); }
OP( 0xe0, i_loopne ) { INT8 disp = (INT8)FETCH; I.regs.w[CW]--; if (!ZF && I.regs.w[CW]) { I.ip = (WORD)(I.ip+disp); /*CHANGE_PC;*/ CLK(6); } else CLK(3); }
OP( 0xe1, i_loope ) { INT8 disp = (INT8)FETCH; I.regs.w[CW]--; if ( ZF && I.regs.w[CW]) { I.ip = (WORD)(I.ip+disp); /*CHANGE_PC;*/ CLK(6); } else CLK(3); }
OP( 0xe2, i_loop ) { INT8 disp = (INT8)FETCH; I.regs.w[CW]--; if (I.regs.w[CW]) { I.ip = (WORD)(I.ip+disp); /*CHANGE_PC;*/ CLK(5); } else CLK(2); }
OP( 0xe3, i_jcxz ) { INT8 disp = (INT8)FETCH; if (I.regs.w[CW] == 0) { I.ip = (WORD)(I.ip+disp); /*CHANGE_PC;*/ CLK(4); } else CLK(1); }
OP( 0xe0, i_loopne ) { INT8 disp = (INT8)FETCH; I.regs.w[CW]--; if (!ZF && I.regs.w[CW]) { I.ip = (WORD)(I.ip+disp); CLK(6); } else CLK(3); }
OP( 0xe1, i_loope ) { INT8 disp = (INT8)FETCH; I.regs.w[CW]--; if ( ZF && I.regs.w[CW]) { I.ip = (WORD)(I.ip+disp); CLK(6); } else CLK(3); }
OP( 0xe2, i_loop ) { INT8 disp = (INT8)FETCH; I.regs.w[CW]--; if (I.regs.w[CW]) { I.ip = (WORD)(I.ip+disp); CLK(5); } else CLK(2); }
OP( 0xe3, i_jcxz ) { INT8 disp = (INT8)FETCH; if (I.regs.w[CW] == 0) { I.ip = (WORD)(I.ip+disp); CLK(4); } else CLK(1); }
OP( 0xe4, i_inal ) { UINT8 port = FETCH; I.regs.b[AL] = read_port(port); CLK(6); }
OP( 0xe5, i_inax ) { UINT8 port = FETCH; I.regs.b[AL] = read_port(port); I.regs.b[AH] = read_port(port+1); CLK(6); }
OP( 0xe6, i_outal ) { UINT8 port = FETCH; write_port(port, I.regs.b[AL]); CLK(6); }
OP( 0xe7, i_outax ) { UINT8 port = FETCH; write_port(port, I.regs.b[AL]); write_port(port+1, I.regs.b[AH]); CLK(6); }
OP( 0xe8, i_call_d16 ) { UINT32 tmp; FETCHWORD(tmp); PUSH(I.ip); I.ip = (WORD)(I.ip+(INT16)tmp); CHANGE_PC; CLK(5); }
OP( 0xe9, i_jmp_d16 ) { UINT32 tmp; FETCHWORD(tmp); I.ip = (WORD)(I.ip+(INT16)tmp); CHANGE_PC; CLK(4); }
OP( 0xea, i_jmp_far ) { UINT32 tmp,tmp1; FETCHWORD(tmp); FETCHWORD(tmp1); I.sregs[CS] = (WORD)tmp1; I.ip = (WORD)tmp; CHANGE_PC; CLK(7); }
OP( 0xe8, i_call_d16 ) { UINT32 tmp; FETCHWORD(tmp); PUSH(I.ip); I.ip = (WORD)(I.ip+(INT16)tmp); CLK(5); }
OP( 0xe9, i_jmp_d16 ) { UINT32 tmp; FETCHWORD(tmp); I.ip = (WORD)(I.ip+(INT16)tmp); CLK(4); }
OP( 0xea, i_jmp_far ) { UINT32 tmp,tmp1; FETCHWORD(tmp); FETCHWORD(tmp1); I.sregs[CS] = (WORD)tmp1; I.ip = (WORD)tmp; CLK(7); }
OP( 0xeb, i_jmp_d8 ) { int tmp = (int)((INT8)FETCH); CLK(4);
if (tmp==-2 && I.no_interrupt==0 && (I.pending_irq==0) && nec_ICount>0) nec_ICount%=12; /* cycle skip */
I.ip = (WORD)(I.ip+tmp);
@ -864,10 +861,10 @@ OP( 0xff, i_ffpre ) { UINT32 tmp, tmp1; GetModRM; tmp=GetRMWord(ModRM);
switch(ModRM & 0x38) {
case 0x00: tmp1 = tmp+1; I.OverVal = (tmp==0x7fff); SetAF(tmp1,tmp,1); SetSZPF_Word(tmp1); PutbackRMWord(ModRM,(WORD)tmp1); CLKM(1,3); break; /* INC */
case 0x08: tmp1 = tmp-1; I.OverVal = (tmp==0x8000); SetAF(tmp1,tmp,1); SetSZPF_Word(tmp1); PutbackRMWord(ModRM,(WORD)tmp1); CLKM(1,3); break; /* DEC */
case 0x10: PUSH(I.ip); I.ip = (WORD)tmp; CHANGE_PC; CLKM(5,6); break; /* CALL */
case 0x18: tmp1 = I.sregs[CS]; I.sregs[CS] = GetnextRMWord; PUSH(tmp1); PUSH(I.ip); I.ip = tmp; CHANGE_PC; CLKM(5,12); break; /* CALL FAR */
case 0x20: I.ip = tmp; CHANGE_PC; CLKM(4,5); break; /* JMP */
case 0x28: I.ip = tmp; I.sregs[CS] = GetnextRMWord; CHANGE_PC; CLK(10); break; /* JMP FAR */
case 0x10: PUSH(I.ip); I.ip = (WORD)tmp; CLKM(5,6); break; /* CALL */
case 0x18: tmp1 = I.sregs[CS]; I.sregs[CS] = GetnextRMWord; PUSH(tmp1); PUSH(I.ip); I.ip = tmp; CLKM(5,12); break; /* CALL FAR */
case 0x20: I.ip = tmp; CLKM(4,5); break; /* JMP */
case 0x28: I.ip = tmp; I.sregs[CS] = GetnextRMWord; CLK(10); break; /* JMP FAR */
case 0x30: PUSH(tmp); CLK(1); break;
default: logerror("%06x: FF Pre with unimplemented mod\n",cpu_get_pc(Machine->activecpu));
}
@ -892,7 +889,6 @@ static CPU_SET_CONTEXT( nec )
if( src )
{
I = *(nec_Regs*)src;
CHANGE_PC;
}
}

3
src/emu/cpu/v30mz/v30mz.h
View File

@ -64,8 +64,6 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,IXH,IXL,IYH,IYL } BREGS;
/************************************************************************/
#define CHANGE_PC change_pc((I.sregs[CS]<<4) + I.ip)
#define SegBase(Seg) (I.sregs[Seg] << 4)
#define DefaultBase(Seg) ((seg_prefix && (Seg==DS || Seg==SS)) ? prefix_base : I.sregs[Seg] << 4)
@ -152,7 +150,6 @@ typedef enum { AH,AL,CH,CL,DH,DL,BH,BL,SPH,SPL,BPH,BPL,IXH,IXL,IYH,IYL } BREGS;
static const UINT8 table[3]={3,10,10}; \
I.ip = (WORD)(I.ip+tmp); \
nec_ICount-=table[chip_type/8]; \
CHANGE_PC; \
return; \
}

4
src/emu/cpu/z180/z180.c
View File

@ -2114,7 +2114,6 @@ static CPU_RESET( z180 )
if (Z180.daisy)
z80daisy_reset(Z180.daisy);
z180_mmu();
z180_change_pc(_PCD);
}
/* Handle PRT timers, decreasing them after 20 clocks and returning the new icount base that needs to be used for the next check */
@ -2308,7 +2307,6 @@ static CPU_SET_CONTEXT( z180 )
{
if( src )
Z180 = *(Z180_Regs*)src;
z180_change_pc(_PCD);
}
#ifdef UNUSED_FUNCTION
@ -2374,7 +2372,7 @@ static CPU_SET_INFO( z180 )
case CPUINFO_INT_INPUT_STATE + Z180_INT1: set_irq_line(Z180_INT1, info->i); break;
case CPUINFO_INT_INPUT_STATE + Z180_INT2: set_irq_line(Z180_INT2, info->i); break;
case CPUINFO_INT_PC: _PC = info->i; z180_change_pc(_PCD); break;
case CPUINFO_INT_PC: _PC = info->i; break;
case CPUINFO_INT_REGISTER + Z180_PC: Z180.PC.w.l = info->i; break;
case CPUINFO_INT_SP: _SP = info->i; break;
case CPUINFO_INT_REGISTER + Z180_SP: Z180.SP.w.l = info->i; break;

2
src/emu/cpu/z180/z180dd.c
View File

@ -268,7 +268,7 @@ OP(dd,e6) { illegal_1(); op_e6(); } /* DB DD */
OP(dd,e7) { illegal_1(); op_e7(); } /* DB DD */
OP(dd,e8) { illegal_1(); op_e8(); } /* DB DD */
OP(dd,e9) { _R++; _PC = _IX; z180_change_pc(_PCD); } /* JP (IX) */
OP(dd,e9) { _R++; _PC = _IX; } /* JP (IX) */
OP(dd,ea) { illegal_1(); op_ea(); } /* DB DD */
OP(dd,eb) { illegal_1(); op_eb(); } /* DB DD */
OP(dd,ec) { illegal_1(); op_ec(); } /* DB DD */

2
src/emu/cpu/z180/z180fd.c
View File

@ -263,7 +263,7 @@ OP(fd,e6) { illegal_1(); op_e6(); } /* DB FD */
OP(fd,e7) { illegal_1(); op_e7(); } /* DB FD */
OP(fd,e8) { illegal_1(); op_e8(); } /* DB FD */
OP(fd,e9) { _R++; _PC = _IY; z180_change_pc(_PCD); } /* JP (IY) */
OP(fd,e9) { _R++; _PC = _IY; } /* JP (IY) */
OP(fd,ea) { illegal_1(); op_ea(); } /* DB FD */
OP(fd,eb) { illegal_1(); op_eb(); } /* DB FD */
OP(fd,ec) { illegal_1(); op_ec(); } /* DB FD */

7
src/emu/cpu/z180/z180op.c
View File

@ -229,7 +229,7 @@ OP(op,c6) { ADD(ARG()); } /* ADD A,n */
OP(op,c7) { RST(0x00); } /* RST 0 */
OP(op,c8) { RET_COND( _F & ZF, 0xc8 ); } /* RET Z */
OP(op,c9) { POP(PC); z180_change_pc(_PCD); } /* RET */
OP(op,c9) { POP(PC); } /* RET */
OP(op,ca) { JP_COND( _F & ZF ); } /* JP Z,a */
OP(op,cb) { _R++; EXEC(cb,ROP()); } /* **** CB xx */
OP(op,cc) { CALL_COND( _F & ZF, 0xcc ); } /* CALL Z,a */
@ -265,7 +265,7 @@ OP(op,e6) { AND(ARG()); } /* AND n */
OP(op,e7) { RST(0x20); } /* RST 4 */
OP(op,e8) { RET_COND( _F & PF, 0xe8 ); } /* RET PE */
OP(op,e9) { _PC = _HL; z180_change_pc(_PCD); } /* JP (HL) */
OP(op,e9) { _PC = _HL; } /* JP (HL) */
OP(op,ea) { JP_COND( _F & PF ); } /* JP PE,a */
OP(op,eb) { EX_DE_HL; } /* EX DE,HL */
OP(op,ec) { CALL_COND( _F & PF, 0xec ); } /* CALL PE,a */
@ -375,8 +375,5 @@ static void take_interrupt(int irq)
/* CALL opcode timing */
z180_icount -= cc[Z180_TABLE_op][0xcd];
}
z180_change_pc(_PCD);
}

16
src/emu/cpu/z180/z180ops.h
View File

@ -137,10 +137,8 @@ INLINE UINT32 ARG16(void)
/****************************************************************************
* Change program counter - MMU lookup
****************************************************************************/
#define z180_change_pc(addr) change_pc(MMU_REMAP_ADDR(addr))
void z180_setOPbase(int pc)
{
z180_change_pc(pc);
}
/***************************************************************
@ -165,7 +163,6 @@ void z180_setOPbase(int pc)
***************************************************************/
#define JP { \
_PCD = ARG16(); \
z180_change_pc(_PCD); \
}
/***************************************************************
@ -176,7 +173,6 @@ void z180_setOPbase(int pc)
if( cond ) \
{ \
_PCD = ARG16(); \
z180_change_pc(_PCD); \
} \
else \
{ \
@ -191,7 +187,6 @@ void z180_setOPbase(int pc)
unsigned oldpc = _PCD-1; \
INT8 arg = (INT8)ARG(); /* ARG() also increments _PC */ \
_PC += arg; /* so don't do _PC += ARG() */ \
z180_change_pc(_PCD); \
/* speed up busy loop */ \
if( _PCD == oldpc ) \
{ \
@ -231,7 +226,6 @@ void z180_setOPbase(int pc)
INT8 arg = (INT8)ARG(); /* ARG() also increments _PC */ \
_PC += arg; /* so don't do _PC += ARG() */ \
CC(ex,opcode); \
z180_change_pc(_PCD); \
} \
else _PC++; \
@ -241,8 +235,7 @@ void z180_setOPbase(int pc)
#define CALL() \
EA = ARG16(); \
PUSH( PC ); \
_PCD = EA; \
z180_change_pc(_PCD)
_PCD = EA;
/***************************************************************
* CALL_COND
@ -254,7 +247,6 @@ void z180_setOPbase(int pc)
PUSH( PC ); \
_PCD = EA; \
CC(ex,opcode); \
z180_change_pc(_PCD); \
} \
else \
{ \
@ -268,7 +260,6 @@ void z180_setOPbase(int pc)
if( cond ) \
{ \
POP(PC); \
z180_change_pc(_PCD); \
CC(ex,opcode); \
}
@ -278,7 +269,6 @@ void z180_setOPbase(int pc)
#define RETN { \
LOG(("Z180 #%d RETN IFF1:%d IFF2:%d\n", cpunum_get_active(), _IFF1, _IFF2)); \
POP(PC); \
z180_change_pc(_PCD); \
_IFF1 = _IFF2; \
}
@ -287,7 +277,6 @@ void z180_setOPbase(int pc)
***************************************************************/
#define RETI { \
POP(PC); \
z180_change_pc(_PCD); \
/* according to http://www.msxnet.org/tech/Z80/z80undoc.txt */ \
/* _IFF1 = _IFF2; */ \
if (Z180.daisy) \
@ -330,8 +319,7 @@ void z180_setOPbase(int pc)
***************************************************************/
#define RST(addr) \
PUSH( PC ); \
_PCD = addr; \
z180_change_pc(_PCD)
_PCD = addr;
/***************************************************************
* INC r8

23
src/emu/cpu/z80/z80.c
View File

@ -651,7 +651,6 @@ INLINE UINT32 ARG16(z80_state *z80)
#define JP(Z) do { \
(Z)->PCD = ARG16(Z); \
(Z)->MEMPTR = (Z)->PCD; \
change_pc((Z)->PCD); \
} while (0)
/***************************************************************
@ -662,7 +661,6 @@ INLINE UINT32 ARG16(z80_state *z80)
{ \
(Z)->PCD = ARG16(Z); \
(Z)->MEMPTR = (Z)->PCD; \
change_pc((Z)->PCD); \
} \
else \
{ \
@ -677,7 +675,6 @@ INLINE UINT32 ARG16(z80_state *z80)
INT8 arg = (INT8)ARG(Z); /* ARG() also increments PC */ \
(Z)->PC += arg; /* so don't do PC += ARG() */ \
(Z)->MEMPTR = (Z)->PC; \
change_pc((Z)->PCD); \
} while (0)
/***************************************************************
@ -700,7 +697,6 @@ INLINE UINT32 ARG16(z80_state *z80)
(Z)->MEMPTR = (Z)->ea; \
PUSH((Z), pc); \
(Z)->PCD = (Z)->ea; \
change_pc((Z)->PCD); \
} while (0)
/***************************************************************
@ -714,7 +710,6 @@ INLINE UINT32 ARG16(z80_state *z80)
PUSH((Z), pc); \
(Z)->PCD = (Z)->ea; \
CC(Z, ex, opcode); \
change_pc((Z)->PCD); \
} \
else \
{ \
@ -730,7 +725,6 @@ INLINE UINT32 ARG16(z80_state *z80)
{ \
POP((Z), pc); \
(Z)->MEMPTR = (Z)->PC; \
change_pc((Z)->PCD); \
CC(Z, ex, opcode); \
} \
} while (0)
@ -743,7 +737,6 @@ INLINE UINT32 ARG16(z80_state *z80)
(Z)->device->tag, (Z)->iff1, (Z)->iff2)); \
POP((Z), pc); \
(Z)->MEMPTR = (Z)->PC; \
change_pc((Z)->PCD); \
(Z)->iff1 = (Z)->iff2; \
} while (0)
@ -753,7 +746,6 @@ INLINE UINT32 ARG16(z80_state *z80)
#define RETI(Z) do { \
POP((Z), pc); \
(Z)->MEMPTR = (Z)->PC; \
change_pc((Z)->PCD); \
/* according to http://www.msxnet.org/tech/z80-documented.pdf */\
(Z)->iff1 = (Z)->iff2; \
if ((Z)->daisy != NULL) \
@ -798,7 +790,6 @@ INLINE UINT32 ARG16(z80_state *z80)
PUSH((Z), pc); \
(Z)->PCD = addr; \
(Z)->MEMPTR = (Z)->PC; \
change_pc((Z)->PCD); \
} while (0)
/***************************************************************
@ -2289,7 +2280,7 @@ OP(dd,e6) { illegal_1(z80); op_e6(z80); } /* DB DD */
OP(dd,e7) { illegal_1(z80); op_e7(z80); } /* DB DD */
OP(dd,e8) { illegal_1(z80); op_e8(z80); } /* DB DD */
OP(dd,e9) { z80->PC = z80->IX; change_pc(z80->PCD); } /* JP (IX) */
OP(dd,e9) { z80->PC = z80->IX; } /* JP (IX) */
OP(dd,ea) { illegal_1(z80); op_ea(z80); } /* DB DD */
OP(dd,eb) { illegal_1(z80); op_eb(z80); } /* DB DD */
OP(dd,ec) { illegal_1(z80); op_ec(z80); } /* DB DD */
@ -2580,7 +2571,7 @@ OP(fd,e6) { illegal_1(z80); op_e6(z80); } /* DB FD */
OP(fd,e7) { illegal_1(z80); op_e7(z80); } /* DB FD */
OP(fd,e8) { illegal_1(z80); op_e8(z80); } /* DB FD */
OP(fd,e9) { z80->PC = z80->IY; change_pc(z80->PCD); } /* JP (IY) */
OP(fd,e9) { z80->PC = z80->IY; } /* JP (IY) */
OP(fd,ea) { illegal_1(z80); op_ea(z80); } /* DB FD */
OP(fd,eb) { illegal_1(z80); op_eb(z80); } /* DB FD */
OP(fd,ec) { illegal_1(z80); op_ec(z80); } /* DB FD */
@ -3133,7 +3124,7 @@ OP(op,c6) { ADD(z80, ARG(z80)); } /* ADD A,n */
OP(op,c7) { RST(z80, 0x00); } /* RST 0 */
OP(op,c8) { RET_COND(z80, z80->F & ZF, 0xc8); } /* RET Z */
OP(op,c9) { POP(z80, pc); change_pc(z80->PCD); z80->MEMPTR=z80->PCD; } /* RET */
OP(op,c9) { POP(z80, pc); z80->MEMPTR=z80->PCD; } /* RET */
OP(op,ca) { JP_COND(z80, z80->F & ZF); } /* JP Z,a */
OP(op,cb) { z80->r++; EXEC(z80,cb,ROP(z80)); } /* **** CB xx */
OP(op,cc) { CALL_COND(z80, z80->F & ZF, 0xcc); } /* CALL Z,a */
@ -3169,7 +3160,7 @@ OP(op,e6) { AND(z80, ARG(z80)); } /* AND n */
OP(op,e7) { RST(z80, 0x20); } /* RST 4 */
OP(op,e8) { RET_COND(z80, z80->F & PF, 0xe8); } /* RET PE */
OP(op,e9) { z80->PC = z80->HL; change_pc(z80->PCD); } /* JP (HL) */
OP(op,e9) { z80->PC = z80->HL; } /* JP (HL) */
OP(op,ea) { JP_COND(z80, z80->F & PF); } /* JP PE,a */
OP(op,eb) { EX_DE_HL(z80); } /* EX DE,HL */
OP(op,ec) { CALL_COND(z80, z80->F & PF, 0xec); } /* CALL PE,a */
@ -3266,7 +3257,6 @@ static void take_interrupt(z80_state *z80)
break;
}
}
change_pc(z80->PCD);
z80->MEMPTR=z80->PCD;
}
@ -3425,7 +3415,6 @@ static CPU_RESET( z80 )
if (z80->daisy)
z80daisy_reset(z80->daisy);
change_pc(z80->PCD);
z80->MEMPTR=z80->PCD;
}
@ -3445,7 +3434,6 @@ static CPU_EXECUTE( z80 )
z80_state *z80 = device->token;
z80->icount = cycles;
change_pc(z80->PCD);
/* check for NMIs on the way in; they can only be set externally */
/* via timers, and can't be dynamically enabled, so it is safe */
@ -3459,7 +3447,6 @@ static CPU_EXECUTE( z80 )
z80->iff1 = 0;
PUSH(z80, pc);
z80->PCD = 0x0066;
change_pc(z80->PCD);
z80->MEMPTR=z80->PCD;
z80->icount -= 11;
z80->nmi_pending = FALSE;
@ -3549,7 +3536,7 @@ static CPU_SET_INFO( z80 )
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(z80, INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(z80, 0, info->i); break;
case CPUINFO_INT_PC: z80->PC = info->i; change_pc(z80->PCD); break;
case CPUINFO_INT_PC: z80->PC = info->i; break;
case CPUINFO_INT_REGISTER + Z80_PC: z80->PC = info->i; break;
case CPUINFO_INT_SP: z80->SP = info->i; break;
case CPUINFO_INT_REGISTER + Z80_SP: z80->SP = info->i; break;

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