mirror of
https://github.com/holub/mame
synced 2025-05-24 23:05:32 +03:00
Pointer-ified the lr35902 core.
This commit is contained in:
Aaron Giles
parent
5f39c19227
commit
540f1eefb4
@ -45,9 +45,9 @@
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#define FLAG_H 0x20
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#define FLAG_C 0x10
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#define CYCLES_PASSED(X) lr35902_ICount -= ((X) / (Regs.w.gb_speed)); \
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if ( Regs.w.timer_fired_func ) { \
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Regs.w.timer_fired_func( X ); \
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#define CYCLES_PASSED(X) cpustate->w.icount -= ((X) / (cpustate->w.gb_speed)); \
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if ( cpustate->w.timer_fired_func ) { \
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cpustate->w.timer_fired_func( cpustate->w.device, X ); \
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}
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typedef struct {
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@ -66,8 +66,9 @@ typedef struct {
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cpu_irq_callback irq_callback;
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const device_config *device;
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const address_space *program;
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int icount;
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/* Timer stuff */
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void (*timer_fired_func)(int cycles);
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lr35902_timer_fired_func timer_fired_func;
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/* Fetch & execute related */
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int execution_state;
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UINT8 op;
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@ -105,14 +106,14 @@ typedef struct {
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} lr35902_8BitRegs;
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#endif
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typedef union {
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typedef union _lr35902_state lr35902_state;
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union _lr35902_state {
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lr35902_16BitRegs w;
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lr35902_8BitRegs b;
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} lr35902_regs;
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};
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typedef int (*OpcodeEmulator) (void);
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static lr35902_regs Regs;
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typedef int (*OpcodeEmulator) (lr35902_state *cpustate);
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#define IME 0x01
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#define HALTED 0x02
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@ -121,25 +122,22 @@ static lr35902_regs Regs;
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/* Memory functions */
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/****************************************************************************/
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#define mem_ReadByte(A) ((UINT8)memory_read_byte_8le(Regs.w.program,A))
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#define mem_WriteByte(A,V) (memory_write_byte_8le(Regs.w.program,A,V))
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#define mem_ReadByte(cs,A) ((UINT8)memory_read_byte_8le((cs)->w.program,A))
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#define mem_WriteByte(cs,A,V) (memory_write_byte_8le((cs)->w.program,A,V))
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INLINE UINT16 mem_ReadWord (UINT32 address)
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INLINE UINT16 mem_ReadWord (lr35902_state *cpustate, UINT32 address)
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{
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UINT16 value = (UINT16) mem_ReadByte ((address + 1) & 0xffff) << 8;
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value |= mem_ReadByte (address);
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UINT16 value = (UINT16) mem_ReadByte (cpustate, (address + 1) & 0xffff) << 8;
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value |= mem_ReadByte (cpustate, address);
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return value;
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}
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INLINE void mem_WriteWord (UINT32 address, UINT16 value)
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INLINE void mem_WriteWord (lr35902_state *cpustate, UINT32 address, UINT16 value)
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{
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mem_WriteByte (address, value & 0xFF);
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mem_WriteByte ((address + 1) & 0xffff, value >> 8);
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mem_WriteByte (cpustate, address, value & 0xFF);
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mem_WriteByte (cpustate, (address + 1) & 0xffff, value >> 8);
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}
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/* Nr of cycles to run */
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static int lr35902_ICount;
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static const int Cycles[256] =
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{
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4,12, 8, 8, 4, 4, 8, 4,20, 8, 8, 8, 4, 4, 8, 4,
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@ -182,65 +180,69 @@ static const int CyclesCB[256] =
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static CPU_INIT( lr35902 )
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{
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Regs.w.config = (const lr35902_cpu_core *) device->static_config;
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Regs.w.irq_callback = irqcallback;
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Regs.w.device = device;
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Regs.w.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
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lr35902_state *cpustate = device->token;
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cpustate->w.config = (const lr35902_cpu_core *) device->static_config;
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cpustate->w.irq_callback = irqcallback;
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cpustate->w.device = device;
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cpustate->w.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
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}
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/*** Reset lr353902 registers: ******************************/
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/*** This function can be used to reset the register ***/
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/*** file before starting execution with lr35902_execute()***/
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/*** file before starting execution with lr35902_execute(cpustate)***/
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/*** It sets the registers to their initial values. ***/
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/************************************************************/
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static CPU_RESET( lr35902 )
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{
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Regs.w.AF = 0x0000;
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Regs.w.BC = 0x0000;
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Regs.w.DE = 0x0000;
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Regs.w.HL = 0x0000;
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Regs.w.SP = 0x0000;
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Regs.w.PC = 0x0000;
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Regs.w.timer_fired_func = NULL;
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Regs.w.features = LR35902_FEATURE_HALT_BUG;
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if (Regs.w.config)
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{
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if ( Regs.w.config->regs ) {
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Regs.w.AF = Regs.w.config->regs[0];
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Regs.w.BC = Regs.w.config->regs[1];
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Regs.w.DE = Regs.w.config->regs[2];
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Regs.w.HL = Regs.w.config->regs[3];
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Regs.w.SP = Regs.w.config->regs[4];
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Regs.w.PC = Regs.w.config->regs[5];
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}
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Regs.w.timer_fired_func = Regs.w.config->timer_fired_func;
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Regs.w.features = Regs.w.config->features;
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}
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Regs.w.enable = 0;
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Regs.w.IE = 0;
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Regs.w.IF = 0;
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lr35902_state *cpustate = device->token;
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Regs.w.execution_state = 0;
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Regs.w.doHALTbug = 0;
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Regs.w.ei_delay = 0;
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Regs.w.gb_speed_change_pending = 0;
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Regs.w.gb_speed = 1;
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cpustate->w.AF = 0x0000;
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cpustate->w.BC = 0x0000;
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cpustate->w.DE = 0x0000;
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cpustate->w.HL = 0x0000;
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cpustate->w.SP = 0x0000;
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cpustate->w.PC = 0x0000;
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cpustate->w.timer_fired_func = NULL;
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cpustate->w.features = LR35902_FEATURE_HALT_BUG;
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if (cpustate->w.config)
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{
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if ( cpustate->w.config->regs ) {
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cpustate->w.AF = cpustate->w.config->regs[0];
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cpustate->w.BC = cpustate->w.config->regs[1];
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cpustate->w.DE = cpustate->w.config->regs[2];
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cpustate->w.HL = cpustate->w.config->regs[3];
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cpustate->w.SP = cpustate->w.config->regs[4];
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cpustate->w.PC = cpustate->w.config->regs[5];
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}
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cpustate->w.timer_fired_func = cpustate->w.config->timer_fired_func;
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cpustate->w.features = cpustate->w.config->features;
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}
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cpustate->w.enable = 0;
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cpustate->w.IE = 0;
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cpustate->w.IF = 0;
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cpustate->w.execution_state = 0;
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cpustate->w.doHALTbug = 0;
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cpustate->w.ei_delay = 0;
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cpustate->w.gb_speed_change_pending = 0;
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cpustate->w.gb_speed = 1;
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}
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INLINE void lr35902_ProcessInterrupts (void)
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INLINE void lr35902_ProcessInterrupts (lr35902_state *cpustate)
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{
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UINT8 irq = Regs.w.IE & Regs.w.IF;
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UINT8 irq = cpustate->w.IE & cpustate->w.IF;
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/* Interrupts should be taken after the first instruction after an EI instruction */
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if (Regs.w.ei_delay) {
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Regs.w.ei_delay = 0;
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if (cpustate->w.ei_delay) {
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cpustate->w.ei_delay = 0;
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return;
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}
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/*
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logerror("Attempting to process LR35902 Interrupt IRQ $%02X\n", irq);
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logerror("Attempting to process LR35902 Interrupt IE $%02X\n", Regs.w.IE);
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logerror("Attempting to process LR35902 Interrupt IF $%02X\n", Regs.w.IF);
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logerror("Attempting to process LR35902 Interrupt IE $%02X\n", cpustate->w.IE);
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logerror("Attempting to process LR35902 Interrupt IF $%02X\n", cpustate->w.IF);
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*/
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if (irq)
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{
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@ -253,17 +255,17 @@ INLINE void lr35902_ProcessInterrupts (void)
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{
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if( irq & (1<<irqline) )
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{
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if (Regs.w.enable & HALTED)
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if (cpustate->w.enable & HALTED)
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{
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Regs.w.enable &= ~HALTED;
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Regs.w.IF &= ~(1 << irqline);
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Regs.w.PC++;
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if ( Regs.w.features & LR35902_FEATURE_HALT_BUG ) {
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if ( ! Regs.w.enable & IME ) {
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cpustate->w.enable &= ~HALTED;
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cpustate->w.IF &= ~(1 << irqline);
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cpustate->w.PC++;
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if ( cpustate->w.features & LR35902_FEATURE_HALT_BUG ) {
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if ( ! cpustate->w.enable & IME ) {
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/* Old cpu core (dmg/mgb/sgb) */
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/* check if the HALT bug should be performed */
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if ( Regs.w.haltIFstatus ) {
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Regs.w.doHALTbug = 1;
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if ( cpustate->w.haltIFstatus ) {
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cpustate->w.doHALTbug = 1;
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}
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}
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} else {
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@ -275,16 +277,16 @@ INLINE void lr35902_ProcessInterrupts (void)
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}
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}
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}
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if ( Regs.w.enable & IME ) {
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if ( Regs.w.irq_callback )
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(*Regs.w.irq_callback)(Regs.w.device, irqline);
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Regs.w.enable &= ~IME;
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Regs.w.IF &= ~(1 << irqline);
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if ( cpustate->w.enable & IME ) {
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if ( cpustate->w.irq_callback )
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(*cpustate->w.irq_callback)(cpustate->w.device, irqline);
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cpustate->w.enable &= ~IME;
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cpustate->w.IF &= ~(1 << irqline);
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CYCLES_PASSED( 20 );
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Regs.w.SP -= 2;
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mem_WriteWord (Regs.w.SP, Regs.w.PC);
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Regs.w.PC = 0x40 + irqline * 8;
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/*logerror("LR35902 Interrupt PC $%04X\n", Regs.w.PC );*/
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cpustate->w.SP -= 2;
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mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC);
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cpustate->w.PC = 0x40 + irqline * 8;
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/*logerror("LR35902 Interrupt PC $%04X\n", cpustate->w.PC );*/
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return;
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}
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}
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@ -298,100 +300,86 @@ INLINE void lr35902_ProcessInterrupts (void)
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/************************************************************/
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static CPU_EXECUTE( lr35902 )
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{
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lr35902_ICount = cycles;
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lr35902_state *cpustate = device->token;
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cpustate->w.icount = cycles;
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do
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{
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if ( Regs.w.execution_state ) {
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if ( cpustate->w.execution_state ) {
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UINT8 x;
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/* Execute instruction */
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switch( Regs.w.op ) {
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switch( cpustate->w.op ) {
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#include "opc_main.h"
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}
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} else {
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/* Fetch and count cycles */
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lr35902_ProcessInterrupts ();
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debugger_instruction_hook(device, Regs.w.PC);
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if ( Regs.w.enable & HALTED ) {
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lr35902_ProcessInterrupts (cpustate);
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debugger_instruction_hook(device, cpustate->w.PC);
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if ( cpustate->w.enable & HALTED ) {
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CYCLES_PASSED( Cycles[0x76] );
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Regs.w.execution_state = 1;
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cpustate->w.execution_state = 1;
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} else {
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Regs.w.op = mem_ReadByte (Regs.w.PC++);
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if ( Regs.w.doHALTbug ) {
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Regs.w.PC--;
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Regs.w.doHALTbug = 0;
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cpustate->w.op = mem_ReadByte (cpustate, cpustate->w.PC++);
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if ( cpustate->w.doHALTbug ) {
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cpustate->w.PC--;
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cpustate->w.doHALTbug = 0;
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}
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CYCLES_PASSED( Cycles[Regs.w.op] );
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CYCLES_PASSED( Cycles[cpustate->w.op] );
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}
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}
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Regs.w.execution_state ^= 1;
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} while (lr35902_ICount > 0);
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cpustate->w.execution_state ^= 1;
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} while (cpustate->w.icount > 0);
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return cycles - lr35902_ICount;
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return cycles - cpustate->w.icount;
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}
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static CPU_BURN( lr35902 )
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{
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lr35902_state *cpustate = device->token;
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if( cycles > 0 )
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{
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/* NOP takes 4 cycles per instruction */
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int n = (cycles + 3) / 4;
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lr35902_ICount -= 4 * n;
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cpustate->w.icount -= 4 * n;
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}
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}
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/****************************************************************************/
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/* Set all registers to given values */
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/****************************************************************************/
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static CPU_SET_CONTEXT( lr35902 )
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{
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if( src )
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Regs = *(lr35902_regs *)src;
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}
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/****************************************************************************/
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/* Get all registers in given buffer */
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/****************************************************************************/
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static CPU_GET_CONTEXT( lr35902 )
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{
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if( dst )
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*(lr35902_regs *)dst = Regs;
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}
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static void lr35902_set_irq_line (int irqline, int state)
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static void lr35902_set_irq_line (lr35902_state *cpustate, int irqline, int state)
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{
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/*logerror("setting irq line 0x%02x state 0x%08x\n", irqline, state);*/
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//if( Regs.w.irq_state == state )
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//if( cpustate->w.irq_state == state )
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// return;
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Regs.w.irq_state = state;
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cpustate->w.irq_state = state;
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if( state == ASSERT_LINE )
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{
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Regs.w.IF |= (0x01 << irqline);
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/*logerror("LR35902 assert irq line %d ($%02X)\n", irqline, Regs.w.IF);*/
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cpustate->w.IF |= (0x01 << irqline);
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/*logerror("LR35902 assert irq line %d ($%02X)\n", irqline, cpustate->w.IF);*/
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}
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else
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{
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Regs.w.IF &= ~(0x01 << irqline);
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/*logerror("LR35902 clear irq line %d ($%02X)\n", irqline, Regs.w.IF);*/
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cpustate->w.IF &= ~(0x01 << irqline);
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/*logerror("LR35902 clear irq line %d ($%02X)\n", irqline, cpustate->w.IF);*/
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}
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}
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#ifdef UNUSED_FUNCTION
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static void lr35902_clear_pending_interrupts (void)
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static void lr35902_clear_pending_interrupts (lr35902_state *cpustate)
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{
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Regs.w.IF = 0;
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cpustate->w.IF = 0;
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}
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#endif
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static CPU_SET_INFO( lr35902 )
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{
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lr35902_state *cpustate = device->token;
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switch (state)
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{
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/* --- the following bits of info are set as 64-bit signed integers --- */
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@ -399,29 +387,31 @@ static CPU_SET_INFO( lr35902 )
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case CPUINFO_INT_INPUT_STATE + 1:
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case CPUINFO_INT_INPUT_STATE + 2:
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case CPUINFO_INT_INPUT_STATE + 3:
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case CPUINFO_INT_INPUT_STATE + 4: lr35902_set_irq_line(state-CPUINFO_INT_INPUT_STATE, info->i); break;
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case CPUINFO_INT_INPUT_STATE + 4: lr35902_set_irq_line(cpustate, state-CPUINFO_INT_INPUT_STATE, info->i); break;
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case CPUINFO_INT_SP: Regs.w.SP = info->i; break;
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case CPUINFO_INT_PC: Regs.w.PC = info->i; break;
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case CPUINFO_INT_SP: cpustate->w.SP = info->i; break;
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case CPUINFO_INT_PC: cpustate->w.PC = info->i; break;
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case CPUINFO_INT_REGISTER + LR35902_PC: Regs.w.PC = info->i; break;
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case CPUINFO_INT_REGISTER + LR35902_SP: Regs.w.SP = info->i; break;
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case CPUINFO_INT_REGISTER + LR35902_AF: Regs.w.AF = info->i; break;
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case CPUINFO_INT_REGISTER + LR35902_BC: Regs.w.BC = info->i; break;
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case CPUINFO_INT_REGISTER + LR35902_DE: Regs.w.DE = info->i; break;
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case CPUINFO_INT_REGISTER + LR35902_HL: Regs.w.HL = info->i; break;
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case CPUINFO_INT_REGISTER + LR35902_IE: Regs.w.IE = info->i; break;
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case CPUINFO_INT_REGISTER + LR35902_IF: Regs.w.IF = info->i; break;
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case CPUINFO_INT_REGISTER + LR35902_SPEED: Regs.w.gb_speed_change_pending = info->i & 0x01; break;
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case CPUINFO_INT_REGISTER + LR35902_PC: cpustate->w.PC = info->i; break;
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case CPUINFO_INT_REGISTER + LR35902_SP: cpustate->w.SP = info->i; break;
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case CPUINFO_INT_REGISTER + LR35902_AF: cpustate->w.AF = info->i; break;
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case CPUINFO_INT_REGISTER + LR35902_BC: cpustate->w.BC = info->i; break;
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case CPUINFO_INT_REGISTER + LR35902_DE: cpustate->w.DE = info->i; break;
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case CPUINFO_INT_REGISTER + LR35902_HL: cpustate->w.HL = info->i; break;
|
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case CPUINFO_INT_REGISTER + LR35902_IE: cpustate->w.IE = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + LR35902_IF: cpustate->w.IF = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + LR35902_SPEED: cpustate->w.gb_speed_change_pending = info->i & 0x01; break;
|
||||
}
|
||||
}
|
||||
|
||||
CPU_GET_INFO( lr35902 )
|
||||
{
|
||||
lr35902_state *cpustate = (device != NULL) ? device->token : NULL;
|
||||
|
||||
switch (state)
|
||||
{
|
||||
/* --- the following bits of info are returned as 64-bit signed integers --- */
|
||||
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(Regs); break;
|
||||
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(lr35902_state); break;
|
||||
case CPUINFO_INT_INPUT_LINES: info->i = 5; break;
|
||||
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0xff; break;
|
||||
case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
|
||||
@ -442,36 +432,36 @@ CPU_GET_INFO( lr35902 )
|
||||
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 16; break;
|
||||
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
|
||||
|
||||
case CPUINFO_INT_SP: info->i = Regs.w.SP; break;
|
||||
case CPUINFO_INT_PC: info->i = Regs.w.PC; break;
|
||||
case CPUINFO_INT_SP: info->i = cpustate->w.SP; break;
|
||||
case CPUINFO_INT_PC: info->i = cpustate->w.PC; break;
|
||||
case CPUINFO_INT_PREVIOUSPC: info->i = 0; /* TODO??? */ break;
|
||||
|
||||
case CPUINFO_INT_INPUT_STATE + 0:
|
||||
case CPUINFO_INT_INPUT_STATE + 1:
|
||||
case CPUINFO_INT_INPUT_STATE + 2:
|
||||
case CPUINFO_INT_INPUT_STATE + 3:
|
||||
case CPUINFO_INT_INPUT_STATE + 4: info->i = Regs.w.IF & (1 << (state-CPUINFO_INT_INPUT_STATE)); break;
|
||||
case CPUINFO_INT_INPUT_STATE + 4: info->i = cpustate->w.IF & (1 << (state-CPUINFO_INT_INPUT_STATE)); break;
|
||||
|
||||
case CPUINFO_INT_REGISTER + LR35902_PC: info->i = Regs.w.PC; break;
|
||||
case CPUINFO_INT_REGISTER + LR35902_SP: info->i = Regs.w.SP; break;
|
||||
case CPUINFO_INT_REGISTER + LR35902_AF: info->i = Regs.w.AF; break;
|
||||
case CPUINFO_INT_REGISTER + LR35902_BC: info->i = Regs.w.BC; break;
|
||||
case CPUINFO_INT_REGISTER + LR35902_DE: info->i = Regs.w.DE; break;
|
||||
case CPUINFO_INT_REGISTER + LR35902_HL: info->i = Regs.w.HL; break;
|
||||
case CPUINFO_INT_REGISTER + LR35902_IE: info->i = Regs.w.IE; break;
|
||||
case CPUINFO_INT_REGISTER + LR35902_IF: info->i = Regs.w.IF; break;
|
||||
case CPUINFO_INT_REGISTER + LR35902_SPEED: info->i = 0x7E | ( ( Regs.w.gb_speed - 1 ) << 7 ) | Regs.w.gb_speed_change_pending; break;
|
||||
case CPUINFO_INT_REGISTER + LR35902_PC: info->i = cpustate->w.PC; break;
|
||||
case CPUINFO_INT_REGISTER + LR35902_SP: info->i = cpustate->w.SP; break;
|
||||
case CPUINFO_INT_REGISTER + LR35902_AF: info->i = cpustate->w.AF; break;
|
||||
case CPUINFO_INT_REGISTER + LR35902_BC: info->i = cpustate->w.BC; break;
|
||||
case CPUINFO_INT_REGISTER + LR35902_DE: info->i = cpustate->w.DE; break;
|
||||
case CPUINFO_INT_REGISTER + LR35902_HL: info->i = cpustate->w.HL; break;
|
||||
case CPUINFO_INT_REGISTER + LR35902_IE: info->i = cpustate->w.IE; break;
|
||||
case CPUINFO_INT_REGISTER + LR35902_IF: info->i = cpustate->w.IF; break;
|
||||
case CPUINFO_INT_REGISTER + LR35902_SPEED: info->i = 0x7E | ( ( cpustate->w.gb_speed - 1 ) << 7 ) | cpustate->w.gb_speed_change_pending; break;
|
||||
|
||||
/* --- the following bits of info are returned as pointers to data or functions --- */
|
||||
case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(lr35902); break;
|
||||
case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(lr35902); break;
|
||||
case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(lr35902); break;
|
||||
case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(dummy); break;
|
||||
case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(dummy); break;
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(lr35902); break;
|
||||
case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(lr35902); break;
|
||||
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(lr35902); break;
|
||||
case CPUINFO_PTR_BURN: info->burn = CPU_BURN_NAME(lr35902); break;
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(lr35902); break;
|
||||
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &lr35902_ICount; break;
|
||||
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->w.icount; break;
|
||||
|
||||
/* --- the following bits of info are returned as NULL-terminated strings --- */
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "LR35902"); break;
|
||||
@ -482,24 +472,24 @@ CPU_GET_INFO( lr35902 )
|
||||
|
||||
case CPUINFO_STR_FLAGS:
|
||||
sprintf(info->s, "%c%c%c%c%c%c%c%c",
|
||||
Regs.b.F & 0x80 ? 'Z':'.',
|
||||
Regs.b.F & 0x40 ? 'N':'.',
|
||||
Regs.b.F & 0x20 ? 'H':'.',
|
||||
Regs.b.F & 0x10 ? 'C':'.',
|
||||
Regs.b.F & 0x08 ? '3':'.',
|
||||
Regs.b.F & 0x04 ? '2':'.',
|
||||
Regs.b.F & 0x02 ? '1':'.',
|
||||
Regs.b.F & 0x01 ? '0':'.');
|
||||
cpustate->b.F & 0x80 ? 'Z':'.',
|
||||
cpustate->b.F & 0x40 ? 'N':'.',
|
||||
cpustate->b.F & 0x20 ? 'H':'.',
|
||||
cpustate->b.F & 0x10 ? 'C':'.',
|
||||
cpustate->b.F & 0x08 ? '3':'.',
|
||||
cpustate->b.F & 0x04 ? '2':'.',
|
||||
cpustate->b.F & 0x02 ? '1':'.',
|
||||
cpustate->b.F & 0x01 ? '0':'.');
|
||||
break;
|
||||
|
||||
case CPUINFO_STR_REGISTER + LR35902_PC: sprintf(info->s, "PC:%04X", Regs.w.PC); break;
|
||||
case CPUINFO_STR_REGISTER + LR35902_SP: sprintf(info->s, "SP:%04X", Regs.w.SP); break;
|
||||
case CPUINFO_STR_REGISTER + LR35902_AF: sprintf(info->s, "AF:%04X", Regs.w.AF); break;
|
||||
case CPUINFO_STR_REGISTER + LR35902_BC: sprintf(info->s, "BC:%04X", Regs.w.BC); break;
|
||||
case CPUINFO_STR_REGISTER + LR35902_DE: sprintf(info->s, "DE:%04X", Regs.w.DE); break;
|
||||
case CPUINFO_STR_REGISTER + LR35902_HL: sprintf(info->s, "HL:%04X", Regs.w.HL); break;
|
||||
case CPUINFO_STR_REGISTER + LR35902_IRQ_STATE: sprintf(info->s, "IRQ:%X", Regs.w.enable & IME ); break;
|
||||
case CPUINFO_STR_REGISTER + LR35902_IE: sprintf(info->s, "IE:%02X", Regs.w.IE); break;
|
||||
case CPUINFO_STR_REGISTER + LR35902_IF: sprintf(info->s, "IF:%02X", Regs.w.IF); break;
|
||||
case CPUINFO_STR_REGISTER + LR35902_PC: sprintf(info->s, "PC:%04X", cpustate->w.PC); break;
|
||||
case CPUINFO_STR_REGISTER + LR35902_SP: sprintf(info->s, "SP:%04X", cpustate->w.SP); break;
|
||||
case CPUINFO_STR_REGISTER + LR35902_AF: sprintf(info->s, "AF:%04X", cpustate->w.AF); break;
|
||||
case CPUINFO_STR_REGISTER + LR35902_BC: sprintf(info->s, "BC:%04X", cpustate->w.BC); break;
|
||||
case CPUINFO_STR_REGISTER + LR35902_DE: sprintf(info->s, "DE:%04X", cpustate->w.DE); break;
|
||||
case CPUINFO_STR_REGISTER + LR35902_HL: sprintf(info->s, "HL:%04X", cpustate->w.HL); break;
|
||||
case CPUINFO_STR_REGISTER + LR35902_IRQ_STATE: sprintf(info->s, "IRQ:%X", cpustate->w.enable & IME ); break;
|
||||
case CPUINFO_STR_REGISTER + LR35902_IE: sprintf(info->s, "IE:%02X", cpustate->w.IE); break;
|
||||
case CPUINFO_STR_REGISTER + LR35902_IF: sprintf(info->s, "IF:%02X", cpustate->w.IF); break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -5,12 +5,14 @@
|
||||
|
||||
#include "cpuintrf.h"
|
||||
|
||||
typedef void (*lr35902_timer_fired_func)(const device_config *device, int cycles);
|
||||
|
||||
typedef struct _lr35902_cpu_core lr35902_cpu_core;
|
||||
struct _lr35902_cpu_core
|
||||
{
|
||||
const UINT16 *regs;
|
||||
UINT8 features;
|
||||
void (*timer_fired_func)(int cycles);
|
||||
lr35902_timer_fired_func timer_fired_func;
|
||||
};
|
||||
|
||||
enum
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user